1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32F %s 4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64F %s 6; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \ 7; RUN: | FileCheck -check-prefix=RV32F %s 8; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \ 9; RUN: | FileCheck -check-prefix=RV64F %s 10 11@gf = external global float 12 13define float @constraint_f_float(float %a) nounwind { 14; RV32F-LABEL: constraint_f_float: 15; RV32F: # %bb.0: 16; RV32F-NEXT: lui a1, %hi(gf) 17; RV32F-NEXT: flw fa5, %lo(gf)(a1) 18; RV32F-NEXT: fmv.w.x fa4, a0 19; RV32F-NEXT: #APP 20; RV32F-NEXT: fadd.s fa5, fa4, fa5 21; RV32F-NEXT: #NO_APP 22; RV32F-NEXT: fmv.x.w a0, fa5 23; RV32F-NEXT: ret 24; 25; RV64F-LABEL: constraint_f_float: 26; RV64F: # %bb.0: 27; RV64F-NEXT: lui a1, %hi(gf) 28; RV64F-NEXT: flw fa5, %lo(gf)(a1) 29; RV64F-NEXT: fmv.w.x fa4, a0 30; RV64F-NEXT: #APP 31; RV64F-NEXT: fadd.s fa5, fa4, fa5 32; RV64F-NEXT: #NO_APP 33; RV64F-NEXT: fmv.x.w a0, fa5 34; RV64F-NEXT: ret 35 %1 = load float, ptr @gf 36 %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1) 37 ret float %2 38} 39 40define float @constraint_cf_float(float %a) nounwind { 41; RV32F-LABEL: constraint_cf_float: 42; RV32F: # %bb.0: 43; RV32F-NEXT: lui a1, %hi(gf) 44; RV32F-NEXT: flw fa5, %lo(gf)(a1) 45; RV32F-NEXT: fmv.w.x fa4, a0 46; RV32F-NEXT: #APP 47; RV32F-NEXT: fadd.s fa5, fa4, fa5 48; RV32F-NEXT: #NO_APP 49; RV32F-NEXT: fmv.x.w a0, fa5 50; RV32F-NEXT: ret 51; 52; RV64F-LABEL: constraint_cf_float: 53; RV64F: # %bb.0: 54; RV64F-NEXT: lui a1, %hi(gf) 55; RV64F-NEXT: flw fa5, %lo(gf)(a1) 56; RV64F-NEXT: fmv.w.x fa4, a0 57; RV64F-NEXT: #APP 58; RV64F-NEXT: fadd.s fa5, fa4, fa5 59; RV64F-NEXT: #NO_APP 60; RV64F-NEXT: fmv.x.w a0, fa5 61; RV64F-NEXT: ret 62 %1 = load float, ptr @gf 63 %2 = tail call float asm "fadd.s $0, $1, $2", "=^cf,cf,cf"(float %a, float %1) 64 ret float %2 65} 66 67define float @constraint_f_float_abi_name(float %a) nounwind { 68; RV32F-LABEL: constraint_f_float_abi_name: 69; RV32F: # %bb.0: 70; RV32F-NEXT: lui a1, %hi(gf) 71; RV32F-NEXT: flw fs0, %lo(gf)(a1) 72; RV32F-NEXT: fmv.w.x fa0, a0 73; RV32F-NEXT: #APP 74; RV32F-NEXT: fadd.s ft0, fa0, fs0 75; RV32F-NEXT: #NO_APP 76; RV32F-NEXT: fmv.x.w a0, ft0 77; RV32F-NEXT: ret 78; 79; RV64F-LABEL: constraint_f_float_abi_name: 80; RV64F: # %bb.0: 81; RV64F-NEXT: lui a1, %hi(gf) 82; RV64F-NEXT: flw fs0, %lo(gf)(a1) 83; RV64F-NEXT: fmv.w.x fa0, a0 84; RV64F-NEXT: #APP 85; RV64F-NEXT: fadd.s ft0, fa0, fs0 86; RV64F-NEXT: #NO_APP 87; RV64F-NEXT: fmv.x.w a0, ft0 88; RV64F-NEXT: ret 89 %1 = load float, ptr @gf 90 %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1) 91 ret float %2 92} 93 94define float @constraint_gpr(float %x) { 95; RV32F-LABEL: constraint_gpr: 96; RV32F: # %bb.0: 97; RV32F-NEXT: #APP 98; RV32F-NEXT: mv a0, a0 99; RV32F-NEXT: #NO_APP 100; RV32F-NEXT: ret 101; 102; RV64F-LABEL: constraint_gpr: 103; RV64F: # %bb.0: 104; RV64F-NEXT: #APP 105; RV64F-NEXT: mv a0, a0 106; RV64F-NEXT: #NO_APP 107; RV64F-NEXT: ret 108 %1 = tail call float asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(float %x) 109 ret float %1 110} 111