1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \ 3; RUN: | FileCheck -check-prefix=RV32F %s 4; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \ 5; RUN: | FileCheck -check-prefix=RV64F %s 6 7;; `.insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is 8;; the raw encoding for `fadd.d` 9 10@gd = external global double 11 12define double @constraint_f_double(double %a) nounwind { 13; RV32F-LABEL: constraint_f_double: 14; RV32F: # %bb.0: 15; RV32F-NEXT: addi sp, sp, -16 16; RV32F-NEXT: sw a0, 8(sp) 17; RV32F-NEXT: sw a1, 12(sp) 18; RV32F-NEXT: lui a0, %hi(gd) 19; RV32F-NEXT: fld fa5, 8(sp) 20; RV32F-NEXT: fld fa4, %lo(gd)(a0) 21; RV32F-NEXT: #APP 22; RV32F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (15 << 15) | (14 << 20) 23; RV32F-NEXT: #NO_APP 24; RV32F-NEXT: fsd fa5, 8(sp) 25; RV32F-NEXT: lw a0, 8(sp) 26; RV32F-NEXT: lw a1, 12(sp) 27; RV32F-NEXT: addi sp, sp, 16 28; RV32F-NEXT: ret 29; 30; RV64F-LABEL: constraint_f_double: 31; RV64F: # %bb.0: 32; RV64F-NEXT: lui a1, %hi(gd) 33; RV64F-NEXT: fld fa5, %lo(gd)(a1) 34; RV64F-NEXT: fmv.d.x fa4, a0 35; RV64F-NEXT: #APP 36; RV64F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (14 << 15) | (15 << 20) 37; RV64F-NEXT: #NO_APP 38; RV64F-NEXT: fmv.x.d a0, fa5 39; RV64F-NEXT: ret 40 %1 = load double, ptr @gd 41 %2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(double %a, double %1) 42 ret double %2 43} 44 45define double @constraint_cf_double(double %a) nounwind { 46; RV32F-LABEL: constraint_cf_double: 47; RV32F: # %bb.0: 48; RV32F-NEXT: addi sp, sp, -16 49; RV32F-NEXT: sw a0, 8(sp) 50; RV32F-NEXT: sw a1, 12(sp) 51; RV32F-NEXT: lui a0, %hi(gd) 52; RV32F-NEXT: fld fa5, 8(sp) 53; RV32F-NEXT: fld fa4, %lo(gd)(a0) 54; RV32F-NEXT: #APP 55; RV32F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (15 << 15) | (14 << 20) 56; RV32F-NEXT: #NO_APP 57; RV32F-NEXT: fsd fa5, 8(sp) 58; RV32F-NEXT: lw a0, 8(sp) 59; RV32F-NEXT: lw a1, 12(sp) 60; RV32F-NEXT: addi sp, sp, 16 61; RV32F-NEXT: ret 62; 63; RV64F-LABEL: constraint_cf_double: 64; RV64F: # %bb.0: 65; RV64F-NEXT: lui a1, %hi(gd) 66; RV64F-NEXT: fld fa5, %lo(gd)(a1) 67; RV64F-NEXT: fmv.d.x fa4, a0 68; RV64F-NEXT: #APP 69; RV64F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (14 << 15) | (15 << 20) 70; RV64F-NEXT: #NO_APP 71; RV64F-NEXT: fmv.x.d a0, fa5 72; RV64F-NEXT: ret 73 %1 = load double, ptr @gd 74 %2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(double %a, double %1) 75 ret double %2 76} 77 78define double @constraint_f_double_abi_name(double %a) nounwind { 79; RV32F-LABEL: constraint_f_double_abi_name: 80; RV32F: # %bb.0: 81; RV32F-NEXT: addi sp, sp, -16 82; RV32F-NEXT: sw a0, 8(sp) 83; RV32F-NEXT: sw a1, 12(sp) 84; RV32F-NEXT: lui a0, %hi(gd) 85; RV32F-NEXT: fld fa1, 8(sp) 86; RV32F-NEXT: fld fs0, %lo(gd)(a0) 87; RV32F-NEXT: #APP 88; RV32F-NEXT: .insn 0x4, 0x02000053 | (0 << 7) | (11 << 15) | (8 << 20) 89; RV32F-NEXT: #NO_APP 90; RV32F-NEXT: fsd ft0, 8(sp) 91; RV32F-NEXT: lw a0, 8(sp) 92; RV32F-NEXT: lw a1, 12(sp) 93; RV32F-NEXT: addi sp, sp, 16 94; RV32F-NEXT: ret 95; 96; RV64F-LABEL: constraint_f_double_abi_name: 97; RV64F: # %bb.0: 98; RV64F-NEXT: lui a1, %hi(gd) 99; RV64F-NEXT: fld fs0, %lo(gd)(a1) 100; RV64F-NEXT: fmv.d.x fa1, a0 101; RV64F-NEXT: #APP 102; RV64F-NEXT: .insn 0x4, 0x02000053 | (0 << 7) | (11 << 15) | (8 << 20) 103; RV64F-NEXT: #NO_APP 104; RV64F-NEXT: fmv.x.d a0, ft0 105; RV64F-NEXT: ret 106 %1 = load double, ptr @gd 107 %2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa1},{fs0}"(double %a, double %1) 108 ret double %2 109} 110