1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV64I 4 5define i64 @icmp_eq(i64 %a, i64 %b) nounwind { 6; RV64I-LABEL: icmp_eq: 7; RV64I: # %bb.0: 8; RV64I-NEXT: xor a0, a0, a1 9; RV64I-NEXT: seqz a0, a0 10; RV64I-NEXT: ret 11 %1 = icmp eq i64 %a, %b 12 %2 = zext i1 %1 to i64 13 ret i64 %2 14} 15 16define i64 @icmp_eq_constant(i64 %a) nounwind { 17; RV64I-LABEL: icmp_eq_constant: 18; RV64I: # %bb.0: 19; RV64I-NEXT: addi a0, a0, -42 20; RV64I-NEXT: seqz a0, a0 21; RV64I-NEXT: ret 22 %1 = icmp eq i64 %a, 42 23 %2 = zext i1 %1 to i64 24 ret i64 %2 25} 26 27define i64 @icmp_eq_constant_2049(i64 %a) nounwind { 28; RV64I-LABEL: icmp_eq_constant_2049: 29; RV64I: # %bb.0: 30; RV64I-NEXT: lui a1, 1 31; RV64I-NEXT: addiw a1, a1, -2047 32; RV64I-NEXT: xor a0, a0, a1 33; RV64I-NEXT: seqz a0, a0 34; RV64I-NEXT: ret 35 %1 = icmp eq i64 %a, 2049 36 %2 = zext i1 %1 to i64 37 ret i64 %2 38} 39 40define i64 @icmp_eq_constant_2048(i64 %a) nounwind { 41; RV64I-LABEL: icmp_eq_constant_2048: 42; RV64I: # %bb.0: 43; RV64I-NEXT: addi a0, a0, -2048 44; RV64I-NEXT: seqz a0, a0 45; RV64I-NEXT: ret 46 %1 = icmp eq i64 %a, 2048 47 %2 = zext i1 %1 to i64 48 ret i64 %2 49} 50 51define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind { 52; RV64I-LABEL: icmp_eq_constant_neg_2048: 53; RV64I: # %bb.0: 54; RV64I-NEXT: xori a0, a0, -2048 55; RV64I-NEXT: seqz a0, a0 56; RV64I-NEXT: ret 57 %1 = icmp eq i64 %a, -2048 58 %2 = zext i1 %1 to i64 59 ret i64 %2 60} 61 62define i64 @icmp_eq_constant_neg_2047(i64 %a) nounwind { 63; RV64I-LABEL: icmp_eq_constant_neg_2047: 64; RV64I: # %bb.0: 65; RV64I-NEXT: addi a0, a0, 2047 66; RV64I-NEXT: seqz a0, a0 67; RV64I-NEXT: ret 68 %1 = icmp eq i64 %a, -2047 69 %2 = zext i1 %1 to i64 70 ret i64 %2 71} 72 73define i64 @icmp_eqz(i64 %a) nounwind { 74; RV64I-LABEL: icmp_eqz: 75; RV64I: # %bb.0: 76; RV64I-NEXT: seqz a0, a0 77; RV64I-NEXT: ret 78 %1 = icmp eq i64 %a, 0 79 %2 = zext i1 %1 to i64 80 ret i64 %2 81} 82 83define i64 @icmp_ne(i64 %a, i64 %b) nounwind { 84; RV64I-LABEL: icmp_ne: 85; RV64I: # %bb.0: 86; RV64I-NEXT: xor a0, a0, a1 87; RV64I-NEXT: snez a0, a0 88; RV64I-NEXT: ret 89 %1 = icmp ne i64 %a, %b 90 %2 = zext i1 %1 to i64 91 ret i64 %2 92} 93 94define i64 @icmp_ne_constant(i64 %a) nounwind { 95; RV64I-LABEL: icmp_ne_constant: 96; RV64I: # %bb.0: 97; RV64I-NEXT: addi a0, a0, -42 98; RV64I-NEXT: snez a0, a0 99; RV64I-NEXT: ret 100 %1 = icmp ne i64 %a, 42 101 %2 = zext i1 %1 to i64 102 ret i64 %2 103} 104 105define i64 @icmp_ne_constant_2049(i64 %a) nounwind { 106; RV64I-LABEL: icmp_ne_constant_2049: 107; RV64I: # %bb.0: 108; RV64I-NEXT: lui a1, 1 109; RV64I-NEXT: addiw a1, a1, -2047 110; RV64I-NEXT: xor a0, a0, a1 111; RV64I-NEXT: snez a0, a0 112; RV64I-NEXT: ret 113 %1 = icmp ne i64 %a, 2049 114 %2 = zext i1 %1 to i64 115 ret i64 %2 116} 117 118define i64 @icmp_ne_constant_2048(i64 %a) nounwind { 119; RV64I-LABEL: icmp_ne_constant_2048: 120; RV64I: # %bb.0: 121; RV64I-NEXT: addi a0, a0, -2048 122; RV64I-NEXT: snez a0, a0 123; RV64I-NEXT: ret 124 %1 = icmp ne i64 %a, 2048 125 %2 = zext i1 %1 to i64 126 ret i64 %2 127} 128 129define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind { 130; RV64I-LABEL: icmp_ne_constant_neg_2048: 131; RV64I: # %bb.0: 132; RV64I-NEXT: xori a0, a0, -2048 133; RV64I-NEXT: snez a0, a0 134; RV64I-NEXT: ret 135 %1 = icmp ne i64 %a, -2048 136 %2 = zext i1 %1 to i64 137 ret i64 %2 138} 139 140define i64 @icmp_ne_constant_neg_2047(i64 %a) nounwind { 141; RV64I-LABEL: icmp_ne_constant_neg_2047: 142; RV64I: # %bb.0: 143; RV64I-NEXT: addi a0, a0, 2047 144; RV64I-NEXT: snez a0, a0 145; RV64I-NEXT: ret 146 %1 = icmp ne i64 %a, -2047 147 %2 = zext i1 %1 to i64 148 ret i64 %2 149} 150 151define i64 @icmp_nez(i64 %a) nounwind { 152; RV64I-LABEL: icmp_nez: 153; RV64I: # %bb.0: 154; RV64I-NEXT: snez a0, a0 155; RV64I-NEXT: ret 156 %1 = icmp ne i64 %a, 0 157 %2 = zext i1 %1 to i64 158 ret i64 %2 159} 160 161define i64 @icmp_ne_neg_1(i64 %a) nounwind { 162; RV64I-LABEL: icmp_ne_neg_1: 163; RV64I: # %bb.0: 164; RV64I-NEXT: sltiu a0, a0, -1 165; RV64I-NEXT: ret 166 %1 = icmp ne i64 %a, -1 167 %2 = zext i1 %1 to i64 168 ret i64 %2 169} 170 171define i64 @icmp_ugt(i64 %a, i64 %b) nounwind { 172; RV64I-LABEL: icmp_ugt: 173; RV64I: # %bb.0: 174; RV64I-NEXT: sltu a0, a1, a0 175; RV64I-NEXT: ret 176 %1 = icmp ugt i64 %a, %b 177 %2 = zext i1 %1 to i64 178 ret i64 %2 179} 180 181define i64 @icmp_ugt_constant_zero(i64 %a) nounwind { 182; RV64I-LABEL: icmp_ugt_constant_zero: 183; RV64I: # %bb.0: 184; RV64I-NEXT: snez a0, a0 185; RV64I-NEXT: ret 186 %1 = icmp ugt i64 %a, 0 187 %2 = zext i1 %1 to i64 188 ret i64 %2 189} 190 191define i64 @icmp_ugt_constant_2047(i64 %a) nounwind { 192; RV64I-LABEL: icmp_ugt_constant_2047: 193; RV64I: # %bb.0: 194; RV64I-NEXT: li a1, 2047 195; RV64I-NEXT: sltu a0, a1, a0 196; RV64I-NEXT: ret 197 %1 = icmp ugt i64 %a, 2047 198 %2 = zext i1 %1 to i64 199 ret i64 %2 200} 201 202define i64 @icmp_ugt_constant_2046(i64 %a) nounwind { 203; RV64I-LABEL: icmp_ugt_constant_2046: 204; RV64I: # %bb.0: 205; RV64I-NEXT: sltiu a0, a0, 2047 206; RV64I-NEXT: xori a0, a0, 1 207; RV64I-NEXT: ret 208 %1 = icmp ugt i64 %a, 2046 209 %2 = zext i1 %1 to i64 210 ret i64 %2 211} 212 213define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind { 214; RV64I-LABEL: icmp_ugt_constant_neg_2049: 215; RV64I: # %bb.0: 216; RV64I-NEXT: sltiu a0, a0, -2048 217; RV64I-NEXT: xori a0, a0, 1 218; RV64I-NEXT: ret 219; 18446744073709549567 signed extend is -2049 220 %1 = icmp ugt i64 %a, 18446744073709549567 221 %2 = zext i1 %1 to i64 222 ret i64 %2 223} 224 225define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind { 226; RV64I-LABEL: icmp_ugt_constant_neg_2050: 227; RV64I: # %bb.0: 228; RV64I-NEXT: lui a1, 1048575 229; RV64I-NEXT: addiw a1, a1, 2046 230; RV64I-NEXT: sltu a0, a1, a0 231; RV64I-NEXT: ret 232; 18446744073709549566 signed extend is -2050 233 %1 = icmp ugt i64 %a, 18446744073709549566 234 %2 = zext i1 %1 to i64 235 ret i64 %2 236} 237 238define i64 @icmp_uge(i64 %a, i64 %b) nounwind { 239; RV64I-LABEL: icmp_uge: 240; RV64I: # %bb.0: 241; RV64I-NEXT: sltu a0, a0, a1 242; RV64I-NEXT: xori a0, a0, 1 243; RV64I-NEXT: ret 244 %1 = icmp uge i64 %a, %b 245 %2 = zext i1 %1 to i64 246 ret i64 %2 247} 248 249define i64 @icmp_uge_constant_zero(i64 %a) nounwind { 250; RV64I-LABEL: icmp_uge_constant_zero: 251; RV64I: # %bb.0: 252; RV64I-NEXT: li a0, 1 253; RV64I-NEXT: ret 254 %1 = icmp uge i64 %a, 0 255 %2 = zext i1 %1 to i64 256 ret i64 %2 257} 258 259define i64 @icmp_uge_constant_2047(i64 %a) nounwind { 260; RV64I-LABEL: icmp_uge_constant_2047: 261; RV64I: # %bb.0: 262; RV64I-NEXT: sltiu a0, a0, 2047 263; RV64I-NEXT: xori a0, a0, 1 264; RV64I-NEXT: ret 265 %1 = icmp uge i64 %a, 2047 266 %2 = zext i1 %1 to i64 267 ret i64 %2 268} 269 270define i64 @icmp_uge_constant_2048(i64 %a) nounwind { 271; RV64I-LABEL: icmp_uge_constant_2048: 272; RV64I: # %bb.0: 273; RV64I-NEXT: li a1, 2047 274; RV64I-NEXT: sltu a0, a1, a0 275; RV64I-NEXT: ret 276 %1 = icmp uge i64 %a, 2048 277 %2 = zext i1 %1 to i64 278 ret i64 %2 279} 280 281define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind { 282; RV64I-LABEL: icmp_uge_constant_neg_2048: 283; RV64I: # %bb.0: 284; RV64I-NEXT: sltiu a0, a0, -2048 285; RV64I-NEXT: xori a0, a0, 1 286; RV64I-NEXT: ret 287; 18446744073709549568 signed extend is -2048 288 %1 = icmp uge i64 %a, 18446744073709549568 289 %2 = zext i1 %1 to i64 290 ret i64 %2 291} 292 293define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind { 294; RV64I-LABEL: icmp_uge_constant_neg_2049: 295; RV64I: # %bb.0: 296; RV64I-NEXT: lui a1, 1048575 297; RV64I-NEXT: addiw a1, a1, 2046 298; RV64I-NEXT: sltu a0, a1, a0 299; RV64I-NEXT: ret 300; 18446744073709549567 signed extend is -2049 301 %1 = icmp uge i64 %a, 18446744073709549567 302 %2 = zext i1 %1 to i64 303 ret i64 %2 304} 305 306define i64 @icmp_ult(i64 %a, i64 %b) nounwind { 307; RV64I-LABEL: icmp_ult: 308; RV64I: # %bb.0: 309; RV64I-NEXT: sltu a0, a0, a1 310; RV64I-NEXT: ret 311 %1 = icmp ult i64 %a, %b 312 %2 = zext i1 %1 to i64 313 ret i64 %2 314} 315 316define i64 @icmp_ult_constant_zero(i64 %a) nounwind { 317; RV64I-LABEL: icmp_ult_constant_zero: 318; RV64I: # %bb.0: 319; RV64I-NEXT: li a0, 0 320; RV64I-NEXT: ret 321 %1 = icmp ult i64 %a, 0 322 %2 = zext i1 %1 to i64 323 ret i64 %2 324} 325 326define i64 @icmp_ult_constant_2047(i64 %a) nounwind { 327; RV64I-LABEL: icmp_ult_constant_2047: 328; RV64I: # %bb.0: 329; RV64I-NEXT: sltiu a0, a0, 2047 330; RV64I-NEXT: ret 331 %1 = icmp ult i64 %a, 2047 332 %2 = zext i1 %1 to i64 333 ret i64 %2 334} 335 336define i64 @icmp_ult_constant_2048(i64 %a) nounwind { 337; RV64I-LABEL: icmp_ult_constant_2048: 338; RV64I: # %bb.0: 339; RV64I-NEXT: srli a0, a0, 11 340; RV64I-NEXT: seqz a0, a0 341; RV64I-NEXT: ret 342 %1 = icmp ult i64 %a, 2048 343 %2 = zext i1 %1 to i64 344 ret i64 %2 345} 346 347define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind { 348; RV64I-LABEL: icmp_ult_constant_neg_2048: 349; RV64I: # %bb.0: 350; RV64I-NEXT: sltiu a0, a0, -2048 351; RV64I-NEXT: ret 352; 18446744073709549568 signed extend is -2048 353 %1 = icmp ult i64 %a, 18446744073709549568 354 %2 = zext i1 %1 to i64 355 ret i64 %2 356} 357 358define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind { 359; RV64I-LABEL: icmp_ult_constant_neg_2049: 360; RV64I: # %bb.0: 361; RV64I-NEXT: lui a1, 1048575 362; RV64I-NEXT: addiw a1, a1, 2047 363; RV64I-NEXT: sltu a0, a0, a1 364; RV64I-NEXT: ret 365; 18446744073709549567 signed extend is -2049 366 %1 = icmp ult i64 %a, 18446744073709549567 367 %2 = zext i1 %1 to i64 368 ret i64 %2 369} 370 371define i64 @icmp_ule(i64 %a, i64 %b) nounwind { 372; RV64I-LABEL: icmp_ule: 373; RV64I: # %bb.0: 374; RV64I-NEXT: sltu a0, a1, a0 375; RV64I-NEXT: xori a0, a0, 1 376; RV64I-NEXT: ret 377 %1 = icmp ule i64 %a, %b 378 %2 = zext i1 %1 to i64 379 ret i64 %2 380} 381 382define i64 @icmp_ule_constant_zero(i64 %a) nounwind { 383; RV64I-LABEL: icmp_ule_constant_zero: 384; RV64I: # %bb.0: 385; RV64I-NEXT: seqz a0, a0 386; RV64I-NEXT: ret 387 %1 = icmp ule i64 %a, 0 388 %2 = zext i1 %1 to i64 389 ret i64 %2 390} 391 392define i64 @icmp_ule_constant_2046(i64 %a) nounwind { 393; RV64I-LABEL: icmp_ule_constant_2046: 394; RV64I: # %bb.0: 395; RV64I-NEXT: sltiu a0, a0, 2047 396; RV64I-NEXT: ret 397 %1 = icmp ule i64 %a, 2046 398 %2 = zext i1 %1 to i64 399 ret i64 %2 400} 401 402define i64 @icmp_ule_constant_2047(i64 %a) nounwind { 403; RV64I-LABEL: icmp_ule_constant_2047: 404; RV64I: # %bb.0: 405; RV64I-NEXT: srli a0, a0, 11 406; RV64I-NEXT: seqz a0, a0 407; RV64I-NEXT: ret 408 %1 = icmp ule i64 %a, 2047 409 %2 = zext i1 %1 to i64 410 ret i64 %2 411} 412 413define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind { 414; RV64I-LABEL: icmp_ule_constant_neg_2049: 415; RV64I: # %bb.0: 416; RV64I-NEXT: sltiu a0, a0, -2048 417; RV64I-NEXT: ret 418; 18446744073709549567 signed extend is -2049 419 %1 = icmp ule i64 %a, 18446744073709549567 420 %2 = zext i1 %1 to i64 421 ret i64 %2 422} 423 424define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind { 425; RV64I-LABEL: icmp_ule_constant_neg_2050: 426; RV64I: # %bb.0: 427; RV64I-NEXT: lui a1, 1048575 428; RV64I-NEXT: addiw a1, a1, 2047 429; RV64I-NEXT: sltu a0, a0, a1 430; RV64I-NEXT: ret 431; 18446744073709549566 signed extend is -2050 432 %1 = icmp ule i64 %a, 18446744073709549566 433 %2 = zext i1 %1 to i64 434 ret i64 %2 435} 436 437define i64 @icmp_sgt(i64 %a, i64 %b) nounwind { 438; RV64I-LABEL: icmp_sgt: 439; RV64I: # %bb.0: 440; RV64I-NEXT: slt a0, a1, a0 441; RV64I-NEXT: ret 442 %1 = icmp sgt i64 %a, %b 443 %2 = zext i1 %1 to i64 444 ret i64 %2 445} 446 447define i64 @icmp_sgt_constant_zero(i64 %a) nounwind { 448; RV64I-LABEL: icmp_sgt_constant_zero: 449; RV64I: # %bb.0: 450; RV64I-NEXT: sgtz a0, a0 451; RV64I-NEXT: ret 452 %1 = icmp sgt i64 %a, 0 453 %2 = zext i1 %1 to i64 454 ret i64 %2 455} 456 457define i64 @icmp_sgt_constant_2046(i64 %a) nounwind { 458; RV64I-LABEL: icmp_sgt_constant_2046: 459; RV64I: # %bb.0: 460; RV64I-NEXT: slti a0, a0, 2047 461; RV64I-NEXT: xori a0, a0, 1 462; RV64I-NEXT: ret 463 %1 = icmp sgt i64 %a, 2046 464 %2 = zext i1 %1 to i64 465 ret i64 %2 466} 467 468define i64 @icmp_sgt_constant_2047(i64 %a) nounwind { 469; RV64I-LABEL: icmp_sgt_constant_2047: 470; RV64I: # %bb.0: 471; RV64I-NEXT: li a1, 2047 472; RV64I-NEXT: slt a0, a1, a0 473; RV64I-NEXT: ret 474 %1 = icmp sgt i64 %a, 2047 475 %2 = zext i1 %1 to i64 476 ret i64 %2 477} 478 479define i64 @icmp_sgt_constant_neg_2049(i64 %a) nounwind { 480; RV64I-LABEL: icmp_sgt_constant_neg_2049: 481; RV64I: # %bb.0: 482; RV64I-NEXT: slti a0, a0, -2048 483; RV64I-NEXT: xori a0, a0, 1 484; RV64I-NEXT: ret 485 %1 = icmp sgt i64 %a, -2049 486 %2 = zext i1 %1 to i64 487 ret i64 %2 488} 489 490define i64 @icmp_sgt_constant_neg_2050(i64 %a) nounwind { 491; RV64I-LABEL: icmp_sgt_constant_neg_2050: 492; RV64I: # %bb.0: 493; RV64I-NEXT: lui a1, 1048575 494; RV64I-NEXT: addiw a1, a1, 2046 495; RV64I-NEXT: slt a0, a1, a0 496; RV64I-NEXT: ret 497 %1 = icmp sgt i64 %a, -2050 498 %2 = zext i1 %1 to i64 499 ret i64 %2 500} 501 502define i64 @icmp_sge(i64 %a, i64 %b) nounwind { 503; RV64I-LABEL: icmp_sge: 504; RV64I: # %bb.0: 505; RV64I-NEXT: slt a0, a0, a1 506; RV64I-NEXT: xori a0, a0, 1 507; RV64I-NEXT: ret 508 %1 = icmp sge i64 %a, %b 509 %2 = zext i1 %1 to i64 510 ret i64 %2 511} 512 513define i64 @icmp_sge_constant_zero(i64 %a) nounwind { 514; RV64I-LABEL: icmp_sge_constant_zero: 515; RV64I: # %bb.0: 516; RV64I-NEXT: not a0, a0 517; RV64I-NEXT: srli a0, a0, 63 518; RV64I-NEXT: ret 519 %1 = icmp sge i64 %a, 0 520 %2 = zext i1 %1 to i64 521 ret i64 %2 522} 523 524define i64 @icmp_sge_constant_2047(i64 %a) nounwind { 525; RV64I-LABEL: icmp_sge_constant_2047: 526; RV64I: # %bb.0: 527; RV64I-NEXT: slti a0, a0, 2047 528; RV64I-NEXT: xori a0, a0, 1 529; RV64I-NEXT: ret 530 %1 = icmp sge i64 %a, 2047 531 %2 = zext i1 %1 to i64 532 ret i64 %2 533} 534 535define i64 @icmp_sge_constant_2048(i64 %a) nounwind { 536; RV64I-LABEL: icmp_sge_constant_2048: 537; RV64I: # %bb.0: 538; RV64I-NEXT: li a1, 2047 539; RV64I-NEXT: slt a0, a1, a0 540; RV64I-NEXT: ret 541 %1 = icmp sge i64 %a, 2048 542 %2 = zext i1 %1 to i64 543 ret i64 %2 544} 545 546define i64 @icmp_sge_constant_neg_2047(i64 %a) nounwind { 547; RV64I-LABEL: icmp_sge_constant_neg_2047: 548; RV64I: # %bb.0: 549; RV64I-NEXT: slti a0, a0, -2047 550; RV64I-NEXT: xori a0, a0, 1 551; RV64I-NEXT: ret 552 %1 = icmp sge i64 %a, -2047 553 %2 = zext i1 %1 to i64 554 ret i64 %2 555} 556 557define i64 @icmp_sge_constant_neg_2048(i64 %a) nounwind { 558; RV64I-LABEL: icmp_sge_constant_neg_2048: 559; RV64I: # %bb.0: 560; RV64I-NEXT: not a0, a0 561; RV64I-NEXT: srli a0, a0, 63 562; RV64I-NEXT: ret 563 %1 = icmp sge i64 %a, 0 564 %2 = zext i1 %1 to i64 565 ret i64 %2 566} 567 568define i64 @icmp_slt(i64 %a, i64 %b) nounwind { 569; RV64I-LABEL: icmp_slt: 570; RV64I: # %bb.0: 571; RV64I-NEXT: slt a0, a0, a1 572; RV64I-NEXT: ret 573 %1 = icmp slt i64 %a, %b 574 %2 = zext i1 %1 to i64 575 ret i64 %2 576} 577 578define i64 @icmp_slt_constant_zero(i64 %a) nounwind { 579; RV64I-LABEL: icmp_slt_constant_zero: 580; RV64I: # %bb.0: 581; RV64I-NEXT: srli a0, a0, 63 582; RV64I-NEXT: ret 583 %1 = icmp slt i64 %a, 0 584 %2 = zext i1 %1 to i64 585 ret i64 %2 586} 587 588define i64 @icmp_slt_constant_2047(i64 %a) nounwind { 589; RV64I-LABEL: icmp_slt_constant_2047: 590; RV64I: # %bb.0: 591; RV64I-NEXT: slti a0, a0, 2047 592; RV64I-NEXT: ret 593 %1 = icmp slt i64 %a, 2047 594 %2 = zext i1 %1 to i64 595 ret i64 %2 596} 597 598define i64 @icmp_slt_constant_2048(i64 %a) nounwind { 599; RV64I-LABEL: icmp_slt_constant_2048: 600; RV64I: # %bb.0: 601; RV64I-NEXT: li a1, 1 602; RV64I-NEXT: slli a1, a1, 11 603; RV64I-NEXT: slt a0, a0, a1 604; RV64I-NEXT: ret 605 %1 = icmp slt i64 %a, 2048 606 %2 = zext i1 %1 to i64 607 ret i64 %2 608} 609 610define i64 @icmp_slt_constant_neg_2048(i64 %a) nounwind { 611; RV64I-LABEL: icmp_slt_constant_neg_2048: 612; RV64I: # %bb.0: 613; RV64I-NEXT: slti a0, a0, -2048 614; RV64I-NEXT: ret 615 %1 = icmp slt i64 %a, -2048 616 %2 = zext i1 %1 to i64 617 ret i64 %2 618} 619 620define i64 @icmp_slt_constant_neg_2049(i64 %a) nounwind { 621; RV64I-LABEL: icmp_slt_constant_neg_2049: 622; RV64I: # %bb.0: 623; RV64I-NEXT: lui a1, 1048575 624; RV64I-NEXT: addiw a1, a1, 2047 625; RV64I-NEXT: slt a0, a0, a1 626; RV64I-NEXT: ret 627 %1 = icmp slt i64 %a, -2049 628 %2 = zext i1 %1 to i64 629 ret i64 %2 630} 631 632define i64 @icmp_sle(i64 %a, i64 %b) nounwind { 633; RV64I-LABEL: icmp_sle: 634; RV64I: # %bb.0: 635; RV64I-NEXT: slt a0, a1, a0 636; RV64I-NEXT: xori a0, a0, 1 637; RV64I-NEXT: ret 638 %1 = icmp sle i64 %a, %b 639 %2 = zext i1 %1 to i64 640 ret i64 %2 641} 642 643define i64 @icmp_sle_constant_zero(i64 %a) nounwind { 644; RV64I-LABEL: icmp_sle_constant_zero: 645; RV64I: # %bb.0: 646; RV64I-NEXT: slti a0, a0, 1 647; RV64I-NEXT: ret 648 %1 = icmp sle i64 %a, 0 649 %2 = zext i1 %1 to i64 650 ret i64 %2 651} 652 653define i64 @icmp_sle_constant_2046(i64 %a) nounwind { 654; RV64I-LABEL: icmp_sle_constant_2046: 655; RV64I: # %bb.0: 656; RV64I-NEXT: slti a0, a0, 2047 657; RV64I-NEXT: ret 658 %1 = icmp sle i64 %a, 2046 659 %2 = zext i1 %1 to i64 660 ret i64 %2 661} 662 663define i64 @icmp_sle_constant_2047(i64 %a) nounwind { 664; RV64I-LABEL: icmp_sle_constant_2047: 665; RV64I: # %bb.0: 666; RV64I-NEXT: li a1, 1 667; RV64I-NEXT: slli a1, a1, 11 668; RV64I-NEXT: slt a0, a0, a1 669; RV64I-NEXT: ret 670 %1 = icmp sle i64 %a, 2047 671 %2 = zext i1 %1 to i64 672 ret i64 %2 673} 674 675define i64 @icmp_sle_constant_neg_2049(i64 %a) nounwind { 676; RV64I-LABEL: icmp_sle_constant_neg_2049: 677; RV64I: # %bb.0: 678; RV64I-NEXT: slti a0, a0, -2048 679; RV64I-NEXT: ret 680 %1 = icmp sle i64 %a, -2049 681 %2 = zext i1 %1 to i64 682 ret i64 %2 683} 684 685define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind { 686; RV64I-LABEL: icmp_sle_constant_neg_2050: 687; RV64I: # %bb.0: 688; RV64I-NEXT: lui a1, 1048575 689; RV64I-NEXT: addiw a1, a1, 2047 690; RV64I-NEXT: slt a0, a0, a1 691; RV64I-NEXT: ret 692 %1 = icmp sle i64 %a, -2050 693 %2 = zext i1 %1 to i64 694 ret i64 %2 695} 696 697define i64 @icmp_eq_zext_inreg_small_constant(i64 %a) nounwind { 698; RV64I-LABEL: icmp_eq_zext_inreg_small_constant: 699; RV64I: # %bb.0: 700; RV64I-NEXT: sext.w a0, a0 701; RV64I-NEXT: addi a0, a0, -123 702; RV64I-NEXT: seqz a0, a0 703; RV64I-NEXT: ret 704 %1 = and i64 %a, 4294967295 705 %2 = icmp eq i64 %1, 123 706 %3 = zext i1 %2 to i64 707 ret i64 %3 708} 709 710define i64 @icmp_eq_zext_inreg_large_constant(i64 %a) nounwind { 711; RV64I-LABEL: icmp_eq_zext_inreg_large_constant: 712; RV64I: # %bb.0: 713; RV64I-NEXT: sext.w a0, a0 714; RV64I-NEXT: lui a1, 563901 715; RV64I-NEXT: addiw a1, a1, -529 716; RV64I-NEXT: xor a0, a0, a1 717; RV64I-NEXT: seqz a0, a0 718; RV64I-NEXT: ret 719 %1 = and i64 %a, 4294967295 720 %2 = icmp eq i64 %1, 2309737967 721 %3 = zext i1 %2 to i64 722 ret i64 %3 723} 724 725define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind { 726; RV64I-LABEL: icmp_ne_zext_inreg_small_constant: 727; RV64I: # %bb.0: 728; RV64I-NEXT: sext.w a0, a0 729; RV64I-NEXT: snez a0, a0 730; RV64I-NEXT: ret 731 %1 = and i64 %a, 4294967295 732 %2 = icmp ne i64 %1, 0 733 %3 = zext i1 %2 to i64 734 ret i64 %3 735} 736 737define i64 @icmp_ne_zext_inreg_large_constant(i64 %a) nounwind { 738; RV64I-LABEL: icmp_ne_zext_inreg_large_constant: 739; RV64I: # %bb.0: 740; RV64I-NEXT: sext.w a0, a0 741; RV64I-NEXT: addi a0, a0, 2 742; RV64I-NEXT: snez a0, a0 743; RV64I-NEXT: ret 744 %1 = and i64 %a, 4294967295 745 %2 = icmp ne i64 %1, 4294967294 746 %3 = zext i1 %2 to i64 747 ret i64 %3 748} 749 750; This used to trigger an infinite loop where we toggled between 'and' and 751; 'sext_inreg'. 752define i64 @icmp_ne_zext_inreg_umin(i64 %a) nounwind { 753; RV64I-LABEL: icmp_ne_zext_inreg_umin: 754; RV64I: # %bb.0: 755; RV64I-NEXT: lui a1, 30141 756; RV64I-NEXT: addiw a1, a1, -747 757; RV64I-NEXT: bltu a0, a1, .LBB67_2 758; RV64I-NEXT: # %bb.1: 759; RV64I-NEXT: mv a0, a1 760; RV64I-NEXT: .LBB67_2: 761; RV64I-NEXT: addi a0, a0, -123 762; RV64I-NEXT: snez a0, a0 763; RV64I-NEXT: ret 764 %1 = call i64 @llvm.umin.i64(i64 %a, i64 123456789) 765 %2 = and i64 %1, 4294967295 766 %3 = icmp ne i64 %2, 123 767 %4 = zext i1 %3 to i64 768 ret i64 %4 769} 770declare i64 @llvm.umin.i64(i64, i64) 771