1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4 5define i32 @icmp_eq(i32 %a, i32 %b) nounwind { 6; RV32I-LABEL: icmp_eq: 7; RV32I: # %bb.0: 8; RV32I-NEXT: xor a0, a0, a1 9; RV32I-NEXT: seqz a0, a0 10; RV32I-NEXT: ret 11 %1 = icmp eq i32 %a, %b 12 %2 = zext i1 %1 to i32 13 ret i32 %2 14} 15 16define i32 @icmp_eq_constant(i32 %a) nounwind { 17; RV32I-LABEL: icmp_eq_constant: 18; RV32I: # %bb.0: 19; RV32I-NEXT: addi a0, a0, -42 20; RV32I-NEXT: seqz a0, a0 21; RV32I-NEXT: ret 22 %1 = icmp eq i32 %a, 42 23 %2 = zext i1 %1 to i32 24 ret i32 %2 25} 26 27define i32 @icmp_eq_constant_2049(i32 %a) nounwind { 28; RV32I-LABEL: icmp_eq_constant_2049: 29; RV32I: # %bb.0: 30; RV32I-NEXT: lui a1, 1 31; RV32I-NEXT: addi a1, a1, -2047 32; RV32I-NEXT: xor a0, a0, a1 33; RV32I-NEXT: seqz a0, a0 34; RV32I-NEXT: ret 35 %1 = icmp eq i32 %a, 2049 36 %2 = zext i1 %1 to i32 37 ret i32 %2 38} 39 40define i32 @icmp_eq_constant_2048(i32 %a) nounwind { 41; RV32I-LABEL: icmp_eq_constant_2048: 42; RV32I: # %bb.0: 43; RV32I-NEXT: addi a0, a0, -2048 44; RV32I-NEXT: seqz a0, a0 45; RV32I-NEXT: ret 46 %1 = icmp eq i32 %a, 2048 47 %2 = zext i1 %1 to i32 48 ret i32 %2 49} 50 51define i32 @icmp_eq_constant_neg_2048(i32 %a) nounwind { 52; RV32I-LABEL: icmp_eq_constant_neg_2048: 53; RV32I: # %bb.0: 54; RV32I-NEXT: xori a0, a0, -2048 55; RV32I-NEXT: seqz a0, a0 56; RV32I-NEXT: ret 57 %1 = icmp eq i32 %a, -2048 58 %2 = zext i1 %1 to i32 59 ret i32 %2 60} 61 62define i32 @icmp_eq_constant_neg_2047(i32 %a) nounwind { 63; RV32I-LABEL: icmp_eq_constant_neg_2047: 64; RV32I: # %bb.0: 65; RV32I-NEXT: addi a0, a0, 2047 66; RV32I-NEXT: seqz a0, a0 67; RV32I-NEXT: ret 68 %1 = icmp eq i32 %a, -2047 69 %2 = zext i1 %1 to i32 70 ret i32 %2 71} 72 73define i32 @icmp_eqz(i32 %a) nounwind { 74; RV32I-LABEL: icmp_eqz: 75; RV32I: # %bb.0: 76; RV32I-NEXT: seqz a0, a0 77; RV32I-NEXT: ret 78 %1 = icmp eq i32 %a, 0 79 %2 = zext i1 %1 to i32 80 ret i32 %2 81} 82 83define i32 @icmp_ne(i32 %a, i32 %b) nounwind { 84; RV32I-LABEL: icmp_ne: 85; RV32I: # %bb.0: 86; RV32I-NEXT: xor a0, a0, a1 87; RV32I-NEXT: snez a0, a0 88; RV32I-NEXT: ret 89 %1 = icmp ne i32 %a, %b 90 %2 = zext i1 %1 to i32 91 ret i32 %2 92} 93 94define i32 @icmp_ne_constant(i32 %a) nounwind { 95; RV32I-LABEL: icmp_ne_constant: 96; RV32I: # %bb.0: 97; RV32I-NEXT: addi a0, a0, -42 98; RV32I-NEXT: snez a0, a0 99; RV32I-NEXT: ret 100 %1 = icmp ne i32 %a, 42 101 %2 = zext i1 %1 to i32 102 ret i32 %2 103} 104 105define i32 @icmp_ne_constant_2049(i32 %a) nounwind { 106; RV32I-LABEL: icmp_ne_constant_2049: 107; RV32I: # %bb.0: 108; RV32I-NEXT: lui a1, 1 109; RV32I-NEXT: addi a1, a1, -2047 110; RV32I-NEXT: xor a0, a0, a1 111; RV32I-NEXT: snez a0, a0 112; RV32I-NEXT: ret 113 %1 = icmp ne i32 %a, 2049 114 %2 = zext i1 %1 to i32 115 ret i32 %2 116} 117 118define i32 @icmp_ne_constant_2048(i32 %a) nounwind { 119; RV32I-LABEL: icmp_ne_constant_2048: 120; RV32I: # %bb.0: 121; RV32I-NEXT: addi a0, a0, -2048 122; RV32I-NEXT: snez a0, a0 123; RV32I-NEXT: ret 124 %1 = icmp ne i32 %a, 2048 125 %2 = zext i1 %1 to i32 126 ret i32 %2 127} 128 129define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind { 130; RV32I-LABEL: icmp_ne_constant_neg_2048: 131; RV32I: # %bb.0: 132; RV32I-NEXT: xori a0, a0, -2048 133; RV32I-NEXT: snez a0, a0 134; RV32I-NEXT: ret 135 %1 = icmp ne i32 %a, -2048 136 %2 = zext i1 %1 to i32 137 ret i32 %2 138} 139 140define i32 @icmp_ne_constant_neg_2047(i32 %a) nounwind { 141; RV32I-LABEL: icmp_ne_constant_neg_2047: 142; RV32I: # %bb.0: 143; RV32I-NEXT: addi a0, a0, 2047 144; RV32I-NEXT: snez a0, a0 145; RV32I-NEXT: ret 146 %1 = icmp ne i32 %a, -2047 147 %2 = zext i1 %1 to i32 148 ret i32 %2 149} 150 151define i32 @icmp_nez(i32 %a) nounwind { 152; RV32I-LABEL: icmp_nez: 153; RV32I: # %bb.0: 154; RV32I-NEXT: snez a0, a0 155; RV32I-NEXT: ret 156 %1 = icmp ne i32 %a, 0 157 %2 = zext i1 %1 to i32 158 ret i32 %2 159} 160 161define i32 @icmp_ne_neg_1(i32 %a) nounwind { 162; RV32I-LABEL: icmp_ne_neg_1: 163; RV32I: # %bb.0: 164; RV32I-NEXT: sltiu a0, a0, -1 165; RV32I-NEXT: ret 166 %1 = icmp ne i32 %a, -1 167 %2 = zext i1 %1 to i32 168 ret i32 %2 169} 170 171define i32 @icmp_ugt(i32 %a, i32 %b) nounwind { 172; RV32I-LABEL: icmp_ugt: 173; RV32I: # %bb.0: 174; RV32I-NEXT: sltu a0, a1, a0 175; RV32I-NEXT: ret 176 %1 = icmp ugt i32 %a, %b 177 %2 = zext i1 %1 to i32 178 ret i32 %2 179} 180 181define i32 @icmp_ugt_constant_zero(i32 %a) nounwind { 182; RV32I-LABEL: icmp_ugt_constant_zero: 183; RV32I: # %bb.0: 184; RV32I-NEXT: snez a0, a0 185; RV32I-NEXT: ret 186 %1 = icmp ugt i32 %a, 0 187 %2 = zext i1 %1 to i32 188 ret i32 %2 189} 190 191define i32 @icmp_ugt_constant_2047(i32 %a) nounwind { 192; RV32I-LABEL: icmp_ugt_constant_2047: 193; RV32I: # %bb.0: 194; RV32I-NEXT: li a1, 2047 195; RV32I-NEXT: sltu a0, a1, a0 196; RV32I-NEXT: ret 197 %1 = icmp ugt i32 %a, 2047 198 %2 = zext i1 %1 to i32 199 ret i32 %2 200} 201 202define i32 @icmp_ugt_constant_2046(i32 %a) nounwind { 203; RV32I-LABEL: icmp_ugt_constant_2046: 204; RV32I: # %bb.0: 205; RV32I-NEXT: sltiu a0, a0, 2047 206; RV32I-NEXT: xori a0, a0, 1 207; RV32I-NEXT: ret 208 %1 = icmp ugt i32 %a, 2046 209 %2 = zext i1 %1 to i32 210 ret i32 %2 211} 212 213define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind { 214; RV32I-LABEL: icmp_ugt_constant_neg_2049: 215; RV32I: # %bb.0: 216; RV32I-NEXT: sltiu a0, a0, -2048 217; RV32I-NEXT: xori a0, a0, 1 218; RV32I-NEXT: ret 219; 4294965247 signed extend is -2049 220 %1 = icmp ugt i32 %a, 4294965247 221 %2 = zext i1 %1 to i32 222 ret i32 %2 223} 224 225define i32 @icmp_ugt_constant_neg_2050(i32 %a) nounwind { 226; RV32I-LABEL: icmp_ugt_constant_neg_2050: 227; RV32I: # %bb.0: 228; RV32I-NEXT: lui a1, 1048575 229; RV32I-NEXT: addi a1, a1, 2046 230; RV32I-NEXT: sltu a0, a1, a0 231; RV32I-NEXT: ret 232; 4294965246 signed extend is -2050 233 %1 = icmp ugt i32 %a, 4294965246 234 %2 = zext i1 %1 to i32 235 ret i32 %2 236} 237 238define i32 @icmp_uge(i32 %a, i32 %b) nounwind { 239; RV32I-LABEL: icmp_uge: 240; RV32I: # %bb.0: 241; RV32I-NEXT: sltu a0, a0, a1 242; RV32I-NEXT: xori a0, a0, 1 243; RV32I-NEXT: ret 244 %1 = icmp uge i32 %a, %b 245 %2 = zext i1 %1 to i32 246 ret i32 %2 247} 248 249define i32 @icmp_uge_constant_zero(i32 %a) nounwind { 250; RV32I-LABEL: icmp_uge_constant_zero: 251; RV32I: # %bb.0: 252; RV32I-NEXT: li a0, 1 253; RV32I-NEXT: ret 254 %1 = icmp uge i32 %a, 0 255 %2 = zext i1 %1 to i32 256 ret i32 %2 257} 258 259define i32 @icmp_uge_constant_2047(i32 %a) nounwind { 260; RV32I-LABEL: icmp_uge_constant_2047: 261; RV32I: # %bb.0: 262; RV32I-NEXT: sltiu a0, a0, 2047 263; RV32I-NEXT: xori a0, a0, 1 264; RV32I-NEXT: ret 265 %1 = icmp uge i32 %a, 2047 266 %2 = zext i1 %1 to i32 267 ret i32 %2 268} 269 270define i32 @icmp_uge_constant_2048(i32 %a) nounwind { 271; RV32I-LABEL: icmp_uge_constant_2048: 272; RV32I: # %bb.0: 273; RV32I-NEXT: li a1, 2047 274; RV32I-NEXT: sltu a0, a1, a0 275; RV32I-NEXT: ret 276 %1 = icmp uge i32 %a, 2048 277 %2 = zext i1 %1 to i32 278 ret i32 %2 279} 280 281define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind { 282; RV32I-LABEL: icmp_uge_constant_neg_2048: 283; RV32I: # %bb.0: 284; RV32I-NEXT: sltiu a0, a0, -2048 285; RV32I-NEXT: xori a0, a0, 1 286; RV32I-NEXT: ret 287; 4294965248 signed extend is -2048 288 %1 = icmp uge i32 %a, 4294965248 289 %2 = zext i1 %1 to i32 290 ret i32 %2 291} 292 293define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind { 294; RV32I-LABEL: icmp_uge_constant_neg_2049: 295; RV32I: # %bb.0: 296; RV32I-NEXT: lui a1, 1048575 297; RV32I-NEXT: addi a1, a1, 2046 298; RV32I-NEXT: sltu a0, a1, a0 299; RV32I-NEXT: ret 300; 4294965247 signed extend is -2049 301 %1 = icmp uge i32 %a, 4294965247 302 %2 = zext i1 %1 to i32 303 ret i32 %2 304} 305 306define i32 @icmp_ult(i32 %a, i32 %b) nounwind { 307; RV32I-LABEL: icmp_ult: 308; RV32I: # %bb.0: 309; RV32I-NEXT: sltu a0, a0, a1 310; RV32I-NEXT: ret 311 %1 = icmp ult i32 %a, %b 312 %2 = zext i1 %1 to i32 313 ret i32 %2 314} 315 316define i32 @icmp_ult_constant_zero(i32 %a) nounwind { 317; RV32I-LABEL: icmp_ult_constant_zero: 318; RV32I: # %bb.0: 319; RV32I-NEXT: li a0, 0 320; RV32I-NEXT: ret 321 %1 = icmp ult i32 %a, 0 322 %2 = zext i1 %1 to i32 323 ret i32 %2 324} 325 326define i32 @icmp_ult_constant_2047(i32 %a) nounwind { 327; RV32I-LABEL: icmp_ult_constant_2047: 328; RV32I: # %bb.0: 329; RV32I-NEXT: sltiu a0, a0, 2047 330; RV32I-NEXT: ret 331 %1 = icmp ult i32 %a, 2047 332 %2 = zext i1 %1 to i32 333 ret i32 %2 334} 335 336define i32 @icmp_ult_constant_2048(i32 %a) nounwind { 337; RV32I-LABEL: icmp_ult_constant_2048: 338; RV32I: # %bb.0: 339; RV32I-NEXT: srli a0, a0, 11 340; RV32I-NEXT: seqz a0, a0 341; RV32I-NEXT: ret 342 %1 = icmp ult i32 %a, 2048 343 %2 = zext i1 %1 to i32 344 ret i32 %2 345} 346 347define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind { 348; RV32I-LABEL: icmp_ult_constant_neg_2048: 349; RV32I: # %bb.0: 350; RV32I-NEXT: sltiu a0, a0, -2048 351; RV32I-NEXT: ret 352; 4294965248 signed extend is -2048 353 %1 = icmp ult i32 %a, 4294965248 354 %2 = zext i1 %1 to i32 355 ret i32 %2 356} 357 358define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind { 359; RV32I-LABEL: icmp_ult_constant_neg_2049: 360; RV32I: # %bb.0: 361; RV32I-NEXT: lui a1, 1048575 362; RV32I-NEXT: addi a1, a1, 2047 363; RV32I-NEXT: sltu a0, a0, a1 364; RV32I-NEXT: ret 365; 4294965247 signed extend is -2049 366 %1 = icmp ult i32 %a, 4294965247 367 %2 = zext i1 %1 to i32 368 ret i32 %2 369} 370 371define i32 @icmp_ule(i32 %a, i32 %b) nounwind { 372; RV32I-LABEL: icmp_ule: 373; RV32I: # %bb.0: 374; RV32I-NEXT: sltu a0, a1, a0 375; RV32I-NEXT: xori a0, a0, 1 376; RV32I-NEXT: ret 377 %1 = icmp ule i32 %a, %b 378 %2 = zext i1 %1 to i32 379 ret i32 %2 380} 381 382define i32 @icmp_ule_constant_zero(i32 %a) nounwind { 383; RV32I-LABEL: icmp_ule_constant_zero: 384; RV32I: # %bb.0: 385; RV32I-NEXT: seqz a0, a0 386; RV32I-NEXT: ret 387 %1 = icmp ule i32 %a, 0 388 %2 = zext i1 %1 to i32 389 ret i32 %2 390} 391 392define i32 @icmp_ule_constant_2046(i32 %a) nounwind { 393; RV32I-LABEL: icmp_ule_constant_2046: 394; RV32I: # %bb.0: 395; RV32I-NEXT: sltiu a0, a0, 2047 396; RV32I-NEXT: ret 397 %1 = icmp ule i32 %a, 2046 398 %2 = zext i1 %1 to i32 399 ret i32 %2 400} 401 402define i32 @icmp_ule_constant_2047(i32 %a) nounwind { 403; RV32I-LABEL: icmp_ule_constant_2047: 404; RV32I: # %bb.0: 405; RV32I-NEXT: srli a0, a0, 11 406; RV32I-NEXT: seqz a0, a0 407; RV32I-NEXT: ret 408 %1 = icmp ule i32 %a, 2047 409 %2 = zext i1 %1 to i32 410 ret i32 %2 411} 412 413define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind { 414; RV32I-LABEL: icmp_ule_constant_neg_2049: 415; RV32I: # %bb.0: 416; RV32I-NEXT: sltiu a0, a0, -2048 417; RV32I-NEXT: ret 418; 4294965247 signed extend is -2049 419 %1 = icmp ule i32 %a, 4294965247 420 %2 = zext i1 %1 to i32 421 ret i32 %2 422} 423 424define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind { 425; RV32I-LABEL: icmp_ule_constant_neg_2050: 426; RV32I: # %bb.0: 427; RV32I-NEXT: lui a1, 1048575 428; RV32I-NEXT: addi a1, a1, 2047 429; RV32I-NEXT: sltu a0, a0, a1 430; RV32I-NEXT: ret 431; 4294965246 signed extend is -2050 432 %1 = icmp ule i32 %a, 4294965246 433 %2 = zext i1 %1 to i32 434 ret i32 %2 435} 436 437define i32 @icmp_sgt(i32 %a, i32 %b) nounwind { 438; RV32I-LABEL: icmp_sgt: 439; RV32I: # %bb.0: 440; RV32I-NEXT: slt a0, a1, a0 441; RV32I-NEXT: ret 442 %1 = icmp sgt i32 %a, %b 443 %2 = zext i1 %1 to i32 444 ret i32 %2 445} 446 447define i32 @icmp_sgt_constant_zero(i32 %a) nounwind { 448; RV32I-LABEL: icmp_sgt_constant_zero: 449; RV32I: # %bb.0: 450; RV32I-NEXT: sgtz a0, a0 451; RV32I-NEXT: ret 452 %1 = icmp sgt i32 %a, 0 453 %2 = zext i1 %1 to i32 454 ret i32 %2 455} 456 457define i32 @icmp_sgt_constant_2046(i32 %a) nounwind { 458; RV32I-LABEL: icmp_sgt_constant_2046: 459; RV32I: # %bb.0: 460; RV32I-NEXT: slti a0, a0, 2047 461; RV32I-NEXT: xori a0, a0, 1 462; RV32I-NEXT: ret 463 %1 = icmp sgt i32 %a, 2046 464 %2 = zext i1 %1 to i32 465 ret i32 %2 466} 467 468define i32 @icmp_sgt_constant_2047(i32 %a) nounwind { 469; RV32I-LABEL: icmp_sgt_constant_2047: 470; RV32I: # %bb.0: 471; RV32I-NEXT: li a1, 2047 472; RV32I-NEXT: slt a0, a1, a0 473; RV32I-NEXT: ret 474 %1 = icmp sgt i32 %a, 2047 475 %2 = zext i1 %1 to i32 476 ret i32 %2 477} 478 479define i32 @icmp_sgt_constant_neg_2049(i32 %a) nounwind { 480; RV32I-LABEL: icmp_sgt_constant_neg_2049: 481; RV32I: # %bb.0: 482; RV32I-NEXT: slti a0, a0, -2048 483; RV32I-NEXT: xori a0, a0, 1 484; RV32I-NEXT: ret 485 %1 = icmp sgt i32 %a, -2049 486 %2 = zext i1 %1 to i32 487 ret i32 %2 488} 489 490define i32 @icmp_sgt_constant_neg_2050(i32 %a) nounwind { 491; RV32I-LABEL: icmp_sgt_constant_neg_2050: 492; RV32I: # %bb.0: 493; RV32I-NEXT: lui a1, 1048575 494; RV32I-NEXT: addi a1, a1, 2046 495; RV32I-NEXT: slt a0, a1, a0 496; RV32I-NEXT: ret 497 %1 = icmp sgt i32 %a, -2050 498 %2 = zext i1 %1 to i32 499 ret i32 %2 500} 501 502define i32 @icmp_sge(i32 %a, i32 %b) nounwind { 503; RV32I-LABEL: icmp_sge: 504; RV32I: # %bb.0: 505; RV32I-NEXT: slt a0, a0, a1 506; RV32I-NEXT: xori a0, a0, 1 507; RV32I-NEXT: ret 508 %1 = icmp sge i32 %a, %b 509 %2 = zext i1 %1 to i32 510 ret i32 %2 511} 512 513define i32 @icmp_sge_constant_zero(i32 %a) nounwind { 514; RV32I-LABEL: icmp_sge_constant_zero: 515; RV32I: # %bb.0: 516; RV32I-NEXT: not a0, a0 517; RV32I-NEXT: srli a0, a0, 31 518; RV32I-NEXT: ret 519 %1 = icmp sge i32 %a, 0 520 %2 = zext i1 %1 to i32 521 ret i32 %2 522} 523 524define i32 @icmp_sge_constant_2047(i32 %a) nounwind { 525; RV32I-LABEL: icmp_sge_constant_2047: 526; RV32I: # %bb.0: 527; RV32I-NEXT: slti a0, a0, 2047 528; RV32I-NEXT: xori a0, a0, 1 529; RV32I-NEXT: ret 530 %1 = icmp sge i32 %a, 2047 531 %2 = zext i1 %1 to i32 532 ret i32 %2 533} 534 535define i32 @icmp_sge_constant_2048(i32 %a) nounwind { 536; RV32I-LABEL: icmp_sge_constant_2048: 537; RV32I: # %bb.0: 538; RV32I-NEXT: li a1, 2047 539; RV32I-NEXT: slt a0, a1, a0 540; RV32I-NEXT: ret 541 %1 = icmp sge i32 %a, 2048 542 %2 = zext i1 %1 to i32 543 ret i32 %2 544} 545 546define i32 @icmp_sge_constant_neg_2047(i32 %a) nounwind { 547; RV32I-LABEL: icmp_sge_constant_neg_2047: 548; RV32I: # %bb.0: 549; RV32I-NEXT: slti a0, a0, -2047 550; RV32I-NEXT: xori a0, a0, 1 551; RV32I-NEXT: ret 552 %1 = icmp sge i32 %a, -2047 553 %2 = zext i1 %1 to i32 554 ret i32 %2 555} 556 557define i32 @icmp_sge_constant_neg_2048(i32 %a) nounwind { 558; RV32I-LABEL: icmp_sge_constant_neg_2048: 559; RV32I: # %bb.0: 560; RV32I-NEXT: not a0, a0 561; RV32I-NEXT: srli a0, a0, 31 562; RV32I-NEXT: ret 563 %1 = icmp sge i32 %a, 0 564 %2 = zext i1 %1 to i32 565 ret i32 %2 566} 567 568define i32 @icmp_slt(i32 %a, i32 %b) nounwind { 569; RV32I-LABEL: icmp_slt: 570; RV32I: # %bb.0: 571; RV32I-NEXT: slt a0, a0, a1 572; RV32I-NEXT: ret 573 %1 = icmp slt i32 %a, %b 574 %2 = zext i1 %1 to i32 575 ret i32 %2 576} 577 578define i32 @icmp_slt_constant_zero(i32 %a) nounwind { 579; RV32I-LABEL: icmp_slt_constant_zero: 580; RV32I: # %bb.0: 581; RV32I-NEXT: srli a0, a0, 31 582; RV32I-NEXT: ret 583 %1 = icmp slt i32 %a, 0 584 %2 = zext i1 %1 to i32 585 ret i32 %2 586} 587 588define i32 @icmp_slt_constant_2047(i32 %a) nounwind { 589; RV32I-LABEL: icmp_slt_constant_2047: 590; RV32I: # %bb.0: 591; RV32I-NEXT: slti a0, a0, 2047 592; RV32I-NEXT: ret 593 %1 = icmp slt i32 %a, 2047 594 %2 = zext i1 %1 to i32 595 ret i32 %2 596} 597 598define i32 @icmp_slt_constant_2048(i32 %a) nounwind { 599; RV32I-LABEL: icmp_slt_constant_2048: 600; RV32I: # %bb.0: 601; RV32I-NEXT: li a1, 1 602; RV32I-NEXT: slli a1, a1, 11 603; RV32I-NEXT: slt a0, a0, a1 604; RV32I-NEXT: ret 605 %1 = icmp slt i32 %a, 2048 606 %2 = zext i1 %1 to i32 607 ret i32 %2 608} 609 610define i32 @icmp_slt_constant_neg_2048(i32 %a) nounwind { 611; RV32I-LABEL: icmp_slt_constant_neg_2048: 612; RV32I: # %bb.0: 613; RV32I-NEXT: slti a0, a0, -2048 614; RV32I-NEXT: ret 615 %1 = icmp slt i32 %a, -2048 616 %2 = zext i1 %1 to i32 617 ret i32 %2 618} 619 620define i32 @icmp_slt_constant_neg_2049(i32 %a) nounwind { 621; RV32I-LABEL: icmp_slt_constant_neg_2049: 622; RV32I: # %bb.0: 623; RV32I-NEXT: lui a1, 1048575 624; RV32I-NEXT: addi a1, a1, 2047 625; RV32I-NEXT: slt a0, a0, a1 626; RV32I-NEXT: ret 627 %1 = icmp slt i32 %a, -2049 628 %2 = zext i1 %1 to i32 629 ret i32 %2 630} 631 632define i32 @icmp_sle(i32 %a, i32 %b) nounwind { 633; RV32I-LABEL: icmp_sle: 634; RV32I: # %bb.0: 635; RV32I-NEXT: slt a0, a1, a0 636; RV32I-NEXT: xori a0, a0, 1 637; RV32I-NEXT: ret 638 %1 = icmp sle i32 %a, %b 639 %2 = zext i1 %1 to i32 640 ret i32 %2 641} 642 643define i32 @icmp_sle_constant_zero(i32 %a) nounwind { 644; RV32I-LABEL: icmp_sle_constant_zero: 645; RV32I: # %bb.0: 646; RV32I-NEXT: slti a0, a0, 1 647; RV32I-NEXT: ret 648 %1 = icmp sle i32 %a, 0 649 %2 = zext i1 %1 to i32 650 ret i32 %2 651} 652 653define i32 @icmp_sle_constant_2046(i32 %a) nounwind { 654; RV32I-LABEL: icmp_sle_constant_2046: 655; RV32I: # %bb.0: 656; RV32I-NEXT: slti a0, a0, 2047 657; RV32I-NEXT: ret 658 %1 = icmp sle i32 %a, 2046 659 %2 = zext i1 %1 to i32 660 ret i32 %2 661} 662 663define i32 @icmp_sle_constant_2047(i32 %a) nounwind { 664; RV32I-LABEL: icmp_sle_constant_2047: 665; RV32I: # %bb.0: 666; RV32I-NEXT: li a1, 1 667; RV32I-NEXT: slli a1, a1, 11 668; RV32I-NEXT: slt a0, a0, a1 669; RV32I-NEXT: ret 670 %1 = icmp sle i32 %a, 2047 671 %2 = zext i1 %1 to i32 672 ret i32 %2 673} 674 675define i32 @icmp_sle_constant_neg_2049(i32 %a) nounwind { 676; RV32I-LABEL: icmp_sle_constant_neg_2049: 677; RV32I: # %bb.0: 678; RV32I-NEXT: slti a0, a0, -2048 679; RV32I-NEXT: ret 680 %1 = icmp sle i32 %a, -2049 681 %2 = zext i1 %1 to i32 682 ret i32 %2 683} 684 685define i32 @icmp_sle_constant_neg_2050(i32 %a) nounwind { 686; RV32I-LABEL: icmp_sle_constant_neg_2050: 687; RV32I: # %bb.0: 688; RV32I-NEXT: lui a1, 1048575 689; RV32I-NEXT: addi a1, a1, 2047 690; RV32I-NEXT: slt a0, a0, a1 691; RV32I-NEXT: ret 692 %1 = icmp sle i32 %a, -2050 693 %2 = zext i1 %1 to i32 694 ret i32 %2 695} 696