1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ 3; RUN: -target-abi ilp32f < %s | FileCheck %s 4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ 5; RUN: -target-abi lp64f < %s | FileCheck %s 6; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \ 7; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \ 9; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s 10; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \ 11; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN %s 12; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \ 13; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN %s 14; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \ 15; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN %s 16; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \ 17; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN %s 18 19define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) { 20; CHECK-LABEL: select_icmp_eq: 21; CHECK: # %bb.0: 22; CHECK-NEXT: beq a0, a1, .LBB0_2 23; CHECK-NEXT: # %bb.1: 24; CHECK-NEXT: fmv.h fa0, fa1 25; CHECK-NEXT: .LBB0_2: 26; CHECK-NEXT: ret 27; 28; CHECKIZHINX-LABEL: select_icmp_eq: 29; CHECKIZHINX: # %bb.0: 30; CHECKIZHINX-NEXT: beq a0, a1, .LBB0_2 31; CHECKIZHINX-NEXT: # %bb.1: 32; CHECKIZHINX-NEXT: mv a2, a3 33; CHECKIZHINX-NEXT: .LBB0_2: 34; CHECKIZHINX-NEXT: mv a0, a2 35; CHECKIZHINX-NEXT: ret 36; 37; CHECKIZFHMIN-LABEL: select_icmp_eq: 38; CHECKIZFHMIN: # %bb.0: 39; CHECKIZFHMIN-NEXT: beq a0, a1, .LBB0_2 40; CHECKIZFHMIN-NEXT: # %bb.1: 41; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 42; CHECKIZFHMIN-NEXT: .LBB0_2: 43; CHECKIZFHMIN-NEXT: ret 44; 45; CHECKIZHINXMIN-LABEL: select_icmp_eq: 46; CHECKIZHINXMIN: # %bb.0: 47; CHECKIZHINXMIN-NEXT: beq a0, a1, .LBB0_2 48; CHECKIZHINXMIN-NEXT: # %bb.1: 49; CHECKIZHINXMIN-NEXT: mv a2, a3 50; CHECKIZHINXMIN-NEXT: .LBB0_2: 51; CHECKIZHINXMIN-NEXT: mv a0, a2 52; CHECKIZHINXMIN-NEXT: ret 53 %1 = icmp eq i32 %a, %b 54 %2 = select i1 %1, half %c, half %d 55 ret half %2 56} 57 58define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) { 59; CHECK-LABEL: select_icmp_ne: 60; CHECK: # %bb.0: 61; CHECK-NEXT: bne a0, a1, .LBB1_2 62; CHECK-NEXT: # %bb.1: 63; CHECK-NEXT: fmv.h fa0, fa1 64; CHECK-NEXT: .LBB1_2: 65; CHECK-NEXT: ret 66; 67; CHECKIZHINX-LABEL: select_icmp_ne: 68; CHECKIZHINX: # %bb.0: 69; CHECKIZHINX-NEXT: bne a0, a1, .LBB1_2 70; CHECKIZHINX-NEXT: # %bb.1: 71; CHECKIZHINX-NEXT: mv a2, a3 72; CHECKIZHINX-NEXT: .LBB1_2: 73; CHECKIZHINX-NEXT: mv a0, a2 74; CHECKIZHINX-NEXT: ret 75; 76; CHECKIZFHMIN-LABEL: select_icmp_ne: 77; CHECKIZFHMIN: # %bb.0: 78; CHECKIZFHMIN-NEXT: bne a0, a1, .LBB1_2 79; CHECKIZFHMIN-NEXT: # %bb.1: 80; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 81; CHECKIZFHMIN-NEXT: .LBB1_2: 82; CHECKIZFHMIN-NEXT: ret 83; 84; CHECKIZHINXMIN-LABEL: select_icmp_ne: 85; CHECKIZHINXMIN: # %bb.0: 86; CHECKIZHINXMIN-NEXT: bne a0, a1, .LBB1_2 87; CHECKIZHINXMIN-NEXT: # %bb.1: 88; CHECKIZHINXMIN-NEXT: mv a2, a3 89; CHECKIZHINXMIN-NEXT: .LBB1_2: 90; CHECKIZHINXMIN-NEXT: mv a0, a2 91; CHECKIZHINXMIN-NEXT: ret 92 %1 = icmp ne i32 %a, %b 93 %2 = select i1 %1, half %c, half %d 94 ret half %2 95} 96 97define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) { 98; CHECK-LABEL: select_icmp_ugt: 99; CHECK: # %bb.0: 100; CHECK-NEXT: bltu a1, a0, .LBB2_2 101; CHECK-NEXT: # %bb.1: 102; CHECK-NEXT: fmv.h fa0, fa1 103; CHECK-NEXT: .LBB2_2: 104; CHECK-NEXT: ret 105; 106; CHECKIZHINX-LABEL: select_icmp_ugt: 107; CHECKIZHINX: # %bb.0: 108; CHECKIZHINX-NEXT: bltu a1, a0, .LBB2_2 109; CHECKIZHINX-NEXT: # %bb.1: 110; CHECKIZHINX-NEXT: mv a2, a3 111; CHECKIZHINX-NEXT: .LBB2_2: 112; CHECKIZHINX-NEXT: mv a0, a2 113; CHECKIZHINX-NEXT: ret 114; 115; CHECKIZFHMIN-LABEL: select_icmp_ugt: 116; CHECKIZFHMIN: # %bb.0: 117; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB2_2 118; CHECKIZFHMIN-NEXT: # %bb.1: 119; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 120; CHECKIZFHMIN-NEXT: .LBB2_2: 121; CHECKIZFHMIN-NEXT: ret 122; 123; CHECKIZHINXMIN-LABEL: select_icmp_ugt: 124; CHECKIZHINXMIN: # %bb.0: 125; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB2_2 126; CHECKIZHINXMIN-NEXT: # %bb.1: 127; CHECKIZHINXMIN-NEXT: mv a2, a3 128; CHECKIZHINXMIN-NEXT: .LBB2_2: 129; CHECKIZHINXMIN-NEXT: mv a0, a2 130; CHECKIZHINXMIN-NEXT: ret 131 %1 = icmp ugt i32 %a, %b 132 %2 = select i1 %1, half %c, half %d 133 ret half %2 134} 135 136define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) { 137; CHECK-LABEL: select_icmp_uge: 138; CHECK: # %bb.0: 139; CHECK-NEXT: bgeu a0, a1, .LBB3_2 140; CHECK-NEXT: # %bb.1: 141; CHECK-NEXT: fmv.h fa0, fa1 142; CHECK-NEXT: .LBB3_2: 143; CHECK-NEXT: ret 144; 145; CHECKIZHINX-LABEL: select_icmp_uge: 146; CHECKIZHINX: # %bb.0: 147; CHECKIZHINX-NEXT: bgeu a0, a1, .LBB3_2 148; CHECKIZHINX-NEXT: # %bb.1: 149; CHECKIZHINX-NEXT: mv a2, a3 150; CHECKIZHINX-NEXT: .LBB3_2: 151; CHECKIZHINX-NEXT: mv a0, a2 152; CHECKIZHINX-NEXT: ret 153; 154; CHECKIZFHMIN-LABEL: select_icmp_uge: 155; CHECKIZFHMIN: # %bb.0: 156; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2 157; CHECKIZFHMIN-NEXT: # %bb.1: 158; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 159; CHECKIZFHMIN-NEXT: .LBB3_2: 160; CHECKIZFHMIN-NEXT: ret 161; 162; CHECKIZHINXMIN-LABEL: select_icmp_uge: 163; CHECKIZHINXMIN: # %bb.0: 164; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2 165; CHECKIZHINXMIN-NEXT: # %bb.1: 166; CHECKIZHINXMIN-NEXT: mv a2, a3 167; CHECKIZHINXMIN-NEXT: .LBB3_2: 168; CHECKIZHINXMIN-NEXT: mv a0, a2 169; CHECKIZHINXMIN-NEXT: ret 170 %1 = icmp uge i32 %a, %b 171 %2 = select i1 %1, half %c, half %d 172 ret half %2 173} 174 175define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) { 176; CHECK-LABEL: select_icmp_ult: 177; CHECK: # %bb.0: 178; CHECK-NEXT: bltu a0, a1, .LBB4_2 179; CHECK-NEXT: # %bb.1: 180; CHECK-NEXT: fmv.h fa0, fa1 181; CHECK-NEXT: .LBB4_2: 182; CHECK-NEXT: ret 183; 184; CHECKIZHINX-LABEL: select_icmp_ult: 185; CHECKIZHINX: # %bb.0: 186; CHECKIZHINX-NEXT: bltu a0, a1, .LBB4_2 187; CHECKIZHINX-NEXT: # %bb.1: 188; CHECKIZHINX-NEXT: mv a2, a3 189; CHECKIZHINX-NEXT: .LBB4_2: 190; CHECKIZHINX-NEXT: mv a0, a2 191; CHECKIZHINX-NEXT: ret 192; 193; CHECKIZFHMIN-LABEL: select_icmp_ult: 194; CHECKIZFHMIN: # %bb.0: 195; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB4_2 196; CHECKIZFHMIN-NEXT: # %bb.1: 197; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 198; CHECKIZFHMIN-NEXT: .LBB4_2: 199; CHECKIZFHMIN-NEXT: ret 200; 201; CHECKIZHINXMIN-LABEL: select_icmp_ult: 202; CHECKIZHINXMIN: # %bb.0: 203; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB4_2 204; CHECKIZHINXMIN-NEXT: # %bb.1: 205; CHECKIZHINXMIN-NEXT: mv a2, a3 206; CHECKIZHINXMIN-NEXT: .LBB4_2: 207; CHECKIZHINXMIN-NEXT: mv a0, a2 208; CHECKIZHINXMIN-NEXT: ret 209 %1 = icmp ult i32 %a, %b 210 %2 = select i1 %1, half %c, half %d 211 ret half %2 212} 213 214define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) { 215; CHECK-LABEL: select_icmp_ule: 216; CHECK: # %bb.0: 217; CHECK-NEXT: bgeu a1, a0, .LBB5_2 218; CHECK-NEXT: # %bb.1: 219; CHECK-NEXT: fmv.h fa0, fa1 220; CHECK-NEXT: .LBB5_2: 221; CHECK-NEXT: ret 222; 223; CHECKIZHINX-LABEL: select_icmp_ule: 224; CHECKIZHINX: # %bb.0: 225; CHECKIZHINX-NEXT: bgeu a1, a0, .LBB5_2 226; CHECKIZHINX-NEXT: # %bb.1: 227; CHECKIZHINX-NEXT: mv a2, a3 228; CHECKIZHINX-NEXT: .LBB5_2: 229; CHECKIZHINX-NEXT: mv a0, a2 230; CHECKIZHINX-NEXT: ret 231; 232; CHECKIZFHMIN-LABEL: select_icmp_ule: 233; CHECKIZFHMIN: # %bb.0: 234; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2 235; CHECKIZFHMIN-NEXT: # %bb.1: 236; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 237; CHECKIZFHMIN-NEXT: .LBB5_2: 238; CHECKIZFHMIN-NEXT: ret 239; 240; CHECKIZHINXMIN-LABEL: select_icmp_ule: 241; CHECKIZHINXMIN: # %bb.0: 242; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2 243; CHECKIZHINXMIN-NEXT: # %bb.1: 244; CHECKIZHINXMIN-NEXT: mv a2, a3 245; CHECKIZHINXMIN-NEXT: .LBB5_2: 246; CHECKIZHINXMIN-NEXT: mv a0, a2 247; CHECKIZHINXMIN-NEXT: ret 248 %1 = icmp ule i32 %a, %b 249 %2 = select i1 %1, half %c, half %d 250 ret half %2 251} 252 253define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) { 254; CHECK-LABEL: select_icmp_sgt: 255; CHECK: # %bb.0: 256; CHECK-NEXT: blt a1, a0, .LBB6_2 257; CHECK-NEXT: # %bb.1: 258; CHECK-NEXT: fmv.h fa0, fa1 259; CHECK-NEXT: .LBB6_2: 260; CHECK-NEXT: ret 261; 262; CHECKIZHINX-LABEL: select_icmp_sgt: 263; CHECKIZHINX: # %bb.0: 264; CHECKIZHINX-NEXT: blt a1, a0, .LBB6_2 265; CHECKIZHINX-NEXT: # %bb.1: 266; CHECKIZHINX-NEXT: mv a2, a3 267; CHECKIZHINX-NEXT: .LBB6_2: 268; CHECKIZHINX-NEXT: mv a0, a2 269; CHECKIZHINX-NEXT: ret 270; 271; CHECKIZFHMIN-LABEL: select_icmp_sgt: 272; CHECKIZFHMIN: # %bb.0: 273; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB6_2 274; CHECKIZFHMIN-NEXT: # %bb.1: 275; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 276; CHECKIZFHMIN-NEXT: .LBB6_2: 277; CHECKIZFHMIN-NEXT: ret 278; 279; CHECKIZHINXMIN-LABEL: select_icmp_sgt: 280; CHECKIZHINXMIN: # %bb.0: 281; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB6_2 282; CHECKIZHINXMIN-NEXT: # %bb.1: 283; CHECKIZHINXMIN-NEXT: mv a2, a3 284; CHECKIZHINXMIN-NEXT: .LBB6_2: 285; CHECKIZHINXMIN-NEXT: mv a0, a2 286; CHECKIZHINXMIN-NEXT: ret 287 %1 = icmp sgt i32 %a, %b 288 %2 = select i1 %1, half %c, half %d 289 ret half %2 290} 291 292define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) { 293; CHECK-LABEL: select_icmp_sge: 294; CHECK: # %bb.0: 295; CHECK-NEXT: bge a0, a1, .LBB7_2 296; CHECK-NEXT: # %bb.1: 297; CHECK-NEXT: fmv.h fa0, fa1 298; CHECK-NEXT: .LBB7_2: 299; CHECK-NEXT: ret 300; 301; CHECKIZHINX-LABEL: select_icmp_sge: 302; CHECKIZHINX: # %bb.0: 303; CHECKIZHINX-NEXT: bge a0, a1, .LBB7_2 304; CHECKIZHINX-NEXT: # %bb.1: 305; CHECKIZHINX-NEXT: mv a2, a3 306; CHECKIZHINX-NEXT: .LBB7_2: 307; CHECKIZHINX-NEXT: mv a0, a2 308; CHECKIZHINX-NEXT: ret 309; 310; CHECKIZFHMIN-LABEL: select_icmp_sge: 311; CHECKIZFHMIN: # %bb.0: 312; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2 313; CHECKIZFHMIN-NEXT: # %bb.1: 314; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 315; CHECKIZFHMIN-NEXT: .LBB7_2: 316; CHECKIZFHMIN-NEXT: ret 317; 318; CHECKIZHINXMIN-LABEL: select_icmp_sge: 319; CHECKIZHINXMIN: # %bb.0: 320; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2 321; CHECKIZHINXMIN-NEXT: # %bb.1: 322; CHECKIZHINXMIN-NEXT: mv a2, a3 323; CHECKIZHINXMIN-NEXT: .LBB7_2: 324; CHECKIZHINXMIN-NEXT: mv a0, a2 325; CHECKIZHINXMIN-NEXT: ret 326 %1 = icmp sge i32 %a, %b 327 %2 = select i1 %1, half %c, half %d 328 ret half %2 329} 330 331define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) { 332; CHECK-LABEL: select_icmp_slt: 333; CHECK: # %bb.0: 334; CHECK-NEXT: blt a0, a1, .LBB8_2 335; CHECK-NEXT: # %bb.1: 336; CHECK-NEXT: fmv.h fa0, fa1 337; CHECK-NEXT: .LBB8_2: 338; CHECK-NEXT: ret 339; 340; CHECKIZHINX-LABEL: select_icmp_slt: 341; CHECKIZHINX: # %bb.0: 342; CHECKIZHINX-NEXT: blt a0, a1, .LBB8_2 343; CHECKIZHINX-NEXT: # %bb.1: 344; CHECKIZHINX-NEXT: mv a2, a3 345; CHECKIZHINX-NEXT: .LBB8_2: 346; CHECKIZHINX-NEXT: mv a0, a2 347; CHECKIZHINX-NEXT: ret 348; 349; CHECKIZFHMIN-LABEL: select_icmp_slt: 350; CHECKIZFHMIN: # %bb.0: 351; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB8_2 352; CHECKIZFHMIN-NEXT: # %bb.1: 353; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 354; CHECKIZFHMIN-NEXT: .LBB8_2: 355; CHECKIZFHMIN-NEXT: ret 356; 357; CHECKIZHINXMIN-LABEL: select_icmp_slt: 358; CHECKIZHINXMIN: # %bb.0: 359; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB8_2 360; CHECKIZHINXMIN-NEXT: # %bb.1: 361; CHECKIZHINXMIN-NEXT: mv a2, a3 362; CHECKIZHINXMIN-NEXT: .LBB8_2: 363; CHECKIZHINXMIN-NEXT: mv a0, a2 364; CHECKIZHINXMIN-NEXT: ret 365 %1 = icmp slt i32 %a, %b 366 %2 = select i1 %1, half %c, half %d 367 ret half %2 368} 369 370define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) { 371; CHECK-LABEL: select_icmp_sle: 372; CHECK: # %bb.0: 373; CHECK-NEXT: bge a1, a0, .LBB9_2 374; CHECK-NEXT: # %bb.1: 375; CHECK-NEXT: fmv.h fa0, fa1 376; CHECK-NEXT: .LBB9_2: 377; CHECK-NEXT: ret 378; 379; CHECKIZHINX-LABEL: select_icmp_sle: 380; CHECKIZHINX: # %bb.0: 381; CHECKIZHINX-NEXT: bge a1, a0, .LBB9_2 382; CHECKIZHINX-NEXT: # %bb.1: 383; CHECKIZHINX-NEXT: mv a2, a3 384; CHECKIZHINX-NEXT: .LBB9_2: 385; CHECKIZHINX-NEXT: mv a0, a2 386; CHECKIZHINX-NEXT: ret 387; 388; CHECKIZFHMIN-LABEL: select_icmp_sle: 389; CHECKIZFHMIN: # %bb.0: 390; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2 391; CHECKIZFHMIN-NEXT: # %bb.1: 392; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1 393; CHECKIZFHMIN-NEXT: .LBB9_2: 394; CHECKIZFHMIN-NEXT: ret 395; 396; CHECKIZHINXMIN-LABEL: select_icmp_sle: 397; CHECKIZHINXMIN: # %bb.0: 398; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2 399; CHECKIZHINXMIN-NEXT: # %bb.1: 400; CHECKIZHINXMIN-NEXT: mv a2, a3 401; CHECKIZHINXMIN-NEXT: .LBB9_2: 402; CHECKIZHINXMIN-NEXT: mv a0, a2 403; CHECKIZHINXMIN-NEXT: ret 404 %1 = icmp sle i32 %a, %b 405 %2 = select i1 %1, half %c, half %d 406 ret half %2 407} 408 409define half @select_icmp_slt_one(i32 signext %a) { 410; CHECK-LABEL: select_icmp_slt_one: 411; CHECK: # %bb.0: 412; CHECK-NEXT: slti a0, a0, 1 413; CHECK-NEXT: fcvt.h.w fa0, a0 414; CHECK-NEXT: ret 415; 416; CHECKIZHINX-LABEL: select_icmp_slt_one: 417; CHECKIZHINX: # %bb.0: 418; CHECKIZHINX-NEXT: slti a0, a0, 1 419; CHECKIZHINX-NEXT: fcvt.h.w a0, a0 420; CHECKIZHINX-NEXT: ret 421; 422; CHECKIZFHMIN-LABEL: select_icmp_slt_one: 423; CHECKIZFHMIN: # %bb.0: 424; CHECKIZFHMIN-NEXT: slti a0, a0, 1 425; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0 426; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 427; CHECKIZFHMIN-NEXT: ret 428; 429; CHECKIZHINXMIN-LABEL: select_icmp_slt_one: 430; CHECKIZHINXMIN: # %bb.0: 431; CHECKIZHINXMIN-NEXT: slti a0, a0, 1 432; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0 433; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 434; CHECKIZHINXMIN-NEXT: ret 435 %1 = icmp slt i32 %a, 1 436 %2 = select i1 %1, half 1.000000e+00, half 0.000000e+00 437 ret half %2 438} 439 440define half @select_icmp_sgt_zero(i32 signext %a) { 441; CHECK-LABEL: select_icmp_sgt_zero: 442; CHECK: # %bb.0: 443; CHECK-NEXT: slti a0, a0, 1 444; CHECK-NEXT: fcvt.h.w fa0, a0 445; CHECK-NEXT: ret 446; 447; CHECKIZHINX-LABEL: select_icmp_sgt_zero: 448; CHECKIZHINX: # %bb.0: 449; CHECKIZHINX-NEXT: slti a0, a0, 1 450; CHECKIZHINX-NEXT: fcvt.h.w a0, a0 451; CHECKIZHINX-NEXT: ret 452; 453; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero: 454; CHECKIZFHMIN: # %bb.0: 455; CHECKIZFHMIN-NEXT: slti a0, a0, 1 456; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0 457; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 458; CHECKIZFHMIN-NEXT: ret 459; 460; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero: 461; CHECKIZHINXMIN: # %bb.0: 462; CHECKIZHINXMIN-NEXT: slti a0, a0, 1 463; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0 464; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 465; CHECKIZHINXMIN-NEXT: ret 466 %1 = icmp sgt i32 %a, 0 467 %2 = select i1 %1, half 0.000000e+00, half 1.000000e+00 468 ret half %2 469} 470