1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \ 3; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s 4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \ 5; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s 6; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \ 7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \ 9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s 10; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \ 11; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s 12; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \ 13; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s 14; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \ 15; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s 16; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \ 17; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s 18 19define signext i32 @test_floor_si32(half %x) { 20; CHECKIZFH-LABEL: test_floor_si32: 21; CHECKIZFH: # %bb.0: 22; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn 23; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 24; CHECKIZFH-NEXT: seqz a1, a1 25; CHECKIZFH-NEXT: addi a1, a1, -1 26; CHECKIZFH-NEXT: and a0, a1, a0 27; CHECKIZFH-NEXT: ret 28; 29; CHECKIZHINX-LABEL: test_floor_si32: 30; CHECKIZHINX: # %bb.0: 31; CHECKIZHINX-NEXT: li a1, 25 32; CHECKIZHINX-NEXT: slli a1, a1, 10 33; CHECKIZHINX-NEXT: fabs.h a2, a0 34; CHECKIZHINX-NEXT: flt.h a1, a2, a1 35; CHECKIZHINX-NEXT: beqz a1, .LBB0_2 36; CHECKIZHINX-NEXT: # %bb.1: 37; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn 38; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn 39; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0 40; CHECKIZHINX-NEXT: .LBB0_2: 41; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 42; CHECKIZHINX-NEXT: feq.h a0, a0, a0 43; CHECKIZHINX-NEXT: seqz a0, a0 44; CHECKIZHINX-NEXT: addi a0, a0, -1 45; CHECKIZHINX-NEXT: and a0, a0, a1 46; CHECKIZHINX-NEXT: ret 47; 48; CHECKIZFHMIN-LABEL: test_floor_si32: 49; CHECKIZFHMIN: # %bb.0: 50; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 51; CHECKIZFHMIN-NEXT: lui a0, 307200 52; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0 53; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5 54; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4 55; CHECKIZFHMIN-NEXT: beqz a0, .LBB0_2 56; CHECKIZFHMIN-NEXT: # %bb.1: 57; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 58; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 59; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 60; CHECKIZFHMIN-NEXT: .LBB0_2: 61; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5 62; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 63; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 64; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 65; CHECKIZFHMIN-NEXT: seqz a1, a1 66; CHECKIZFHMIN-NEXT: addi a1, a1, -1 67; CHECKIZFHMIN-NEXT: and a0, a1, a0 68; CHECKIZFHMIN-NEXT: ret 69; 70; CHECKIZHINXMIN-LABEL: test_floor_si32: 71; CHECKIZHINXMIN: # %bb.0: 72; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 73; CHECKIZHINXMIN-NEXT: lui a1, 307200 74; CHECKIZHINXMIN-NEXT: fabs.s a2, a0 75; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1 76; CHECKIZHINXMIN-NEXT: beqz a1, .LBB0_2 77; CHECKIZHINXMIN-NEXT: # %bb.1: 78; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 79; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 80; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0 81; CHECKIZHINXMIN-NEXT: .LBB0_2: 82; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 83; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 84; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 85; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 86; CHECKIZHINXMIN-NEXT: seqz a0, a0 87; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 88; CHECKIZHINXMIN-NEXT: and a0, a0, a1 89; CHECKIZHINXMIN-NEXT: ret 90 %a = call half @llvm.floor.f16(half %x) 91 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a) 92 ret i32 %b 93} 94 95define i64 @test_floor_si64(half %x) nounwind { 96; RV32IZFH-LABEL: test_floor_si64: 97; RV32IZFH: # %bb.0: 98; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0) 99; RV32IZFH-NEXT: flh fa5, %lo(.LCPI1_0)(a0) 100; RV32IZFH-NEXT: fabs.h fa4, fa0 101; RV32IZFH-NEXT: flt.h a0, fa4, fa5 102; RV32IZFH-NEXT: beqz a0, .LBB1_2 103; RV32IZFH-NEXT: # %bb.1: 104; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn 105; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn 106; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 107; RV32IZFH-NEXT: .LBB1_2: 108; RV32IZFH-NEXT: addi sp, sp, -16 109; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 110; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 111; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 112; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 113; RV32IZFH-NEXT: lui a0, 913408 114; RV32IZFH-NEXT: fmv.w.x fa5, a0 115; RV32IZFH-NEXT: fle.s s0, fa5, fs0 116; RV32IZFH-NEXT: fmv.s fa0, fs0 117; RV32IZFH-NEXT: call __fixsfdi 118; RV32IZFH-NEXT: lui a3, 524288 119; RV32IZFH-NEXT: lui a2, 524288 120; RV32IZFH-NEXT: beqz s0, .LBB1_4 121; RV32IZFH-NEXT: # %bb.3: 122; RV32IZFH-NEXT: mv a2, a1 123; RV32IZFH-NEXT: .LBB1_4: 124; RV32IZFH-NEXT: lui a1, %hi(.LCPI1_1) 125; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a1) 126; RV32IZFH-NEXT: flt.s a1, fa5, fs0 127; RV32IZFH-NEXT: beqz a1, .LBB1_6 128; RV32IZFH-NEXT: # %bb.5: 129; RV32IZFH-NEXT: addi a2, a3, -1 130; RV32IZFH-NEXT: .LBB1_6: 131; RV32IZFH-NEXT: feq.s a3, fs0, fs0 132; RV32IZFH-NEXT: neg a4, s0 133; RV32IZFH-NEXT: neg a5, a1 134; RV32IZFH-NEXT: neg a3, a3 135; RV32IZFH-NEXT: and a0, a4, a0 136; RV32IZFH-NEXT: and a1, a3, a2 137; RV32IZFH-NEXT: or a0, a5, a0 138; RV32IZFH-NEXT: and a0, a3, a0 139; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 140; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 141; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 142; RV32IZFH-NEXT: addi sp, sp, 16 143; RV32IZFH-NEXT: ret 144; 145; RV64IZFH-LABEL: test_floor_si64: 146; RV64IZFH: # %bb.0: 147; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn 148; RV64IZFH-NEXT: feq.h a1, fa0, fa0 149; RV64IZFH-NEXT: seqz a1, a1 150; RV64IZFH-NEXT: addi a1, a1, -1 151; RV64IZFH-NEXT: and a0, a1, a0 152; RV64IZFH-NEXT: ret 153; 154; RV32IZHINX-LABEL: test_floor_si64: 155; RV32IZHINX: # %bb.0: 156; RV32IZHINX-NEXT: li a1, 25 157; RV32IZHINX-NEXT: slli a1, a1, 10 158; RV32IZHINX-NEXT: fabs.h a2, a0 159; RV32IZHINX-NEXT: flt.h a1, a2, a1 160; RV32IZHINX-NEXT: beqz a1, .LBB1_2 161; RV32IZHINX-NEXT: # %bb.1: 162; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn 163; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn 164; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 165; RV32IZHINX-NEXT: .LBB1_2: 166; RV32IZHINX-NEXT: addi sp, sp, -16 167; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 168; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 169; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 170; RV32IZHINX-NEXT: fcvt.s.h s0, a0 171; RV32IZHINX-NEXT: lui a0, 913408 172; RV32IZHINX-NEXT: fle.s s1, a0, s0 173; RV32IZHINX-NEXT: mv a0, s0 174; RV32IZHINX-NEXT: call __fixsfdi 175; RV32IZHINX-NEXT: lui a3, 524288 176; RV32IZHINX-NEXT: lui a2, 524288 177; RV32IZHINX-NEXT: beqz s1, .LBB1_4 178; RV32IZHINX-NEXT: # %bb.3: 179; RV32IZHINX-NEXT: mv a2, a1 180; RV32IZHINX-NEXT: .LBB1_4: 181; RV32IZHINX-NEXT: lui a1, 389120 182; RV32IZHINX-NEXT: addi a1, a1, -1 183; RV32IZHINX-NEXT: flt.s a1, a1, s0 184; RV32IZHINX-NEXT: beqz a1, .LBB1_6 185; RV32IZHINX-NEXT: # %bb.5: 186; RV32IZHINX-NEXT: addi a2, a3, -1 187; RV32IZHINX-NEXT: .LBB1_6: 188; RV32IZHINX-NEXT: feq.s a3, s0, s0 189; RV32IZHINX-NEXT: neg a4, s1 190; RV32IZHINX-NEXT: neg a5, a1 191; RV32IZHINX-NEXT: neg a3, a3 192; RV32IZHINX-NEXT: and a0, a4, a0 193; RV32IZHINX-NEXT: and a1, a3, a2 194; RV32IZHINX-NEXT: or a0, a5, a0 195; RV32IZHINX-NEXT: and a0, a3, a0 196; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 197; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 198; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 199; RV32IZHINX-NEXT: addi sp, sp, 16 200; RV32IZHINX-NEXT: ret 201; 202; RV64IZHINX-LABEL: test_floor_si64: 203; RV64IZHINX: # %bb.0: 204; RV64IZHINX-NEXT: li a1, 25 205; RV64IZHINX-NEXT: slli a1, a1, 10 206; RV64IZHINX-NEXT: fabs.h a2, a0 207; RV64IZHINX-NEXT: flt.h a1, a2, a1 208; RV64IZHINX-NEXT: beqz a1, .LBB1_2 209; RV64IZHINX-NEXT: # %bb.1: 210; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn 211; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn 212; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 213; RV64IZHINX-NEXT: .LBB1_2: 214; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz 215; RV64IZHINX-NEXT: feq.h a0, a0, a0 216; RV64IZHINX-NEXT: seqz a0, a0 217; RV64IZHINX-NEXT: addi a0, a0, -1 218; RV64IZHINX-NEXT: and a0, a0, a1 219; RV64IZHINX-NEXT: ret 220; 221; RV32IZFHMIN-LABEL: test_floor_si64: 222; RV32IZFHMIN: # %bb.0: 223; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 224; RV32IZFHMIN-NEXT: lui a0, 307200 225; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 226; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 227; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 228; RV32IZFHMIN-NEXT: beqz a0, .LBB1_2 229; RV32IZFHMIN-NEXT: # %bb.1: 230; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 231; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 232; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 233; RV32IZFHMIN-NEXT: .LBB1_2: 234; RV32IZFHMIN-NEXT: addi sp, sp, -16 235; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 236; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 237; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 238; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 239; RV32IZFHMIN-NEXT: lui a0, 913408 240; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 241; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 242; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 243; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 244; RV32IZFHMIN-NEXT: call __fixsfdi 245; RV32IZFHMIN-NEXT: lui a3, 524288 246; RV32IZFHMIN-NEXT: lui a2, 524288 247; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4 248; RV32IZFHMIN-NEXT: # %bb.3: 249; RV32IZFHMIN-NEXT: mv a2, a1 250; RV32IZFHMIN-NEXT: .LBB1_4: 251; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0) 252; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a1) 253; RV32IZFHMIN-NEXT: flt.s a1, fa5, fs0 254; RV32IZFHMIN-NEXT: beqz a1, .LBB1_6 255; RV32IZFHMIN-NEXT: # %bb.5: 256; RV32IZFHMIN-NEXT: addi a2, a3, -1 257; RV32IZFHMIN-NEXT: .LBB1_6: 258; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 259; RV32IZFHMIN-NEXT: neg a4, s0 260; RV32IZFHMIN-NEXT: neg a5, a1 261; RV32IZFHMIN-NEXT: neg a3, a3 262; RV32IZFHMIN-NEXT: and a0, a4, a0 263; RV32IZFHMIN-NEXT: and a1, a3, a2 264; RV32IZFHMIN-NEXT: or a0, a5, a0 265; RV32IZFHMIN-NEXT: and a0, a3, a0 266; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 267; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 268; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 269; RV32IZFHMIN-NEXT: addi sp, sp, 16 270; RV32IZFHMIN-NEXT: ret 271; 272; RV64IZFHMIN-LABEL: test_floor_si64: 273; RV64IZFHMIN: # %bb.0: 274; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 275; RV64IZFHMIN-NEXT: lui a0, 307200 276; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 277; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 278; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 279; RV64IZFHMIN-NEXT: beqz a0, .LBB1_2 280; RV64IZFHMIN-NEXT: # %bb.1: 281; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 282; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 283; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 284; RV64IZFHMIN-NEXT: .LBB1_2: 285; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 286; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 287; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz 288; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 289; RV64IZFHMIN-NEXT: seqz a1, a1 290; RV64IZFHMIN-NEXT: addi a1, a1, -1 291; RV64IZFHMIN-NEXT: and a0, a1, a0 292; RV64IZFHMIN-NEXT: ret 293; 294; RV32IZHINXMIN-LABEL: test_floor_si64: 295; RV32IZHINXMIN: # %bb.0: 296; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 297; RV32IZHINXMIN-NEXT: lui a1, 307200 298; RV32IZHINXMIN-NEXT: fabs.s a2, a0 299; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 300; RV32IZHINXMIN-NEXT: beqz a1, .LBB1_2 301; RV32IZHINXMIN-NEXT: # %bb.1: 302; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 303; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 304; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 305; RV32IZHINXMIN-NEXT: .LBB1_2: 306; RV32IZHINXMIN-NEXT: addi sp, sp, -16 307; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 308; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 309; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 310; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 311; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 312; RV32IZHINXMIN-NEXT: lui a0, 913408 313; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 314; RV32IZHINXMIN-NEXT: mv a0, s0 315; RV32IZHINXMIN-NEXT: call __fixsfdi 316; RV32IZHINXMIN-NEXT: lui a3, 524288 317; RV32IZHINXMIN-NEXT: lui a2, 524288 318; RV32IZHINXMIN-NEXT: beqz s1, .LBB1_4 319; RV32IZHINXMIN-NEXT: # %bb.3: 320; RV32IZHINXMIN-NEXT: mv a2, a1 321; RV32IZHINXMIN-NEXT: .LBB1_4: 322; RV32IZHINXMIN-NEXT: lui a1, 389120 323; RV32IZHINXMIN-NEXT: addi a1, a1, -1 324; RV32IZHINXMIN-NEXT: flt.s a1, a1, s0 325; RV32IZHINXMIN-NEXT: beqz a1, .LBB1_6 326; RV32IZHINXMIN-NEXT: # %bb.5: 327; RV32IZHINXMIN-NEXT: addi a2, a3, -1 328; RV32IZHINXMIN-NEXT: .LBB1_6: 329; RV32IZHINXMIN-NEXT: feq.s a3, s0, s0 330; RV32IZHINXMIN-NEXT: neg a4, s1 331; RV32IZHINXMIN-NEXT: neg a5, a1 332; RV32IZHINXMIN-NEXT: neg a3, a3 333; RV32IZHINXMIN-NEXT: and a0, a4, a0 334; RV32IZHINXMIN-NEXT: and a1, a3, a2 335; RV32IZHINXMIN-NEXT: or a0, a5, a0 336; RV32IZHINXMIN-NEXT: and a0, a3, a0 337; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 338; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 339; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 340; RV32IZHINXMIN-NEXT: addi sp, sp, 16 341; RV32IZHINXMIN-NEXT: ret 342; 343; RV64IZHINXMIN-LABEL: test_floor_si64: 344; RV64IZHINXMIN: # %bb.0: 345; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 346; RV64IZHINXMIN-NEXT: lui a1, 307200 347; RV64IZHINXMIN-NEXT: fabs.s a2, a0 348; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 349; RV64IZHINXMIN-NEXT: beqz a1, .LBB1_2 350; RV64IZHINXMIN-NEXT: # %bb.1: 351; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 352; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 353; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 354; RV64IZHINXMIN-NEXT: .LBB1_2: 355; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 356; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 357; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz 358; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 359; RV64IZHINXMIN-NEXT: seqz a0, a0 360; RV64IZHINXMIN-NEXT: addi a0, a0, -1 361; RV64IZHINXMIN-NEXT: and a0, a0, a1 362; RV64IZHINXMIN-NEXT: ret 363 %a = call half @llvm.floor.f16(half %x) 364 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a) 365 ret i64 %b 366} 367 368define signext i32 @test_floor_ui32(half %x) { 369; CHECKIZFH-LABEL: test_floor_ui32: 370; CHECKIZFH: # %bb.0: 371; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rdn 372; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 373; CHECKIZFH-NEXT: seqz a1, a1 374; CHECKIZFH-NEXT: addi a1, a1, -1 375; CHECKIZFH-NEXT: and a0, a1, a0 376; CHECKIZFH-NEXT: ret 377; 378; RV32IZHINX-LABEL: test_floor_ui32: 379; RV32IZHINX: # %bb.0: 380; RV32IZHINX-NEXT: li a1, 25 381; RV32IZHINX-NEXT: slli a1, a1, 10 382; RV32IZHINX-NEXT: fabs.h a2, a0 383; RV32IZHINX-NEXT: flt.h a1, a2, a1 384; RV32IZHINX-NEXT: beqz a1, .LBB2_2 385; RV32IZHINX-NEXT: # %bb.1: 386; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn 387; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn 388; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 389; RV32IZHINX-NEXT: .LBB2_2: 390; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 391; RV32IZHINX-NEXT: feq.h a0, a0, a0 392; RV32IZHINX-NEXT: seqz a0, a0 393; RV32IZHINX-NEXT: addi a0, a0, -1 394; RV32IZHINX-NEXT: and a0, a0, a1 395; RV32IZHINX-NEXT: ret 396; 397; RV64IZHINX-LABEL: test_floor_ui32: 398; RV64IZHINX: # %bb.0: 399; RV64IZHINX-NEXT: li a1, 25 400; RV64IZHINX-NEXT: slli a1, a1, 10 401; RV64IZHINX-NEXT: fabs.h a2, a0 402; RV64IZHINX-NEXT: flt.h a1, a2, a1 403; RV64IZHINX-NEXT: beqz a1, .LBB2_2 404; RV64IZHINX-NEXT: # %bb.1: 405; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn 406; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn 407; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 408; RV64IZHINX-NEXT: .LBB2_2: 409; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 410; RV64IZHINX-NEXT: feq.h a0, a0, a0 411; RV64IZHINX-NEXT: seqz a0, a0 412; RV64IZHINX-NEXT: addiw a0, a0, -1 413; RV64IZHINX-NEXT: and a0, a1, a0 414; RV64IZHINX-NEXT: ret 415; 416; RV32IZFHMIN-LABEL: test_floor_ui32: 417; RV32IZFHMIN: # %bb.0: 418; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 419; RV32IZFHMIN-NEXT: lui a0, 307200 420; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 421; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 422; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 423; RV32IZFHMIN-NEXT: beqz a0, .LBB2_2 424; RV32IZFHMIN-NEXT: # %bb.1: 425; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 426; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 427; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 428; RV32IZFHMIN-NEXT: .LBB2_2: 429; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 430; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 431; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 432; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5 433; RV32IZFHMIN-NEXT: seqz a1, a1 434; RV32IZFHMIN-NEXT: addi a1, a1, -1 435; RV32IZFHMIN-NEXT: and a0, a1, a0 436; RV32IZFHMIN-NEXT: ret 437; 438; RV64IZFHMIN-LABEL: test_floor_ui32: 439; RV64IZFHMIN: # %bb.0: 440; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 441; RV64IZFHMIN-NEXT: lui a0, 307200 442; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 443; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 444; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 445; RV64IZFHMIN-NEXT: beqz a0, .LBB2_2 446; RV64IZFHMIN-NEXT: # %bb.1: 447; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 448; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 449; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 450; RV64IZFHMIN-NEXT: .LBB2_2: 451; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 452; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 453; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 454; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 455; RV64IZFHMIN-NEXT: seqz a1, a1 456; RV64IZFHMIN-NEXT: addiw a1, a1, -1 457; RV64IZFHMIN-NEXT: and a0, a0, a1 458; RV64IZFHMIN-NEXT: ret 459; 460; RV32IZHINXMIN-LABEL: test_floor_ui32: 461; RV32IZHINXMIN: # %bb.0: 462; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 463; RV32IZHINXMIN-NEXT: lui a1, 307200 464; RV32IZHINXMIN-NEXT: fabs.s a2, a0 465; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 466; RV32IZHINXMIN-NEXT: beqz a1, .LBB2_2 467; RV32IZHINXMIN-NEXT: # %bb.1: 468; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 469; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 470; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 471; RV32IZHINXMIN-NEXT: .LBB2_2: 472; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 473; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 474; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 475; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0 476; RV32IZHINXMIN-NEXT: seqz a0, a0 477; RV32IZHINXMIN-NEXT: addi a0, a0, -1 478; RV32IZHINXMIN-NEXT: and a0, a0, a1 479; RV32IZHINXMIN-NEXT: ret 480; 481; RV64IZHINXMIN-LABEL: test_floor_ui32: 482; RV64IZHINXMIN: # %bb.0: 483; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 484; RV64IZHINXMIN-NEXT: lui a1, 307200 485; RV64IZHINXMIN-NEXT: fabs.s a2, a0 486; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 487; RV64IZHINXMIN-NEXT: beqz a1, .LBB2_2 488; RV64IZHINXMIN-NEXT: # %bb.1: 489; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 490; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 491; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 492; RV64IZHINXMIN-NEXT: .LBB2_2: 493; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 494; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 495; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 496; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 497; RV64IZHINXMIN-NEXT: seqz a0, a0 498; RV64IZHINXMIN-NEXT: addiw a0, a0, -1 499; RV64IZHINXMIN-NEXT: and a0, a1, a0 500; RV64IZHINXMIN-NEXT: ret 501 %a = call half @llvm.floor.f16(half %x) 502 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a) 503 ret i32 %b 504} 505 506define i64 @test_floor_ui64(half %x) nounwind { 507; RV32IZFH-LABEL: test_floor_ui64: 508; RV32IZFH: # %bb.0: 509; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0) 510; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0) 511; RV32IZFH-NEXT: fabs.h fa4, fa0 512; RV32IZFH-NEXT: flt.h a0, fa4, fa5 513; RV32IZFH-NEXT: beqz a0, .LBB3_2 514; RV32IZFH-NEXT: # %bb.1: 515; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn 516; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn 517; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 518; RV32IZFH-NEXT: .LBB3_2: 519; RV32IZFH-NEXT: addi sp, sp, -16 520; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 521; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 522; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 523; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 524; RV32IZFH-NEXT: fmv.w.x fa5, zero 525; RV32IZFH-NEXT: fle.s a0, fa5, fs0 526; RV32IZFH-NEXT: neg s0, a0 527; RV32IZFH-NEXT: fmv.s fa0, fs0 528; RV32IZFH-NEXT: call __fixunssfdi 529; RV32IZFH-NEXT: lui a2, %hi(.LCPI3_1) 530; RV32IZFH-NEXT: flw fa5, %lo(.LCPI3_1)(a2) 531; RV32IZFH-NEXT: and a0, s0, a0 532; RV32IZFH-NEXT: and a1, s0, a1 533; RV32IZFH-NEXT: flt.s a2, fa5, fs0 534; RV32IZFH-NEXT: neg a2, a2 535; RV32IZFH-NEXT: or a0, a2, a0 536; RV32IZFH-NEXT: or a1, a2, a1 537; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 538; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 539; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 540; RV32IZFH-NEXT: addi sp, sp, 16 541; RV32IZFH-NEXT: ret 542; 543; RV64IZFH-LABEL: test_floor_ui64: 544; RV64IZFH: # %bb.0: 545; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn 546; RV64IZFH-NEXT: feq.h a1, fa0, fa0 547; RV64IZFH-NEXT: seqz a1, a1 548; RV64IZFH-NEXT: addi a1, a1, -1 549; RV64IZFH-NEXT: and a0, a1, a0 550; RV64IZFH-NEXT: ret 551; 552; RV32IZHINX-LABEL: test_floor_ui64: 553; RV32IZHINX: # %bb.0: 554; RV32IZHINX-NEXT: li a1, 25 555; RV32IZHINX-NEXT: slli a1, a1, 10 556; RV32IZHINX-NEXT: fabs.h a2, a0 557; RV32IZHINX-NEXT: flt.h a1, a2, a1 558; RV32IZHINX-NEXT: beqz a1, .LBB3_2 559; RV32IZHINX-NEXT: # %bb.1: 560; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn 561; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn 562; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 563; RV32IZHINX-NEXT: .LBB3_2: 564; RV32IZHINX-NEXT: addi sp, sp, -16 565; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 566; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 567; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 568; RV32IZHINX-NEXT: fcvt.s.h s0, a0 569; RV32IZHINX-NEXT: fle.s a0, zero, s0 570; RV32IZHINX-NEXT: neg s1, a0 571; RV32IZHINX-NEXT: mv a0, s0 572; RV32IZHINX-NEXT: call __fixunssfdi 573; RV32IZHINX-NEXT: and a0, s1, a0 574; RV32IZHINX-NEXT: lui a2, 391168 575; RV32IZHINX-NEXT: and a1, s1, a1 576; RV32IZHINX-NEXT: addi a2, a2, -1 577; RV32IZHINX-NEXT: flt.s a2, a2, s0 578; RV32IZHINX-NEXT: neg a2, a2 579; RV32IZHINX-NEXT: or a0, a2, a0 580; RV32IZHINX-NEXT: or a1, a2, a1 581; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 582; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 583; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 584; RV32IZHINX-NEXT: addi sp, sp, 16 585; RV32IZHINX-NEXT: ret 586; 587; RV64IZHINX-LABEL: test_floor_ui64: 588; RV64IZHINX: # %bb.0: 589; RV64IZHINX-NEXT: li a1, 25 590; RV64IZHINX-NEXT: slli a1, a1, 10 591; RV64IZHINX-NEXT: fabs.h a2, a0 592; RV64IZHINX-NEXT: flt.h a1, a2, a1 593; RV64IZHINX-NEXT: beqz a1, .LBB3_2 594; RV64IZHINX-NEXT: # %bb.1: 595; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn 596; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn 597; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 598; RV64IZHINX-NEXT: .LBB3_2: 599; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz 600; RV64IZHINX-NEXT: feq.h a0, a0, a0 601; RV64IZHINX-NEXT: seqz a0, a0 602; RV64IZHINX-NEXT: addi a0, a0, -1 603; RV64IZHINX-NEXT: and a0, a0, a1 604; RV64IZHINX-NEXT: ret 605; 606; RV32IZFHMIN-LABEL: test_floor_ui64: 607; RV32IZFHMIN: # %bb.0: 608; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 609; RV32IZFHMIN-NEXT: lui a0, 307200 610; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 611; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 612; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 613; RV32IZFHMIN-NEXT: beqz a0, .LBB3_2 614; RV32IZFHMIN-NEXT: # %bb.1: 615; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 616; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 617; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 618; RV32IZFHMIN-NEXT: .LBB3_2: 619; RV32IZFHMIN-NEXT: addi sp, sp, -16 620; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 621; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 622; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 623; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 624; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 625; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero 626; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 627; RV32IZFHMIN-NEXT: neg s0, a0 628; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 629; RV32IZFHMIN-NEXT: call __fixunssfdi 630; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI3_0) 631; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a2) 632; RV32IZFHMIN-NEXT: and a0, s0, a0 633; RV32IZFHMIN-NEXT: and a1, s0, a1 634; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 635; RV32IZFHMIN-NEXT: neg a2, a2 636; RV32IZFHMIN-NEXT: or a0, a2, a0 637; RV32IZFHMIN-NEXT: or a1, a2, a1 638; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 639; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 640; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 641; RV32IZFHMIN-NEXT: addi sp, sp, 16 642; RV32IZFHMIN-NEXT: ret 643; 644; RV64IZFHMIN-LABEL: test_floor_ui64: 645; RV64IZFHMIN: # %bb.0: 646; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 647; RV64IZFHMIN-NEXT: lui a0, 307200 648; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 649; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 650; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 651; RV64IZFHMIN-NEXT: beqz a0, .LBB3_2 652; RV64IZFHMIN-NEXT: # %bb.1: 653; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn 654; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn 655; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 656; RV64IZFHMIN-NEXT: .LBB3_2: 657; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 658; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 659; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 660; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 661; RV64IZFHMIN-NEXT: seqz a1, a1 662; RV64IZFHMIN-NEXT: addi a1, a1, -1 663; RV64IZFHMIN-NEXT: and a0, a1, a0 664; RV64IZFHMIN-NEXT: ret 665; 666; RV32IZHINXMIN-LABEL: test_floor_ui64: 667; RV32IZHINXMIN: # %bb.0: 668; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 669; RV32IZHINXMIN-NEXT: lui a1, 307200 670; RV32IZHINXMIN-NEXT: fabs.s a2, a0 671; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 672; RV32IZHINXMIN-NEXT: beqz a1, .LBB3_2 673; RV32IZHINXMIN-NEXT: # %bb.1: 674; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 675; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 676; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 677; RV32IZHINXMIN-NEXT: .LBB3_2: 678; RV32IZHINXMIN-NEXT: addi sp, sp, -16 679; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 680; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 681; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 682; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 683; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 684; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 685; RV32IZHINXMIN-NEXT: neg s1, a0 686; RV32IZHINXMIN-NEXT: mv a0, s0 687; RV32IZHINXMIN-NEXT: call __fixunssfdi 688; RV32IZHINXMIN-NEXT: and a0, s1, a0 689; RV32IZHINXMIN-NEXT: lui a2, 391168 690; RV32IZHINXMIN-NEXT: and a1, s1, a1 691; RV32IZHINXMIN-NEXT: addi a2, a2, -1 692; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 693; RV32IZHINXMIN-NEXT: neg a2, a2 694; RV32IZHINXMIN-NEXT: or a0, a2, a0 695; RV32IZHINXMIN-NEXT: or a1, a2, a1 696; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 697; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 698; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 699; RV32IZHINXMIN-NEXT: addi sp, sp, 16 700; RV32IZHINXMIN-NEXT: ret 701; 702; RV64IZHINXMIN-LABEL: test_floor_ui64: 703; RV64IZHINXMIN: # %bb.0: 704; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 705; RV64IZHINXMIN-NEXT: lui a1, 307200 706; RV64IZHINXMIN-NEXT: fabs.s a2, a0 707; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 708; RV64IZHINXMIN-NEXT: beqz a1, .LBB3_2 709; RV64IZHINXMIN-NEXT: # %bb.1: 710; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn 711; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn 712; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 713; RV64IZHINXMIN-NEXT: .LBB3_2: 714; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 715; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 716; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz 717; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 718; RV64IZHINXMIN-NEXT: seqz a0, a0 719; RV64IZHINXMIN-NEXT: addi a0, a0, -1 720; RV64IZHINXMIN-NEXT: and a0, a0, a1 721; RV64IZHINXMIN-NEXT: ret 722 %a = call half @llvm.floor.f16(half %x) 723 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a) 724 ret i64 %b 725} 726 727define signext i32 @test_ceil_si32(half %x) { 728; CHECKIZFH-LABEL: test_ceil_si32: 729; CHECKIZFH: # %bb.0: 730; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup 731; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 732; CHECKIZFH-NEXT: seqz a1, a1 733; CHECKIZFH-NEXT: addi a1, a1, -1 734; CHECKIZFH-NEXT: and a0, a1, a0 735; CHECKIZFH-NEXT: ret 736; 737; CHECKIZHINX-LABEL: test_ceil_si32: 738; CHECKIZHINX: # %bb.0: 739; CHECKIZHINX-NEXT: li a1, 25 740; CHECKIZHINX-NEXT: slli a1, a1, 10 741; CHECKIZHINX-NEXT: fabs.h a2, a0 742; CHECKIZHINX-NEXT: flt.h a1, a2, a1 743; CHECKIZHINX-NEXT: beqz a1, .LBB4_2 744; CHECKIZHINX-NEXT: # %bb.1: 745; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup 746; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup 747; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0 748; CHECKIZHINX-NEXT: .LBB4_2: 749; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 750; CHECKIZHINX-NEXT: feq.h a0, a0, a0 751; CHECKIZHINX-NEXT: seqz a0, a0 752; CHECKIZHINX-NEXT: addi a0, a0, -1 753; CHECKIZHINX-NEXT: and a0, a0, a1 754; CHECKIZHINX-NEXT: ret 755; 756; CHECKIZFHMIN-LABEL: test_ceil_si32: 757; CHECKIZFHMIN: # %bb.0: 758; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 759; CHECKIZFHMIN-NEXT: lui a0, 307200 760; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0 761; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5 762; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4 763; CHECKIZFHMIN-NEXT: beqz a0, .LBB4_2 764; CHECKIZFHMIN-NEXT: # %bb.1: 765; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 766; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 767; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 768; CHECKIZFHMIN-NEXT: .LBB4_2: 769; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5 770; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 771; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 772; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 773; CHECKIZFHMIN-NEXT: seqz a1, a1 774; CHECKIZFHMIN-NEXT: addi a1, a1, -1 775; CHECKIZFHMIN-NEXT: and a0, a1, a0 776; CHECKIZFHMIN-NEXT: ret 777; 778; CHECKIZHINXMIN-LABEL: test_ceil_si32: 779; CHECKIZHINXMIN: # %bb.0: 780; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 781; CHECKIZHINXMIN-NEXT: lui a1, 307200 782; CHECKIZHINXMIN-NEXT: fabs.s a2, a0 783; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1 784; CHECKIZHINXMIN-NEXT: beqz a1, .LBB4_2 785; CHECKIZHINXMIN-NEXT: # %bb.1: 786; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 787; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 788; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0 789; CHECKIZHINXMIN-NEXT: .LBB4_2: 790; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 791; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 792; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 793; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 794; CHECKIZHINXMIN-NEXT: seqz a0, a0 795; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 796; CHECKIZHINXMIN-NEXT: and a0, a0, a1 797; CHECKIZHINXMIN-NEXT: ret 798 %a = call half @llvm.ceil.f16(half %x) 799 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a) 800 ret i32 %b 801} 802 803define i64 @test_ceil_si64(half %x) nounwind { 804; RV32IZFH-LABEL: test_ceil_si64: 805; RV32IZFH: # %bb.0: 806; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_0) 807; RV32IZFH-NEXT: flh fa5, %lo(.LCPI5_0)(a0) 808; RV32IZFH-NEXT: fabs.h fa4, fa0 809; RV32IZFH-NEXT: flt.h a0, fa4, fa5 810; RV32IZFH-NEXT: beqz a0, .LBB5_2 811; RV32IZFH-NEXT: # %bb.1: 812; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup 813; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup 814; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 815; RV32IZFH-NEXT: .LBB5_2: 816; RV32IZFH-NEXT: addi sp, sp, -16 817; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 818; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 819; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 820; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 821; RV32IZFH-NEXT: lui a0, 913408 822; RV32IZFH-NEXT: fmv.w.x fa5, a0 823; RV32IZFH-NEXT: fle.s s0, fa5, fs0 824; RV32IZFH-NEXT: fmv.s fa0, fs0 825; RV32IZFH-NEXT: call __fixsfdi 826; RV32IZFH-NEXT: lui a3, 524288 827; RV32IZFH-NEXT: lui a2, 524288 828; RV32IZFH-NEXT: beqz s0, .LBB5_4 829; RV32IZFH-NEXT: # %bb.3: 830; RV32IZFH-NEXT: mv a2, a1 831; RV32IZFH-NEXT: .LBB5_4: 832; RV32IZFH-NEXT: lui a1, %hi(.LCPI5_1) 833; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a1) 834; RV32IZFH-NEXT: flt.s a1, fa5, fs0 835; RV32IZFH-NEXT: beqz a1, .LBB5_6 836; RV32IZFH-NEXT: # %bb.5: 837; RV32IZFH-NEXT: addi a2, a3, -1 838; RV32IZFH-NEXT: .LBB5_6: 839; RV32IZFH-NEXT: feq.s a3, fs0, fs0 840; RV32IZFH-NEXT: neg a4, s0 841; RV32IZFH-NEXT: neg a5, a1 842; RV32IZFH-NEXT: neg a3, a3 843; RV32IZFH-NEXT: and a0, a4, a0 844; RV32IZFH-NEXT: and a1, a3, a2 845; RV32IZFH-NEXT: or a0, a5, a0 846; RV32IZFH-NEXT: and a0, a3, a0 847; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 848; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 849; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 850; RV32IZFH-NEXT: addi sp, sp, 16 851; RV32IZFH-NEXT: ret 852; 853; RV64IZFH-LABEL: test_ceil_si64: 854; RV64IZFH: # %bb.0: 855; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup 856; RV64IZFH-NEXT: feq.h a1, fa0, fa0 857; RV64IZFH-NEXT: seqz a1, a1 858; RV64IZFH-NEXT: addi a1, a1, -1 859; RV64IZFH-NEXT: and a0, a1, a0 860; RV64IZFH-NEXT: ret 861; 862; RV32IZHINX-LABEL: test_ceil_si64: 863; RV32IZHINX: # %bb.0: 864; RV32IZHINX-NEXT: li a1, 25 865; RV32IZHINX-NEXT: slli a1, a1, 10 866; RV32IZHINX-NEXT: fabs.h a2, a0 867; RV32IZHINX-NEXT: flt.h a1, a2, a1 868; RV32IZHINX-NEXT: beqz a1, .LBB5_2 869; RV32IZHINX-NEXT: # %bb.1: 870; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup 871; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup 872; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 873; RV32IZHINX-NEXT: .LBB5_2: 874; RV32IZHINX-NEXT: addi sp, sp, -16 875; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 876; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 877; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 878; RV32IZHINX-NEXT: fcvt.s.h s0, a0 879; RV32IZHINX-NEXT: lui a0, 913408 880; RV32IZHINX-NEXT: fle.s s1, a0, s0 881; RV32IZHINX-NEXT: mv a0, s0 882; RV32IZHINX-NEXT: call __fixsfdi 883; RV32IZHINX-NEXT: lui a3, 524288 884; RV32IZHINX-NEXT: lui a2, 524288 885; RV32IZHINX-NEXT: beqz s1, .LBB5_4 886; RV32IZHINX-NEXT: # %bb.3: 887; RV32IZHINX-NEXT: mv a2, a1 888; RV32IZHINX-NEXT: .LBB5_4: 889; RV32IZHINX-NEXT: lui a1, 389120 890; RV32IZHINX-NEXT: addi a1, a1, -1 891; RV32IZHINX-NEXT: flt.s a1, a1, s0 892; RV32IZHINX-NEXT: beqz a1, .LBB5_6 893; RV32IZHINX-NEXT: # %bb.5: 894; RV32IZHINX-NEXT: addi a2, a3, -1 895; RV32IZHINX-NEXT: .LBB5_6: 896; RV32IZHINX-NEXT: feq.s a3, s0, s0 897; RV32IZHINX-NEXT: neg a4, s1 898; RV32IZHINX-NEXT: neg a5, a1 899; RV32IZHINX-NEXT: neg a3, a3 900; RV32IZHINX-NEXT: and a0, a4, a0 901; RV32IZHINX-NEXT: and a1, a3, a2 902; RV32IZHINX-NEXT: or a0, a5, a0 903; RV32IZHINX-NEXT: and a0, a3, a0 904; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 905; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 906; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 907; RV32IZHINX-NEXT: addi sp, sp, 16 908; RV32IZHINX-NEXT: ret 909; 910; RV64IZHINX-LABEL: test_ceil_si64: 911; RV64IZHINX: # %bb.0: 912; RV64IZHINX-NEXT: li a1, 25 913; RV64IZHINX-NEXT: slli a1, a1, 10 914; RV64IZHINX-NEXT: fabs.h a2, a0 915; RV64IZHINX-NEXT: flt.h a1, a2, a1 916; RV64IZHINX-NEXT: beqz a1, .LBB5_2 917; RV64IZHINX-NEXT: # %bb.1: 918; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup 919; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup 920; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 921; RV64IZHINX-NEXT: .LBB5_2: 922; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz 923; RV64IZHINX-NEXT: feq.h a0, a0, a0 924; RV64IZHINX-NEXT: seqz a0, a0 925; RV64IZHINX-NEXT: addi a0, a0, -1 926; RV64IZHINX-NEXT: and a0, a0, a1 927; RV64IZHINX-NEXT: ret 928; 929; RV32IZFHMIN-LABEL: test_ceil_si64: 930; RV32IZFHMIN: # %bb.0: 931; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 932; RV32IZFHMIN-NEXT: lui a0, 307200 933; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 934; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 935; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 936; RV32IZFHMIN-NEXT: beqz a0, .LBB5_2 937; RV32IZFHMIN-NEXT: # %bb.1: 938; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 939; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 940; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 941; RV32IZFHMIN-NEXT: .LBB5_2: 942; RV32IZFHMIN-NEXT: addi sp, sp, -16 943; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 944; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 945; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 946; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 947; RV32IZFHMIN-NEXT: lui a0, 913408 948; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 949; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 950; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 951; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 952; RV32IZFHMIN-NEXT: call __fixsfdi 953; RV32IZFHMIN-NEXT: lui a3, 524288 954; RV32IZFHMIN-NEXT: lui a2, 524288 955; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4 956; RV32IZFHMIN-NEXT: # %bb.3: 957; RV32IZFHMIN-NEXT: mv a2, a1 958; RV32IZFHMIN-NEXT: .LBB5_4: 959; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI5_0) 960; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a1) 961; RV32IZFHMIN-NEXT: flt.s a1, fa5, fs0 962; RV32IZFHMIN-NEXT: beqz a1, .LBB5_6 963; RV32IZFHMIN-NEXT: # %bb.5: 964; RV32IZFHMIN-NEXT: addi a2, a3, -1 965; RV32IZFHMIN-NEXT: .LBB5_6: 966; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 967; RV32IZFHMIN-NEXT: neg a4, s0 968; RV32IZFHMIN-NEXT: neg a5, a1 969; RV32IZFHMIN-NEXT: neg a3, a3 970; RV32IZFHMIN-NEXT: and a0, a4, a0 971; RV32IZFHMIN-NEXT: and a1, a3, a2 972; RV32IZFHMIN-NEXT: or a0, a5, a0 973; RV32IZFHMIN-NEXT: and a0, a3, a0 974; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 975; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 976; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 977; RV32IZFHMIN-NEXT: addi sp, sp, 16 978; RV32IZFHMIN-NEXT: ret 979; 980; RV64IZFHMIN-LABEL: test_ceil_si64: 981; RV64IZFHMIN: # %bb.0: 982; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 983; RV64IZFHMIN-NEXT: lui a0, 307200 984; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 985; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 986; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 987; RV64IZFHMIN-NEXT: beqz a0, .LBB5_2 988; RV64IZFHMIN-NEXT: # %bb.1: 989; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 990; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 991; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 992; RV64IZFHMIN-NEXT: .LBB5_2: 993; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 994; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 995; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz 996; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 997; RV64IZFHMIN-NEXT: seqz a1, a1 998; RV64IZFHMIN-NEXT: addi a1, a1, -1 999; RV64IZFHMIN-NEXT: and a0, a1, a0 1000; RV64IZFHMIN-NEXT: ret 1001; 1002; RV32IZHINXMIN-LABEL: test_ceil_si64: 1003; RV32IZHINXMIN: # %bb.0: 1004; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1005; RV32IZHINXMIN-NEXT: lui a1, 307200 1006; RV32IZHINXMIN-NEXT: fabs.s a2, a0 1007; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 1008; RV32IZHINXMIN-NEXT: beqz a1, .LBB5_2 1009; RV32IZHINXMIN-NEXT: # %bb.1: 1010; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 1011; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 1012; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1013; RV32IZHINXMIN-NEXT: .LBB5_2: 1014; RV32IZHINXMIN-NEXT: addi sp, sp, -16 1015; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1016; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1017; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1018; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 1019; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 1020; RV32IZHINXMIN-NEXT: lui a0, 913408 1021; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 1022; RV32IZHINXMIN-NEXT: mv a0, s0 1023; RV32IZHINXMIN-NEXT: call __fixsfdi 1024; RV32IZHINXMIN-NEXT: lui a3, 524288 1025; RV32IZHINXMIN-NEXT: lui a2, 524288 1026; RV32IZHINXMIN-NEXT: beqz s1, .LBB5_4 1027; RV32IZHINXMIN-NEXT: # %bb.3: 1028; RV32IZHINXMIN-NEXT: mv a2, a1 1029; RV32IZHINXMIN-NEXT: .LBB5_4: 1030; RV32IZHINXMIN-NEXT: lui a1, 389120 1031; RV32IZHINXMIN-NEXT: addi a1, a1, -1 1032; RV32IZHINXMIN-NEXT: flt.s a1, a1, s0 1033; RV32IZHINXMIN-NEXT: beqz a1, .LBB5_6 1034; RV32IZHINXMIN-NEXT: # %bb.5: 1035; RV32IZHINXMIN-NEXT: addi a2, a3, -1 1036; RV32IZHINXMIN-NEXT: .LBB5_6: 1037; RV32IZHINXMIN-NEXT: feq.s a3, s0, s0 1038; RV32IZHINXMIN-NEXT: neg a4, s1 1039; RV32IZHINXMIN-NEXT: neg a5, a1 1040; RV32IZHINXMIN-NEXT: neg a3, a3 1041; RV32IZHINXMIN-NEXT: and a0, a4, a0 1042; RV32IZHINXMIN-NEXT: and a1, a3, a2 1043; RV32IZHINXMIN-NEXT: or a0, a5, a0 1044; RV32IZHINXMIN-NEXT: and a0, a3, a0 1045; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1046; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1047; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1048; RV32IZHINXMIN-NEXT: addi sp, sp, 16 1049; RV32IZHINXMIN-NEXT: ret 1050; 1051; RV64IZHINXMIN-LABEL: test_ceil_si64: 1052; RV64IZHINXMIN: # %bb.0: 1053; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1054; RV64IZHINXMIN-NEXT: lui a1, 307200 1055; RV64IZHINXMIN-NEXT: fabs.s a2, a0 1056; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 1057; RV64IZHINXMIN-NEXT: beqz a1, .LBB5_2 1058; RV64IZHINXMIN-NEXT: # %bb.1: 1059; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 1060; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 1061; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1062; RV64IZHINXMIN-NEXT: .LBB5_2: 1063; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 1064; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1065; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz 1066; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 1067; RV64IZHINXMIN-NEXT: seqz a0, a0 1068; RV64IZHINXMIN-NEXT: addi a0, a0, -1 1069; RV64IZHINXMIN-NEXT: and a0, a0, a1 1070; RV64IZHINXMIN-NEXT: ret 1071 %a = call half @llvm.ceil.f16(half %x) 1072 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a) 1073 ret i64 %b 1074} 1075 1076define signext i32 @test_ceil_ui32(half %x) { 1077; CHECKIZFH-LABEL: test_ceil_ui32: 1078; CHECKIZFH: # %bb.0: 1079; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rup 1080; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 1081; CHECKIZFH-NEXT: seqz a1, a1 1082; CHECKIZFH-NEXT: addi a1, a1, -1 1083; CHECKIZFH-NEXT: and a0, a1, a0 1084; CHECKIZFH-NEXT: ret 1085; 1086; RV32IZHINX-LABEL: test_ceil_ui32: 1087; RV32IZHINX: # %bb.0: 1088; RV32IZHINX-NEXT: li a1, 25 1089; RV32IZHINX-NEXT: slli a1, a1, 10 1090; RV32IZHINX-NEXT: fabs.h a2, a0 1091; RV32IZHINX-NEXT: flt.h a1, a2, a1 1092; RV32IZHINX-NEXT: beqz a1, .LBB6_2 1093; RV32IZHINX-NEXT: # %bb.1: 1094; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup 1095; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup 1096; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 1097; RV32IZHINX-NEXT: .LBB6_2: 1098; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 1099; RV32IZHINX-NEXT: feq.h a0, a0, a0 1100; RV32IZHINX-NEXT: seqz a0, a0 1101; RV32IZHINX-NEXT: addi a0, a0, -1 1102; RV32IZHINX-NEXT: and a0, a0, a1 1103; RV32IZHINX-NEXT: ret 1104; 1105; RV64IZHINX-LABEL: test_ceil_ui32: 1106; RV64IZHINX: # %bb.0: 1107; RV64IZHINX-NEXT: li a1, 25 1108; RV64IZHINX-NEXT: slli a1, a1, 10 1109; RV64IZHINX-NEXT: fabs.h a2, a0 1110; RV64IZHINX-NEXT: flt.h a1, a2, a1 1111; RV64IZHINX-NEXT: beqz a1, .LBB6_2 1112; RV64IZHINX-NEXT: # %bb.1: 1113; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup 1114; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup 1115; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 1116; RV64IZHINX-NEXT: .LBB6_2: 1117; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 1118; RV64IZHINX-NEXT: feq.h a0, a0, a0 1119; RV64IZHINX-NEXT: seqz a0, a0 1120; RV64IZHINX-NEXT: addiw a0, a0, -1 1121; RV64IZHINX-NEXT: and a0, a1, a0 1122; RV64IZHINX-NEXT: ret 1123; 1124; RV32IZFHMIN-LABEL: test_ceil_ui32: 1125; RV32IZFHMIN: # %bb.0: 1126; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1127; RV32IZFHMIN-NEXT: lui a0, 307200 1128; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 1129; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 1130; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 1131; RV32IZFHMIN-NEXT: beqz a0, .LBB6_2 1132; RV32IZFHMIN-NEXT: # %bb.1: 1133; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 1134; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 1135; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1136; RV32IZFHMIN-NEXT: .LBB6_2: 1137; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1138; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 1139; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 1140; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5 1141; RV32IZFHMIN-NEXT: seqz a1, a1 1142; RV32IZFHMIN-NEXT: addi a1, a1, -1 1143; RV32IZFHMIN-NEXT: and a0, a1, a0 1144; RV32IZFHMIN-NEXT: ret 1145; 1146; RV64IZFHMIN-LABEL: test_ceil_ui32: 1147; RV64IZFHMIN: # %bb.0: 1148; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1149; RV64IZFHMIN-NEXT: lui a0, 307200 1150; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 1151; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 1152; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 1153; RV64IZFHMIN-NEXT: beqz a0, .LBB6_2 1154; RV64IZFHMIN-NEXT: # %bb.1: 1155; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 1156; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 1157; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1158; RV64IZFHMIN-NEXT: .LBB6_2: 1159; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1160; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 1161; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 1162; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 1163; RV64IZFHMIN-NEXT: seqz a1, a1 1164; RV64IZFHMIN-NEXT: addiw a1, a1, -1 1165; RV64IZFHMIN-NEXT: and a0, a0, a1 1166; RV64IZFHMIN-NEXT: ret 1167; 1168; RV32IZHINXMIN-LABEL: test_ceil_ui32: 1169; RV32IZHINXMIN: # %bb.0: 1170; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1171; RV32IZHINXMIN-NEXT: lui a1, 307200 1172; RV32IZHINXMIN-NEXT: fabs.s a2, a0 1173; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 1174; RV32IZHINXMIN-NEXT: beqz a1, .LBB6_2 1175; RV32IZHINXMIN-NEXT: # %bb.1: 1176; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 1177; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 1178; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1179; RV32IZHINXMIN-NEXT: .LBB6_2: 1180; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 1181; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1182; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 1183; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0 1184; RV32IZHINXMIN-NEXT: seqz a0, a0 1185; RV32IZHINXMIN-NEXT: addi a0, a0, -1 1186; RV32IZHINXMIN-NEXT: and a0, a0, a1 1187; RV32IZHINXMIN-NEXT: ret 1188; 1189; RV64IZHINXMIN-LABEL: test_ceil_ui32: 1190; RV64IZHINXMIN: # %bb.0: 1191; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1192; RV64IZHINXMIN-NEXT: lui a1, 307200 1193; RV64IZHINXMIN-NEXT: fabs.s a2, a0 1194; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 1195; RV64IZHINXMIN-NEXT: beqz a1, .LBB6_2 1196; RV64IZHINXMIN-NEXT: # %bb.1: 1197; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 1198; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 1199; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1200; RV64IZHINXMIN-NEXT: .LBB6_2: 1201; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 1202; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1203; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 1204; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 1205; RV64IZHINXMIN-NEXT: seqz a0, a0 1206; RV64IZHINXMIN-NEXT: addiw a0, a0, -1 1207; RV64IZHINXMIN-NEXT: and a0, a1, a0 1208; RV64IZHINXMIN-NEXT: ret 1209 %a = call half @llvm.ceil.f16(half %x) 1210 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a) 1211 ret i32 %b 1212} 1213 1214define i64 @test_ceil_ui64(half %x) nounwind { 1215; RV32IZFH-LABEL: test_ceil_ui64: 1216; RV32IZFH: # %bb.0: 1217; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0) 1218; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) 1219; RV32IZFH-NEXT: fabs.h fa4, fa0 1220; RV32IZFH-NEXT: flt.h a0, fa4, fa5 1221; RV32IZFH-NEXT: beqz a0, .LBB7_2 1222; RV32IZFH-NEXT: # %bb.1: 1223; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup 1224; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup 1225; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 1226; RV32IZFH-NEXT: .LBB7_2: 1227; RV32IZFH-NEXT: addi sp, sp, -16 1228; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1229; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1230; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 1231; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 1232; RV32IZFH-NEXT: fmv.w.x fa5, zero 1233; RV32IZFH-NEXT: fle.s a0, fa5, fs0 1234; RV32IZFH-NEXT: neg s0, a0 1235; RV32IZFH-NEXT: fmv.s fa0, fs0 1236; RV32IZFH-NEXT: call __fixunssfdi 1237; RV32IZFH-NEXT: lui a2, %hi(.LCPI7_1) 1238; RV32IZFH-NEXT: flw fa5, %lo(.LCPI7_1)(a2) 1239; RV32IZFH-NEXT: and a0, s0, a0 1240; RV32IZFH-NEXT: and a1, s0, a1 1241; RV32IZFH-NEXT: flt.s a2, fa5, fs0 1242; RV32IZFH-NEXT: neg a2, a2 1243; RV32IZFH-NEXT: or a0, a2, a0 1244; RV32IZFH-NEXT: or a1, a2, a1 1245; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1246; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1247; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 1248; RV32IZFH-NEXT: addi sp, sp, 16 1249; RV32IZFH-NEXT: ret 1250; 1251; RV64IZFH-LABEL: test_ceil_ui64: 1252; RV64IZFH: # %bb.0: 1253; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup 1254; RV64IZFH-NEXT: feq.h a1, fa0, fa0 1255; RV64IZFH-NEXT: seqz a1, a1 1256; RV64IZFH-NEXT: addi a1, a1, -1 1257; RV64IZFH-NEXT: and a0, a1, a0 1258; RV64IZFH-NEXT: ret 1259; 1260; RV32IZHINX-LABEL: test_ceil_ui64: 1261; RV32IZHINX: # %bb.0: 1262; RV32IZHINX-NEXT: li a1, 25 1263; RV32IZHINX-NEXT: slli a1, a1, 10 1264; RV32IZHINX-NEXT: fabs.h a2, a0 1265; RV32IZHINX-NEXT: flt.h a1, a2, a1 1266; RV32IZHINX-NEXT: beqz a1, .LBB7_2 1267; RV32IZHINX-NEXT: # %bb.1: 1268; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup 1269; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup 1270; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 1271; RV32IZHINX-NEXT: .LBB7_2: 1272; RV32IZHINX-NEXT: addi sp, sp, -16 1273; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1274; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1275; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1276; RV32IZHINX-NEXT: fcvt.s.h s0, a0 1277; RV32IZHINX-NEXT: fle.s a0, zero, s0 1278; RV32IZHINX-NEXT: neg s1, a0 1279; RV32IZHINX-NEXT: mv a0, s0 1280; RV32IZHINX-NEXT: call __fixunssfdi 1281; RV32IZHINX-NEXT: and a0, s1, a0 1282; RV32IZHINX-NEXT: lui a2, 391168 1283; RV32IZHINX-NEXT: and a1, s1, a1 1284; RV32IZHINX-NEXT: addi a2, a2, -1 1285; RV32IZHINX-NEXT: flt.s a2, a2, s0 1286; RV32IZHINX-NEXT: neg a2, a2 1287; RV32IZHINX-NEXT: or a0, a2, a0 1288; RV32IZHINX-NEXT: or a1, a2, a1 1289; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1290; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1291; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1292; RV32IZHINX-NEXT: addi sp, sp, 16 1293; RV32IZHINX-NEXT: ret 1294; 1295; RV64IZHINX-LABEL: test_ceil_ui64: 1296; RV64IZHINX: # %bb.0: 1297; RV64IZHINX-NEXT: li a1, 25 1298; RV64IZHINX-NEXT: slli a1, a1, 10 1299; RV64IZHINX-NEXT: fabs.h a2, a0 1300; RV64IZHINX-NEXT: flt.h a1, a2, a1 1301; RV64IZHINX-NEXT: beqz a1, .LBB7_2 1302; RV64IZHINX-NEXT: # %bb.1: 1303; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup 1304; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup 1305; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 1306; RV64IZHINX-NEXT: .LBB7_2: 1307; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz 1308; RV64IZHINX-NEXT: feq.h a0, a0, a0 1309; RV64IZHINX-NEXT: seqz a0, a0 1310; RV64IZHINX-NEXT: addi a0, a0, -1 1311; RV64IZHINX-NEXT: and a0, a0, a1 1312; RV64IZHINX-NEXT: ret 1313; 1314; RV32IZFHMIN-LABEL: test_ceil_ui64: 1315; RV32IZFHMIN: # %bb.0: 1316; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1317; RV32IZFHMIN-NEXT: lui a0, 307200 1318; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 1319; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 1320; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 1321; RV32IZFHMIN-NEXT: beqz a0, .LBB7_2 1322; RV32IZFHMIN-NEXT: # %bb.1: 1323; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 1324; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 1325; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1326; RV32IZFHMIN-NEXT: .LBB7_2: 1327; RV32IZFHMIN-NEXT: addi sp, sp, -16 1328; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1329; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1330; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 1331; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1332; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 1333; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero 1334; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 1335; RV32IZFHMIN-NEXT: neg s0, a0 1336; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 1337; RV32IZFHMIN-NEXT: call __fixunssfdi 1338; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI7_0) 1339; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI7_0)(a2) 1340; RV32IZFHMIN-NEXT: and a0, s0, a0 1341; RV32IZFHMIN-NEXT: and a1, s0, a1 1342; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 1343; RV32IZFHMIN-NEXT: neg a2, a2 1344; RV32IZFHMIN-NEXT: or a0, a2, a0 1345; RV32IZFHMIN-NEXT: or a1, a2, a1 1346; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1347; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1348; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 1349; RV32IZFHMIN-NEXT: addi sp, sp, 16 1350; RV32IZFHMIN-NEXT: ret 1351; 1352; RV64IZFHMIN-LABEL: test_ceil_ui64: 1353; RV64IZFHMIN: # %bb.0: 1354; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1355; RV64IZFHMIN-NEXT: lui a0, 307200 1356; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 1357; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 1358; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 1359; RV64IZFHMIN-NEXT: beqz a0, .LBB7_2 1360; RV64IZFHMIN-NEXT: # %bb.1: 1361; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup 1362; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup 1363; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1364; RV64IZFHMIN-NEXT: .LBB7_2: 1365; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1366; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 1367; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 1368; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 1369; RV64IZFHMIN-NEXT: seqz a1, a1 1370; RV64IZFHMIN-NEXT: addi a1, a1, -1 1371; RV64IZFHMIN-NEXT: and a0, a1, a0 1372; RV64IZFHMIN-NEXT: ret 1373; 1374; RV32IZHINXMIN-LABEL: test_ceil_ui64: 1375; RV32IZHINXMIN: # %bb.0: 1376; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1377; RV32IZHINXMIN-NEXT: lui a1, 307200 1378; RV32IZHINXMIN-NEXT: fabs.s a2, a0 1379; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 1380; RV32IZHINXMIN-NEXT: beqz a1, .LBB7_2 1381; RV32IZHINXMIN-NEXT: # %bb.1: 1382; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 1383; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 1384; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1385; RV32IZHINXMIN-NEXT: .LBB7_2: 1386; RV32IZHINXMIN-NEXT: addi sp, sp, -16 1387; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1388; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1389; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1390; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 1391; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 1392; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 1393; RV32IZHINXMIN-NEXT: neg s1, a0 1394; RV32IZHINXMIN-NEXT: mv a0, s0 1395; RV32IZHINXMIN-NEXT: call __fixunssfdi 1396; RV32IZHINXMIN-NEXT: and a0, s1, a0 1397; RV32IZHINXMIN-NEXT: lui a2, 391168 1398; RV32IZHINXMIN-NEXT: and a1, s1, a1 1399; RV32IZHINXMIN-NEXT: addi a2, a2, -1 1400; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 1401; RV32IZHINXMIN-NEXT: neg a2, a2 1402; RV32IZHINXMIN-NEXT: or a0, a2, a0 1403; RV32IZHINXMIN-NEXT: or a1, a2, a1 1404; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1405; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1406; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1407; RV32IZHINXMIN-NEXT: addi sp, sp, 16 1408; RV32IZHINXMIN-NEXT: ret 1409; 1410; RV64IZHINXMIN-LABEL: test_ceil_ui64: 1411; RV64IZHINXMIN: # %bb.0: 1412; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1413; RV64IZHINXMIN-NEXT: lui a1, 307200 1414; RV64IZHINXMIN-NEXT: fabs.s a2, a0 1415; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 1416; RV64IZHINXMIN-NEXT: beqz a1, .LBB7_2 1417; RV64IZHINXMIN-NEXT: # %bb.1: 1418; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup 1419; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup 1420; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1421; RV64IZHINXMIN-NEXT: .LBB7_2: 1422; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 1423; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1424; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz 1425; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 1426; RV64IZHINXMIN-NEXT: seqz a0, a0 1427; RV64IZHINXMIN-NEXT: addi a0, a0, -1 1428; RV64IZHINXMIN-NEXT: and a0, a0, a1 1429; RV64IZHINXMIN-NEXT: ret 1430 %a = call half @llvm.ceil.f16(half %x) 1431 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a) 1432 ret i64 %b 1433} 1434 1435define signext i32 @test_trunc_si32(half %x) { 1436; CHECKIZFH-LABEL: test_trunc_si32: 1437; CHECKIZFH: # %bb.0: 1438; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz 1439; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 1440; CHECKIZFH-NEXT: seqz a1, a1 1441; CHECKIZFH-NEXT: addi a1, a1, -1 1442; CHECKIZFH-NEXT: and a0, a1, a0 1443; CHECKIZFH-NEXT: ret 1444; 1445; CHECKIZHINX-LABEL: test_trunc_si32: 1446; CHECKIZHINX: # %bb.0: 1447; CHECKIZHINX-NEXT: li a1, 25 1448; CHECKIZHINX-NEXT: slli a1, a1, 10 1449; CHECKIZHINX-NEXT: fabs.h a2, a0 1450; CHECKIZHINX-NEXT: flt.h a1, a2, a1 1451; CHECKIZHINX-NEXT: beqz a1, .LBB8_2 1452; CHECKIZHINX-NEXT: # %bb.1: 1453; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 1454; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz 1455; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0 1456; CHECKIZHINX-NEXT: .LBB8_2: 1457; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 1458; CHECKIZHINX-NEXT: feq.h a0, a0, a0 1459; CHECKIZHINX-NEXT: seqz a0, a0 1460; CHECKIZHINX-NEXT: addi a0, a0, -1 1461; CHECKIZHINX-NEXT: and a0, a0, a1 1462; CHECKIZHINX-NEXT: ret 1463; 1464; CHECKIZFHMIN-LABEL: test_trunc_si32: 1465; CHECKIZFHMIN: # %bb.0: 1466; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 1467; CHECKIZFHMIN-NEXT: lui a0, 307200 1468; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0 1469; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5 1470; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4 1471; CHECKIZFHMIN-NEXT: beqz a0, .LBB8_2 1472; CHECKIZFHMIN-NEXT: # %bb.1: 1473; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 1474; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 1475; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1476; CHECKIZFHMIN-NEXT: .LBB8_2: 1477; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5 1478; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 1479; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 1480; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 1481; CHECKIZFHMIN-NEXT: seqz a1, a1 1482; CHECKIZFHMIN-NEXT: addi a1, a1, -1 1483; CHECKIZFHMIN-NEXT: and a0, a1, a0 1484; CHECKIZFHMIN-NEXT: ret 1485; 1486; CHECKIZHINXMIN-LABEL: test_trunc_si32: 1487; CHECKIZHINXMIN: # %bb.0: 1488; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 1489; CHECKIZHINXMIN-NEXT: lui a1, 307200 1490; CHECKIZHINXMIN-NEXT: fabs.s a2, a0 1491; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1 1492; CHECKIZHINXMIN-NEXT: beqz a1, .LBB8_2 1493; CHECKIZHINXMIN-NEXT: # %bb.1: 1494; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 1495; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 1496; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1497; CHECKIZHINXMIN-NEXT: .LBB8_2: 1498; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 1499; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 1500; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 1501; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 1502; CHECKIZHINXMIN-NEXT: seqz a0, a0 1503; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 1504; CHECKIZHINXMIN-NEXT: and a0, a0, a1 1505; CHECKIZHINXMIN-NEXT: ret 1506 %a = call half @llvm.trunc.f16(half %x) 1507 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a) 1508 ret i32 %b 1509} 1510 1511define i64 @test_trunc_si64(half %x) nounwind { 1512; RV32IZFH-LABEL: test_trunc_si64: 1513; RV32IZFH: # %bb.0: 1514; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_0) 1515; RV32IZFH-NEXT: flh fa5, %lo(.LCPI9_0)(a0) 1516; RV32IZFH-NEXT: fabs.h fa4, fa0 1517; RV32IZFH-NEXT: flt.h a0, fa4, fa5 1518; RV32IZFH-NEXT: beqz a0, .LBB9_2 1519; RV32IZFH-NEXT: # %bb.1: 1520; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz 1521; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz 1522; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 1523; RV32IZFH-NEXT: .LBB9_2: 1524; RV32IZFH-NEXT: addi sp, sp, -16 1525; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1526; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1527; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 1528; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 1529; RV32IZFH-NEXT: lui a0, 913408 1530; RV32IZFH-NEXT: fmv.w.x fa5, a0 1531; RV32IZFH-NEXT: fle.s s0, fa5, fs0 1532; RV32IZFH-NEXT: fmv.s fa0, fs0 1533; RV32IZFH-NEXT: call __fixsfdi 1534; RV32IZFH-NEXT: lui a3, 524288 1535; RV32IZFH-NEXT: lui a2, 524288 1536; RV32IZFH-NEXT: beqz s0, .LBB9_4 1537; RV32IZFH-NEXT: # %bb.3: 1538; RV32IZFH-NEXT: mv a2, a1 1539; RV32IZFH-NEXT: .LBB9_4: 1540; RV32IZFH-NEXT: lui a1, %hi(.LCPI9_1) 1541; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a1) 1542; RV32IZFH-NEXT: flt.s a1, fa5, fs0 1543; RV32IZFH-NEXT: beqz a1, .LBB9_6 1544; RV32IZFH-NEXT: # %bb.5: 1545; RV32IZFH-NEXT: addi a2, a3, -1 1546; RV32IZFH-NEXT: .LBB9_6: 1547; RV32IZFH-NEXT: feq.s a3, fs0, fs0 1548; RV32IZFH-NEXT: neg a4, s0 1549; RV32IZFH-NEXT: neg a5, a1 1550; RV32IZFH-NEXT: neg a3, a3 1551; RV32IZFH-NEXT: and a0, a4, a0 1552; RV32IZFH-NEXT: and a1, a3, a2 1553; RV32IZFH-NEXT: or a0, a5, a0 1554; RV32IZFH-NEXT: and a0, a3, a0 1555; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1556; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1557; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 1558; RV32IZFH-NEXT: addi sp, sp, 16 1559; RV32IZFH-NEXT: ret 1560; 1561; RV64IZFH-LABEL: test_trunc_si64: 1562; RV64IZFH: # %bb.0: 1563; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 1564; RV64IZFH-NEXT: feq.h a1, fa0, fa0 1565; RV64IZFH-NEXT: seqz a1, a1 1566; RV64IZFH-NEXT: addi a1, a1, -1 1567; RV64IZFH-NEXT: and a0, a1, a0 1568; RV64IZFH-NEXT: ret 1569; 1570; RV32IZHINX-LABEL: test_trunc_si64: 1571; RV32IZHINX: # %bb.0: 1572; RV32IZHINX-NEXT: li a1, 25 1573; RV32IZHINX-NEXT: slli a1, a1, 10 1574; RV32IZHINX-NEXT: fabs.h a2, a0 1575; RV32IZHINX-NEXT: flt.h a1, a2, a1 1576; RV32IZHINX-NEXT: beqz a1, .LBB9_2 1577; RV32IZHINX-NEXT: # %bb.1: 1578; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz 1579; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz 1580; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 1581; RV32IZHINX-NEXT: .LBB9_2: 1582; RV32IZHINX-NEXT: addi sp, sp, -16 1583; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1584; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1585; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1586; RV32IZHINX-NEXT: fcvt.s.h s0, a0 1587; RV32IZHINX-NEXT: lui a0, 913408 1588; RV32IZHINX-NEXT: fle.s s1, a0, s0 1589; RV32IZHINX-NEXT: mv a0, s0 1590; RV32IZHINX-NEXT: call __fixsfdi 1591; RV32IZHINX-NEXT: lui a3, 524288 1592; RV32IZHINX-NEXT: lui a2, 524288 1593; RV32IZHINX-NEXT: beqz s1, .LBB9_4 1594; RV32IZHINX-NEXT: # %bb.3: 1595; RV32IZHINX-NEXT: mv a2, a1 1596; RV32IZHINX-NEXT: .LBB9_4: 1597; RV32IZHINX-NEXT: lui a1, 389120 1598; RV32IZHINX-NEXT: addi a1, a1, -1 1599; RV32IZHINX-NEXT: flt.s a1, a1, s0 1600; RV32IZHINX-NEXT: beqz a1, .LBB9_6 1601; RV32IZHINX-NEXT: # %bb.5: 1602; RV32IZHINX-NEXT: addi a2, a3, -1 1603; RV32IZHINX-NEXT: .LBB9_6: 1604; RV32IZHINX-NEXT: feq.s a3, s0, s0 1605; RV32IZHINX-NEXT: neg a4, s1 1606; RV32IZHINX-NEXT: neg a5, a1 1607; RV32IZHINX-NEXT: neg a3, a3 1608; RV32IZHINX-NEXT: and a0, a4, a0 1609; RV32IZHINX-NEXT: and a1, a3, a2 1610; RV32IZHINX-NEXT: or a0, a5, a0 1611; RV32IZHINX-NEXT: and a0, a3, a0 1612; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1613; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1614; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1615; RV32IZHINX-NEXT: addi sp, sp, 16 1616; RV32IZHINX-NEXT: ret 1617; 1618; RV64IZHINX-LABEL: test_trunc_si64: 1619; RV64IZHINX: # %bb.0: 1620; RV64IZHINX-NEXT: li a1, 25 1621; RV64IZHINX-NEXT: slli a1, a1, 10 1622; RV64IZHINX-NEXT: fabs.h a2, a0 1623; RV64IZHINX-NEXT: flt.h a1, a2, a1 1624; RV64IZHINX-NEXT: beqz a1, .LBB9_2 1625; RV64IZHINX-NEXT: # %bb.1: 1626; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz 1627; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz 1628; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 1629; RV64IZHINX-NEXT: .LBB9_2: 1630; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz 1631; RV64IZHINX-NEXT: feq.h a0, a0, a0 1632; RV64IZHINX-NEXT: seqz a0, a0 1633; RV64IZHINX-NEXT: addi a0, a0, -1 1634; RV64IZHINX-NEXT: and a0, a0, a1 1635; RV64IZHINX-NEXT: ret 1636; 1637; RV32IZFHMIN-LABEL: test_trunc_si64: 1638; RV32IZFHMIN: # %bb.0: 1639; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1640; RV32IZFHMIN-NEXT: lui a0, 307200 1641; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 1642; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 1643; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 1644; RV32IZFHMIN-NEXT: beqz a0, .LBB9_2 1645; RV32IZFHMIN-NEXT: # %bb.1: 1646; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 1647; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 1648; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1649; RV32IZFHMIN-NEXT: .LBB9_2: 1650; RV32IZFHMIN-NEXT: addi sp, sp, -16 1651; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1652; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1653; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 1654; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1655; RV32IZFHMIN-NEXT: lui a0, 913408 1656; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 1657; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 1658; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 1659; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 1660; RV32IZFHMIN-NEXT: call __fixsfdi 1661; RV32IZFHMIN-NEXT: lui a3, 524288 1662; RV32IZFHMIN-NEXT: lui a2, 524288 1663; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4 1664; RV32IZFHMIN-NEXT: # %bb.3: 1665; RV32IZFHMIN-NEXT: mv a2, a1 1666; RV32IZFHMIN-NEXT: .LBB9_4: 1667; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI9_0) 1668; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a1) 1669; RV32IZFHMIN-NEXT: flt.s a1, fa5, fs0 1670; RV32IZFHMIN-NEXT: beqz a1, .LBB9_6 1671; RV32IZFHMIN-NEXT: # %bb.5: 1672; RV32IZFHMIN-NEXT: addi a2, a3, -1 1673; RV32IZFHMIN-NEXT: .LBB9_6: 1674; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 1675; RV32IZFHMIN-NEXT: neg a4, s0 1676; RV32IZFHMIN-NEXT: neg a5, a1 1677; RV32IZFHMIN-NEXT: neg a3, a3 1678; RV32IZFHMIN-NEXT: and a0, a4, a0 1679; RV32IZFHMIN-NEXT: and a1, a3, a2 1680; RV32IZFHMIN-NEXT: or a0, a5, a0 1681; RV32IZFHMIN-NEXT: and a0, a3, a0 1682; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1683; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1684; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 1685; RV32IZFHMIN-NEXT: addi sp, sp, 16 1686; RV32IZFHMIN-NEXT: ret 1687; 1688; RV64IZFHMIN-LABEL: test_trunc_si64: 1689; RV64IZFHMIN: # %bb.0: 1690; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1691; RV64IZFHMIN-NEXT: lui a0, 307200 1692; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 1693; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 1694; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 1695; RV64IZFHMIN-NEXT: beqz a0, .LBB9_2 1696; RV64IZFHMIN-NEXT: # %bb.1: 1697; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 1698; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 1699; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1700; RV64IZFHMIN-NEXT: .LBB9_2: 1701; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1702; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 1703; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz 1704; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 1705; RV64IZFHMIN-NEXT: seqz a1, a1 1706; RV64IZFHMIN-NEXT: addi a1, a1, -1 1707; RV64IZFHMIN-NEXT: and a0, a1, a0 1708; RV64IZFHMIN-NEXT: ret 1709; 1710; RV32IZHINXMIN-LABEL: test_trunc_si64: 1711; RV32IZHINXMIN: # %bb.0: 1712; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1713; RV32IZHINXMIN-NEXT: lui a1, 307200 1714; RV32IZHINXMIN-NEXT: fabs.s a2, a0 1715; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 1716; RV32IZHINXMIN-NEXT: beqz a1, .LBB9_2 1717; RV32IZHINXMIN-NEXT: # %bb.1: 1718; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 1719; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 1720; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1721; RV32IZHINXMIN-NEXT: .LBB9_2: 1722; RV32IZHINXMIN-NEXT: addi sp, sp, -16 1723; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1724; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1725; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1726; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 1727; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 1728; RV32IZHINXMIN-NEXT: lui a0, 913408 1729; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 1730; RV32IZHINXMIN-NEXT: mv a0, s0 1731; RV32IZHINXMIN-NEXT: call __fixsfdi 1732; RV32IZHINXMIN-NEXT: lui a3, 524288 1733; RV32IZHINXMIN-NEXT: lui a2, 524288 1734; RV32IZHINXMIN-NEXT: beqz s1, .LBB9_4 1735; RV32IZHINXMIN-NEXT: # %bb.3: 1736; RV32IZHINXMIN-NEXT: mv a2, a1 1737; RV32IZHINXMIN-NEXT: .LBB9_4: 1738; RV32IZHINXMIN-NEXT: lui a1, 389120 1739; RV32IZHINXMIN-NEXT: addi a1, a1, -1 1740; RV32IZHINXMIN-NEXT: flt.s a1, a1, s0 1741; RV32IZHINXMIN-NEXT: beqz a1, .LBB9_6 1742; RV32IZHINXMIN-NEXT: # %bb.5: 1743; RV32IZHINXMIN-NEXT: addi a2, a3, -1 1744; RV32IZHINXMIN-NEXT: .LBB9_6: 1745; RV32IZHINXMIN-NEXT: feq.s a3, s0, s0 1746; RV32IZHINXMIN-NEXT: neg a4, s1 1747; RV32IZHINXMIN-NEXT: neg a5, a1 1748; RV32IZHINXMIN-NEXT: neg a3, a3 1749; RV32IZHINXMIN-NEXT: and a0, a4, a0 1750; RV32IZHINXMIN-NEXT: and a1, a3, a2 1751; RV32IZHINXMIN-NEXT: or a0, a5, a0 1752; RV32IZHINXMIN-NEXT: and a0, a3, a0 1753; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1754; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1755; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1756; RV32IZHINXMIN-NEXT: addi sp, sp, 16 1757; RV32IZHINXMIN-NEXT: ret 1758; 1759; RV64IZHINXMIN-LABEL: test_trunc_si64: 1760; RV64IZHINXMIN: # %bb.0: 1761; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1762; RV64IZHINXMIN-NEXT: lui a1, 307200 1763; RV64IZHINXMIN-NEXT: fabs.s a2, a0 1764; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 1765; RV64IZHINXMIN-NEXT: beqz a1, .LBB9_2 1766; RV64IZHINXMIN-NEXT: # %bb.1: 1767; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 1768; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 1769; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1770; RV64IZHINXMIN-NEXT: .LBB9_2: 1771; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 1772; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1773; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz 1774; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 1775; RV64IZHINXMIN-NEXT: seqz a0, a0 1776; RV64IZHINXMIN-NEXT: addi a0, a0, -1 1777; RV64IZHINXMIN-NEXT: and a0, a0, a1 1778; RV64IZHINXMIN-NEXT: ret 1779 %a = call half @llvm.trunc.f16(half %x) 1780 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a) 1781 ret i64 %b 1782} 1783 1784define signext i32 @test_trunc_ui32(half %x) { 1785; CHECKIZFH-LABEL: test_trunc_ui32: 1786; CHECKIZFH: # %bb.0: 1787; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz 1788; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 1789; CHECKIZFH-NEXT: seqz a1, a1 1790; CHECKIZFH-NEXT: addi a1, a1, -1 1791; CHECKIZFH-NEXT: and a0, a1, a0 1792; CHECKIZFH-NEXT: ret 1793; 1794; RV32IZHINX-LABEL: test_trunc_ui32: 1795; RV32IZHINX: # %bb.0: 1796; RV32IZHINX-NEXT: li a1, 25 1797; RV32IZHINX-NEXT: slli a1, a1, 10 1798; RV32IZHINX-NEXT: fabs.h a2, a0 1799; RV32IZHINX-NEXT: flt.h a1, a2, a1 1800; RV32IZHINX-NEXT: beqz a1, .LBB10_2 1801; RV32IZHINX-NEXT: # %bb.1: 1802; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz 1803; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz 1804; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 1805; RV32IZHINX-NEXT: .LBB10_2: 1806; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 1807; RV32IZHINX-NEXT: feq.h a0, a0, a0 1808; RV32IZHINX-NEXT: seqz a0, a0 1809; RV32IZHINX-NEXT: addi a0, a0, -1 1810; RV32IZHINX-NEXT: and a0, a0, a1 1811; RV32IZHINX-NEXT: ret 1812; 1813; RV64IZHINX-LABEL: test_trunc_ui32: 1814; RV64IZHINX: # %bb.0: 1815; RV64IZHINX-NEXT: li a1, 25 1816; RV64IZHINX-NEXT: slli a1, a1, 10 1817; RV64IZHINX-NEXT: fabs.h a2, a0 1818; RV64IZHINX-NEXT: flt.h a1, a2, a1 1819; RV64IZHINX-NEXT: beqz a1, .LBB10_2 1820; RV64IZHINX-NEXT: # %bb.1: 1821; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz 1822; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz 1823; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 1824; RV64IZHINX-NEXT: .LBB10_2: 1825; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 1826; RV64IZHINX-NEXT: feq.h a0, a0, a0 1827; RV64IZHINX-NEXT: seqz a0, a0 1828; RV64IZHINX-NEXT: addiw a0, a0, -1 1829; RV64IZHINX-NEXT: and a0, a1, a0 1830; RV64IZHINX-NEXT: ret 1831; 1832; RV32IZFHMIN-LABEL: test_trunc_ui32: 1833; RV32IZFHMIN: # %bb.0: 1834; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1835; RV32IZFHMIN-NEXT: lui a0, 307200 1836; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 1837; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 1838; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 1839; RV32IZFHMIN-NEXT: beqz a0, .LBB10_2 1840; RV32IZFHMIN-NEXT: # %bb.1: 1841; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 1842; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 1843; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1844; RV32IZFHMIN-NEXT: .LBB10_2: 1845; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1846; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 1847; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 1848; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5 1849; RV32IZFHMIN-NEXT: seqz a1, a1 1850; RV32IZFHMIN-NEXT: addi a1, a1, -1 1851; RV32IZFHMIN-NEXT: and a0, a1, a0 1852; RV32IZFHMIN-NEXT: ret 1853; 1854; RV64IZFHMIN-LABEL: test_trunc_ui32: 1855; RV64IZFHMIN: # %bb.0: 1856; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 1857; RV64IZFHMIN-NEXT: lui a0, 307200 1858; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 1859; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 1860; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 1861; RV64IZFHMIN-NEXT: beqz a0, .LBB10_2 1862; RV64IZFHMIN-NEXT: # %bb.1: 1863; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 1864; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 1865; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 1866; RV64IZFHMIN-NEXT: .LBB10_2: 1867; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 1868; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 1869; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 1870; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 1871; RV64IZFHMIN-NEXT: seqz a1, a1 1872; RV64IZFHMIN-NEXT: addiw a1, a1, -1 1873; RV64IZFHMIN-NEXT: and a0, a0, a1 1874; RV64IZFHMIN-NEXT: ret 1875; 1876; RV32IZHINXMIN-LABEL: test_trunc_ui32: 1877; RV32IZHINXMIN: # %bb.0: 1878; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1879; RV32IZHINXMIN-NEXT: lui a1, 307200 1880; RV32IZHINXMIN-NEXT: fabs.s a2, a0 1881; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 1882; RV32IZHINXMIN-NEXT: beqz a1, .LBB10_2 1883; RV32IZHINXMIN-NEXT: # %bb.1: 1884; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 1885; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 1886; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1887; RV32IZHINXMIN-NEXT: .LBB10_2: 1888; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 1889; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 1890; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 1891; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0 1892; RV32IZHINXMIN-NEXT: seqz a0, a0 1893; RV32IZHINXMIN-NEXT: addi a0, a0, -1 1894; RV32IZHINXMIN-NEXT: and a0, a0, a1 1895; RV32IZHINXMIN-NEXT: ret 1896; 1897; RV64IZHINXMIN-LABEL: test_trunc_ui32: 1898; RV64IZHINXMIN: # %bb.0: 1899; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1900; RV64IZHINXMIN-NEXT: lui a1, 307200 1901; RV64IZHINXMIN-NEXT: fabs.s a2, a0 1902; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 1903; RV64IZHINXMIN-NEXT: beqz a1, .LBB10_2 1904; RV64IZHINXMIN-NEXT: # %bb.1: 1905; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 1906; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 1907; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 1908; RV64IZHINXMIN-NEXT: .LBB10_2: 1909; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 1910; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 1911; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 1912; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 1913; RV64IZHINXMIN-NEXT: seqz a0, a0 1914; RV64IZHINXMIN-NEXT: addiw a0, a0, -1 1915; RV64IZHINXMIN-NEXT: and a0, a1, a0 1916; RV64IZHINXMIN-NEXT: ret 1917 %a = call half @llvm.trunc.f16(half %x) 1918 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a) 1919 ret i32 %b 1920} 1921 1922define i64 @test_trunc_ui64(half %x) nounwind { 1923; RV32IZFH-LABEL: test_trunc_ui64: 1924; RV32IZFH: # %bb.0: 1925; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0) 1926; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0) 1927; RV32IZFH-NEXT: fabs.h fa4, fa0 1928; RV32IZFH-NEXT: flt.h a0, fa4, fa5 1929; RV32IZFH-NEXT: beqz a0, .LBB11_2 1930; RV32IZFH-NEXT: # %bb.1: 1931; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz 1932; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz 1933; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 1934; RV32IZFH-NEXT: .LBB11_2: 1935; RV32IZFH-NEXT: addi sp, sp, -16 1936; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1937; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1938; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 1939; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 1940; RV32IZFH-NEXT: fmv.w.x fa5, zero 1941; RV32IZFH-NEXT: fle.s a0, fa5, fs0 1942; RV32IZFH-NEXT: neg s0, a0 1943; RV32IZFH-NEXT: fmv.s fa0, fs0 1944; RV32IZFH-NEXT: call __fixunssfdi 1945; RV32IZFH-NEXT: lui a2, %hi(.LCPI11_1) 1946; RV32IZFH-NEXT: flw fa5, %lo(.LCPI11_1)(a2) 1947; RV32IZFH-NEXT: and a0, s0, a0 1948; RV32IZFH-NEXT: and a1, s0, a1 1949; RV32IZFH-NEXT: flt.s a2, fa5, fs0 1950; RV32IZFH-NEXT: neg a2, a2 1951; RV32IZFH-NEXT: or a0, a2, a0 1952; RV32IZFH-NEXT: or a1, a2, a1 1953; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1954; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1955; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 1956; RV32IZFH-NEXT: addi sp, sp, 16 1957; RV32IZFH-NEXT: ret 1958; 1959; RV64IZFH-LABEL: test_trunc_ui64: 1960; RV64IZFH: # %bb.0: 1961; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz 1962; RV64IZFH-NEXT: feq.h a1, fa0, fa0 1963; RV64IZFH-NEXT: seqz a1, a1 1964; RV64IZFH-NEXT: addi a1, a1, -1 1965; RV64IZFH-NEXT: and a0, a1, a0 1966; RV64IZFH-NEXT: ret 1967; 1968; RV32IZHINX-LABEL: test_trunc_ui64: 1969; RV32IZHINX: # %bb.0: 1970; RV32IZHINX-NEXT: li a1, 25 1971; RV32IZHINX-NEXT: slli a1, a1, 10 1972; RV32IZHINX-NEXT: fabs.h a2, a0 1973; RV32IZHINX-NEXT: flt.h a1, a2, a1 1974; RV32IZHINX-NEXT: beqz a1, .LBB11_2 1975; RV32IZHINX-NEXT: # %bb.1: 1976; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz 1977; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz 1978; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 1979; RV32IZHINX-NEXT: .LBB11_2: 1980; RV32IZHINX-NEXT: addi sp, sp, -16 1981; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1982; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1983; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1984; RV32IZHINX-NEXT: fcvt.s.h s0, a0 1985; RV32IZHINX-NEXT: fle.s a0, zero, s0 1986; RV32IZHINX-NEXT: neg s1, a0 1987; RV32IZHINX-NEXT: mv a0, s0 1988; RV32IZHINX-NEXT: call __fixunssfdi 1989; RV32IZHINX-NEXT: and a0, s1, a0 1990; RV32IZHINX-NEXT: lui a2, 391168 1991; RV32IZHINX-NEXT: and a1, s1, a1 1992; RV32IZHINX-NEXT: addi a2, a2, -1 1993; RV32IZHINX-NEXT: flt.s a2, a2, s0 1994; RV32IZHINX-NEXT: neg a2, a2 1995; RV32IZHINX-NEXT: or a0, a2, a0 1996; RV32IZHINX-NEXT: or a1, a2, a1 1997; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1998; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1999; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2000; RV32IZHINX-NEXT: addi sp, sp, 16 2001; RV32IZHINX-NEXT: ret 2002; 2003; RV64IZHINX-LABEL: test_trunc_ui64: 2004; RV64IZHINX: # %bb.0: 2005; RV64IZHINX-NEXT: li a1, 25 2006; RV64IZHINX-NEXT: slli a1, a1, 10 2007; RV64IZHINX-NEXT: fabs.h a2, a0 2008; RV64IZHINX-NEXT: flt.h a1, a2, a1 2009; RV64IZHINX-NEXT: beqz a1, .LBB11_2 2010; RV64IZHINX-NEXT: # %bb.1: 2011; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz 2012; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz 2013; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 2014; RV64IZHINX-NEXT: .LBB11_2: 2015; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz 2016; RV64IZHINX-NEXT: feq.h a0, a0, a0 2017; RV64IZHINX-NEXT: seqz a0, a0 2018; RV64IZHINX-NEXT: addi a0, a0, -1 2019; RV64IZHINX-NEXT: and a0, a0, a1 2020; RV64IZHINX-NEXT: ret 2021; 2022; RV32IZFHMIN-LABEL: test_trunc_ui64: 2023; RV32IZFHMIN: # %bb.0: 2024; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2025; RV32IZFHMIN-NEXT: lui a0, 307200 2026; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 2027; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 2028; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 2029; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2 2030; RV32IZFHMIN-NEXT: # %bb.1: 2031; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 2032; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 2033; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2034; RV32IZFHMIN-NEXT: .LBB11_2: 2035; RV32IZFHMIN-NEXT: addi sp, sp, -16 2036; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2037; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2038; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 2039; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2040; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 2041; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero 2042; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 2043; RV32IZFHMIN-NEXT: neg s0, a0 2044; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 2045; RV32IZFHMIN-NEXT: call __fixunssfdi 2046; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI11_0) 2047; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI11_0)(a2) 2048; RV32IZFHMIN-NEXT: and a0, s0, a0 2049; RV32IZFHMIN-NEXT: and a1, s0, a1 2050; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 2051; RV32IZFHMIN-NEXT: neg a2, a2 2052; RV32IZFHMIN-NEXT: or a0, a2, a0 2053; RV32IZFHMIN-NEXT: or a1, a2, a1 2054; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2055; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2056; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 2057; RV32IZFHMIN-NEXT: addi sp, sp, 16 2058; RV32IZFHMIN-NEXT: ret 2059; 2060; RV64IZFHMIN-LABEL: test_trunc_ui64: 2061; RV64IZFHMIN: # %bb.0: 2062; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2063; RV64IZFHMIN-NEXT: lui a0, 307200 2064; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 2065; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 2066; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 2067; RV64IZFHMIN-NEXT: beqz a0, .LBB11_2 2068; RV64IZFHMIN-NEXT: # %bb.1: 2069; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 2070; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz 2071; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2072; RV64IZFHMIN-NEXT: .LBB11_2: 2073; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2074; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 2075; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 2076; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 2077; RV64IZFHMIN-NEXT: seqz a1, a1 2078; RV64IZFHMIN-NEXT: addi a1, a1, -1 2079; RV64IZFHMIN-NEXT: and a0, a1, a0 2080; RV64IZFHMIN-NEXT: ret 2081; 2082; RV32IZHINXMIN-LABEL: test_trunc_ui64: 2083; RV32IZHINXMIN: # %bb.0: 2084; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 2085; RV32IZHINXMIN-NEXT: lui a1, 307200 2086; RV32IZHINXMIN-NEXT: fabs.s a2, a0 2087; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 2088; RV32IZHINXMIN-NEXT: beqz a1, .LBB11_2 2089; RV32IZHINXMIN-NEXT: # %bb.1: 2090; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 2091; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 2092; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2093; RV32IZHINXMIN-NEXT: .LBB11_2: 2094; RV32IZHINXMIN-NEXT: addi sp, sp, -16 2095; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2096; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2097; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 2098; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 2099; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 2100; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 2101; RV32IZHINXMIN-NEXT: neg s1, a0 2102; RV32IZHINXMIN-NEXT: mv a0, s0 2103; RV32IZHINXMIN-NEXT: call __fixunssfdi 2104; RV32IZHINXMIN-NEXT: and a0, s1, a0 2105; RV32IZHINXMIN-NEXT: lui a2, 391168 2106; RV32IZHINXMIN-NEXT: and a1, s1, a1 2107; RV32IZHINXMIN-NEXT: addi a2, a2, -1 2108; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 2109; RV32IZHINXMIN-NEXT: neg a2, a2 2110; RV32IZHINXMIN-NEXT: or a0, a2, a0 2111; RV32IZHINXMIN-NEXT: or a1, a2, a1 2112; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2113; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2114; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2115; RV32IZHINXMIN-NEXT: addi sp, sp, 16 2116; RV32IZHINXMIN-NEXT: ret 2117; 2118; RV64IZHINXMIN-LABEL: test_trunc_ui64: 2119; RV64IZHINXMIN: # %bb.0: 2120; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2121; RV64IZHINXMIN-NEXT: lui a1, 307200 2122; RV64IZHINXMIN-NEXT: fabs.s a2, a0 2123; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 2124; RV64IZHINXMIN-NEXT: beqz a1, .LBB11_2 2125; RV64IZHINXMIN-NEXT: # %bb.1: 2126; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 2127; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz 2128; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2129; RV64IZHINXMIN-NEXT: .LBB11_2: 2130; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 2131; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2132; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz 2133; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 2134; RV64IZHINXMIN-NEXT: seqz a0, a0 2135; RV64IZHINXMIN-NEXT: addi a0, a0, -1 2136; RV64IZHINXMIN-NEXT: and a0, a0, a1 2137; RV64IZHINXMIN-NEXT: ret 2138 %a = call half @llvm.trunc.f16(half %x) 2139 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a) 2140 ret i64 %b 2141} 2142 2143define signext i32 @test_round_si32(half %x) { 2144; CHECKIZFH-LABEL: test_round_si32: 2145; CHECKIZFH: # %bb.0: 2146; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm 2147; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 2148; CHECKIZFH-NEXT: seqz a1, a1 2149; CHECKIZFH-NEXT: addi a1, a1, -1 2150; CHECKIZFH-NEXT: and a0, a1, a0 2151; CHECKIZFH-NEXT: ret 2152; 2153; CHECKIZHINX-LABEL: test_round_si32: 2154; CHECKIZHINX: # %bb.0: 2155; CHECKIZHINX-NEXT: li a1, 25 2156; CHECKIZHINX-NEXT: slli a1, a1, 10 2157; CHECKIZHINX-NEXT: fabs.h a2, a0 2158; CHECKIZHINX-NEXT: flt.h a1, a2, a1 2159; CHECKIZHINX-NEXT: beqz a1, .LBB12_2 2160; CHECKIZHINX-NEXT: # %bb.1: 2161; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm 2162; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm 2163; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0 2164; CHECKIZHINX-NEXT: .LBB12_2: 2165; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 2166; CHECKIZHINX-NEXT: feq.h a0, a0, a0 2167; CHECKIZHINX-NEXT: seqz a0, a0 2168; CHECKIZHINX-NEXT: addi a0, a0, -1 2169; CHECKIZHINX-NEXT: and a0, a0, a1 2170; CHECKIZHINX-NEXT: ret 2171; 2172; CHECKIZFHMIN-LABEL: test_round_si32: 2173; CHECKIZFHMIN: # %bb.0: 2174; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 2175; CHECKIZFHMIN-NEXT: lui a0, 307200 2176; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0 2177; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5 2178; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4 2179; CHECKIZFHMIN-NEXT: beqz a0, .LBB12_2 2180; CHECKIZFHMIN-NEXT: # %bb.1: 2181; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2182; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2183; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2184; CHECKIZFHMIN-NEXT: .LBB12_2: 2185; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5 2186; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 2187; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 2188; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 2189; CHECKIZFHMIN-NEXT: seqz a1, a1 2190; CHECKIZFHMIN-NEXT: addi a1, a1, -1 2191; CHECKIZFHMIN-NEXT: and a0, a1, a0 2192; CHECKIZFHMIN-NEXT: ret 2193; 2194; CHECKIZHINXMIN-LABEL: test_round_si32: 2195; CHECKIZHINXMIN: # %bb.0: 2196; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 2197; CHECKIZHINXMIN-NEXT: lui a1, 307200 2198; CHECKIZHINXMIN-NEXT: fabs.s a2, a0 2199; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1 2200; CHECKIZHINXMIN-NEXT: beqz a1, .LBB12_2 2201; CHECKIZHINXMIN-NEXT: # %bb.1: 2202; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2203; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2204; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2205; CHECKIZHINXMIN-NEXT: .LBB12_2: 2206; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 2207; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 2208; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 2209; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 2210; CHECKIZHINXMIN-NEXT: seqz a0, a0 2211; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 2212; CHECKIZHINXMIN-NEXT: and a0, a0, a1 2213; CHECKIZHINXMIN-NEXT: ret 2214 %a = call half @llvm.round.f16(half %x) 2215 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a) 2216 ret i32 %b 2217} 2218 2219define i64 @test_round_si64(half %x) nounwind { 2220; RV32IZFH-LABEL: test_round_si64: 2221; RV32IZFH: # %bb.0: 2222; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_0) 2223; RV32IZFH-NEXT: flh fa5, %lo(.LCPI13_0)(a0) 2224; RV32IZFH-NEXT: fabs.h fa4, fa0 2225; RV32IZFH-NEXT: flt.h a0, fa4, fa5 2226; RV32IZFH-NEXT: beqz a0, .LBB13_2 2227; RV32IZFH-NEXT: # %bb.1: 2228; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm 2229; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm 2230; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 2231; RV32IZFH-NEXT: .LBB13_2: 2232; RV32IZFH-NEXT: addi sp, sp, -16 2233; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2234; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2235; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 2236; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 2237; RV32IZFH-NEXT: lui a0, 913408 2238; RV32IZFH-NEXT: fmv.w.x fa5, a0 2239; RV32IZFH-NEXT: fle.s s0, fa5, fs0 2240; RV32IZFH-NEXT: fmv.s fa0, fs0 2241; RV32IZFH-NEXT: call __fixsfdi 2242; RV32IZFH-NEXT: lui a3, 524288 2243; RV32IZFH-NEXT: lui a2, 524288 2244; RV32IZFH-NEXT: beqz s0, .LBB13_4 2245; RV32IZFH-NEXT: # %bb.3: 2246; RV32IZFH-NEXT: mv a2, a1 2247; RV32IZFH-NEXT: .LBB13_4: 2248; RV32IZFH-NEXT: lui a1, %hi(.LCPI13_1) 2249; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a1) 2250; RV32IZFH-NEXT: flt.s a1, fa5, fs0 2251; RV32IZFH-NEXT: beqz a1, .LBB13_6 2252; RV32IZFH-NEXT: # %bb.5: 2253; RV32IZFH-NEXT: addi a2, a3, -1 2254; RV32IZFH-NEXT: .LBB13_6: 2255; RV32IZFH-NEXT: feq.s a3, fs0, fs0 2256; RV32IZFH-NEXT: neg a4, s0 2257; RV32IZFH-NEXT: neg a5, a1 2258; RV32IZFH-NEXT: neg a3, a3 2259; RV32IZFH-NEXT: and a0, a4, a0 2260; RV32IZFH-NEXT: and a1, a3, a2 2261; RV32IZFH-NEXT: or a0, a5, a0 2262; RV32IZFH-NEXT: and a0, a3, a0 2263; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2264; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2265; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 2266; RV32IZFH-NEXT: addi sp, sp, 16 2267; RV32IZFH-NEXT: ret 2268; 2269; RV64IZFH-LABEL: test_round_si64: 2270; RV64IZFH: # %bb.0: 2271; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm 2272; RV64IZFH-NEXT: feq.h a1, fa0, fa0 2273; RV64IZFH-NEXT: seqz a1, a1 2274; RV64IZFH-NEXT: addi a1, a1, -1 2275; RV64IZFH-NEXT: and a0, a1, a0 2276; RV64IZFH-NEXT: ret 2277; 2278; RV32IZHINX-LABEL: test_round_si64: 2279; RV32IZHINX: # %bb.0: 2280; RV32IZHINX-NEXT: li a1, 25 2281; RV32IZHINX-NEXT: slli a1, a1, 10 2282; RV32IZHINX-NEXT: fabs.h a2, a0 2283; RV32IZHINX-NEXT: flt.h a1, a2, a1 2284; RV32IZHINX-NEXT: beqz a1, .LBB13_2 2285; RV32IZHINX-NEXT: # %bb.1: 2286; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm 2287; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm 2288; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 2289; RV32IZHINX-NEXT: .LBB13_2: 2290; RV32IZHINX-NEXT: addi sp, sp, -16 2291; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2292; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2293; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 2294; RV32IZHINX-NEXT: fcvt.s.h s0, a0 2295; RV32IZHINX-NEXT: lui a0, 913408 2296; RV32IZHINX-NEXT: fle.s s1, a0, s0 2297; RV32IZHINX-NEXT: mv a0, s0 2298; RV32IZHINX-NEXT: call __fixsfdi 2299; RV32IZHINX-NEXT: lui a3, 524288 2300; RV32IZHINX-NEXT: lui a2, 524288 2301; RV32IZHINX-NEXT: beqz s1, .LBB13_4 2302; RV32IZHINX-NEXT: # %bb.3: 2303; RV32IZHINX-NEXT: mv a2, a1 2304; RV32IZHINX-NEXT: .LBB13_4: 2305; RV32IZHINX-NEXT: lui a1, 389120 2306; RV32IZHINX-NEXT: addi a1, a1, -1 2307; RV32IZHINX-NEXT: flt.s a1, a1, s0 2308; RV32IZHINX-NEXT: beqz a1, .LBB13_6 2309; RV32IZHINX-NEXT: # %bb.5: 2310; RV32IZHINX-NEXT: addi a2, a3, -1 2311; RV32IZHINX-NEXT: .LBB13_6: 2312; RV32IZHINX-NEXT: feq.s a3, s0, s0 2313; RV32IZHINX-NEXT: neg a4, s1 2314; RV32IZHINX-NEXT: neg a5, a1 2315; RV32IZHINX-NEXT: neg a3, a3 2316; RV32IZHINX-NEXT: and a0, a4, a0 2317; RV32IZHINX-NEXT: and a1, a3, a2 2318; RV32IZHINX-NEXT: or a0, a5, a0 2319; RV32IZHINX-NEXT: and a0, a3, a0 2320; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2321; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2322; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2323; RV32IZHINX-NEXT: addi sp, sp, 16 2324; RV32IZHINX-NEXT: ret 2325; 2326; RV64IZHINX-LABEL: test_round_si64: 2327; RV64IZHINX: # %bb.0: 2328; RV64IZHINX-NEXT: li a1, 25 2329; RV64IZHINX-NEXT: slli a1, a1, 10 2330; RV64IZHINX-NEXT: fabs.h a2, a0 2331; RV64IZHINX-NEXT: flt.h a1, a2, a1 2332; RV64IZHINX-NEXT: beqz a1, .LBB13_2 2333; RV64IZHINX-NEXT: # %bb.1: 2334; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm 2335; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm 2336; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 2337; RV64IZHINX-NEXT: .LBB13_2: 2338; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz 2339; RV64IZHINX-NEXT: feq.h a0, a0, a0 2340; RV64IZHINX-NEXT: seqz a0, a0 2341; RV64IZHINX-NEXT: addi a0, a0, -1 2342; RV64IZHINX-NEXT: and a0, a0, a1 2343; RV64IZHINX-NEXT: ret 2344; 2345; RV32IZFHMIN-LABEL: test_round_si64: 2346; RV32IZFHMIN: # %bb.0: 2347; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2348; RV32IZFHMIN-NEXT: lui a0, 307200 2349; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 2350; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 2351; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 2352; RV32IZFHMIN-NEXT: beqz a0, .LBB13_2 2353; RV32IZFHMIN-NEXT: # %bb.1: 2354; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2355; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2356; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2357; RV32IZFHMIN-NEXT: .LBB13_2: 2358; RV32IZFHMIN-NEXT: addi sp, sp, -16 2359; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2360; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2361; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 2362; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2363; RV32IZFHMIN-NEXT: lui a0, 913408 2364; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 2365; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 2366; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 2367; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 2368; RV32IZFHMIN-NEXT: call __fixsfdi 2369; RV32IZFHMIN-NEXT: lui a3, 524288 2370; RV32IZFHMIN-NEXT: lui a2, 524288 2371; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4 2372; RV32IZFHMIN-NEXT: # %bb.3: 2373; RV32IZFHMIN-NEXT: mv a2, a1 2374; RV32IZFHMIN-NEXT: .LBB13_4: 2375; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI13_0) 2376; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a1) 2377; RV32IZFHMIN-NEXT: flt.s a1, fa5, fs0 2378; RV32IZFHMIN-NEXT: beqz a1, .LBB13_6 2379; RV32IZFHMIN-NEXT: # %bb.5: 2380; RV32IZFHMIN-NEXT: addi a2, a3, -1 2381; RV32IZFHMIN-NEXT: .LBB13_6: 2382; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 2383; RV32IZFHMIN-NEXT: neg a4, s0 2384; RV32IZFHMIN-NEXT: neg a5, a1 2385; RV32IZFHMIN-NEXT: neg a3, a3 2386; RV32IZFHMIN-NEXT: and a0, a4, a0 2387; RV32IZFHMIN-NEXT: and a1, a3, a2 2388; RV32IZFHMIN-NEXT: or a0, a5, a0 2389; RV32IZFHMIN-NEXT: and a0, a3, a0 2390; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2391; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2392; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 2393; RV32IZFHMIN-NEXT: addi sp, sp, 16 2394; RV32IZFHMIN-NEXT: ret 2395; 2396; RV64IZFHMIN-LABEL: test_round_si64: 2397; RV64IZFHMIN: # %bb.0: 2398; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2399; RV64IZFHMIN-NEXT: lui a0, 307200 2400; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 2401; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 2402; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 2403; RV64IZFHMIN-NEXT: beqz a0, .LBB13_2 2404; RV64IZFHMIN-NEXT: # %bb.1: 2405; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2406; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2407; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2408; RV64IZFHMIN-NEXT: .LBB13_2: 2409; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2410; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 2411; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz 2412; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 2413; RV64IZFHMIN-NEXT: seqz a1, a1 2414; RV64IZFHMIN-NEXT: addi a1, a1, -1 2415; RV64IZFHMIN-NEXT: and a0, a1, a0 2416; RV64IZFHMIN-NEXT: ret 2417; 2418; RV32IZHINXMIN-LABEL: test_round_si64: 2419; RV32IZHINXMIN: # %bb.0: 2420; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 2421; RV32IZHINXMIN-NEXT: lui a1, 307200 2422; RV32IZHINXMIN-NEXT: fabs.s a2, a0 2423; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 2424; RV32IZHINXMIN-NEXT: beqz a1, .LBB13_2 2425; RV32IZHINXMIN-NEXT: # %bb.1: 2426; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2427; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2428; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2429; RV32IZHINXMIN-NEXT: .LBB13_2: 2430; RV32IZHINXMIN-NEXT: addi sp, sp, -16 2431; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2432; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2433; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 2434; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 2435; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 2436; RV32IZHINXMIN-NEXT: lui a0, 913408 2437; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 2438; RV32IZHINXMIN-NEXT: mv a0, s0 2439; RV32IZHINXMIN-NEXT: call __fixsfdi 2440; RV32IZHINXMIN-NEXT: lui a3, 524288 2441; RV32IZHINXMIN-NEXT: lui a2, 524288 2442; RV32IZHINXMIN-NEXT: beqz s1, .LBB13_4 2443; RV32IZHINXMIN-NEXT: # %bb.3: 2444; RV32IZHINXMIN-NEXT: mv a2, a1 2445; RV32IZHINXMIN-NEXT: .LBB13_4: 2446; RV32IZHINXMIN-NEXT: lui a1, 389120 2447; RV32IZHINXMIN-NEXT: addi a1, a1, -1 2448; RV32IZHINXMIN-NEXT: flt.s a1, a1, s0 2449; RV32IZHINXMIN-NEXT: beqz a1, .LBB13_6 2450; RV32IZHINXMIN-NEXT: # %bb.5: 2451; RV32IZHINXMIN-NEXT: addi a2, a3, -1 2452; RV32IZHINXMIN-NEXT: .LBB13_6: 2453; RV32IZHINXMIN-NEXT: feq.s a3, s0, s0 2454; RV32IZHINXMIN-NEXT: neg a4, s1 2455; RV32IZHINXMIN-NEXT: neg a5, a1 2456; RV32IZHINXMIN-NEXT: neg a3, a3 2457; RV32IZHINXMIN-NEXT: and a0, a4, a0 2458; RV32IZHINXMIN-NEXT: and a1, a3, a2 2459; RV32IZHINXMIN-NEXT: or a0, a5, a0 2460; RV32IZHINXMIN-NEXT: and a0, a3, a0 2461; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2462; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2463; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2464; RV32IZHINXMIN-NEXT: addi sp, sp, 16 2465; RV32IZHINXMIN-NEXT: ret 2466; 2467; RV64IZHINXMIN-LABEL: test_round_si64: 2468; RV64IZHINXMIN: # %bb.0: 2469; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2470; RV64IZHINXMIN-NEXT: lui a1, 307200 2471; RV64IZHINXMIN-NEXT: fabs.s a2, a0 2472; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 2473; RV64IZHINXMIN-NEXT: beqz a1, .LBB13_2 2474; RV64IZHINXMIN-NEXT: # %bb.1: 2475; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2476; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2477; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2478; RV64IZHINXMIN-NEXT: .LBB13_2: 2479; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 2480; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2481; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz 2482; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 2483; RV64IZHINXMIN-NEXT: seqz a0, a0 2484; RV64IZHINXMIN-NEXT: addi a0, a0, -1 2485; RV64IZHINXMIN-NEXT: and a0, a0, a1 2486; RV64IZHINXMIN-NEXT: ret 2487 %a = call half @llvm.round.f16(half %x) 2488 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a) 2489 ret i64 %b 2490} 2491 2492define signext i32 @test_round_ui32(half %x) { 2493; CHECKIZFH-LABEL: test_round_ui32: 2494; CHECKIZFH: # %bb.0: 2495; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rmm 2496; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 2497; CHECKIZFH-NEXT: seqz a1, a1 2498; CHECKIZFH-NEXT: addi a1, a1, -1 2499; CHECKIZFH-NEXT: and a0, a1, a0 2500; CHECKIZFH-NEXT: ret 2501; 2502; RV32IZHINX-LABEL: test_round_ui32: 2503; RV32IZHINX: # %bb.0: 2504; RV32IZHINX-NEXT: li a1, 25 2505; RV32IZHINX-NEXT: slli a1, a1, 10 2506; RV32IZHINX-NEXT: fabs.h a2, a0 2507; RV32IZHINX-NEXT: flt.h a1, a2, a1 2508; RV32IZHINX-NEXT: beqz a1, .LBB14_2 2509; RV32IZHINX-NEXT: # %bb.1: 2510; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm 2511; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm 2512; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 2513; RV32IZHINX-NEXT: .LBB14_2: 2514; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 2515; RV32IZHINX-NEXT: feq.h a0, a0, a0 2516; RV32IZHINX-NEXT: seqz a0, a0 2517; RV32IZHINX-NEXT: addi a0, a0, -1 2518; RV32IZHINX-NEXT: and a0, a0, a1 2519; RV32IZHINX-NEXT: ret 2520; 2521; RV64IZHINX-LABEL: test_round_ui32: 2522; RV64IZHINX: # %bb.0: 2523; RV64IZHINX-NEXT: li a1, 25 2524; RV64IZHINX-NEXT: slli a1, a1, 10 2525; RV64IZHINX-NEXT: fabs.h a2, a0 2526; RV64IZHINX-NEXT: flt.h a1, a2, a1 2527; RV64IZHINX-NEXT: beqz a1, .LBB14_2 2528; RV64IZHINX-NEXT: # %bb.1: 2529; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm 2530; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm 2531; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 2532; RV64IZHINX-NEXT: .LBB14_2: 2533; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 2534; RV64IZHINX-NEXT: feq.h a0, a0, a0 2535; RV64IZHINX-NEXT: seqz a0, a0 2536; RV64IZHINX-NEXT: addiw a0, a0, -1 2537; RV64IZHINX-NEXT: and a0, a1, a0 2538; RV64IZHINX-NEXT: ret 2539; 2540; RV32IZFHMIN-LABEL: test_round_ui32: 2541; RV32IZFHMIN: # %bb.0: 2542; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2543; RV32IZFHMIN-NEXT: lui a0, 307200 2544; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 2545; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 2546; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 2547; RV32IZFHMIN-NEXT: beqz a0, .LBB14_2 2548; RV32IZFHMIN-NEXT: # %bb.1: 2549; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2550; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2551; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2552; RV32IZFHMIN-NEXT: .LBB14_2: 2553; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2554; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 2555; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 2556; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5 2557; RV32IZFHMIN-NEXT: seqz a1, a1 2558; RV32IZFHMIN-NEXT: addi a1, a1, -1 2559; RV32IZFHMIN-NEXT: and a0, a1, a0 2560; RV32IZFHMIN-NEXT: ret 2561; 2562; RV64IZFHMIN-LABEL: test_round_ui32: 2563; RV64IZFHMIN: # %bb.0: 2564; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2565; RV64IZFHMIN-NEXT: lui a0, 307200 2566; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 2567; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 2568; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 2569; RV64IZFHMIN-NEXT: beqz a0, .LBB14_2 2570; RV64IZFHMIN-NEXT: # %bb.1: 2571; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2572; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2573; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2574; RV64IZFHMIN-NEXT: .LBB14_2: 2575; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2576; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 2577; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 2578; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 2579; RV64IZFHMIN-NEXT: seqz a1, a1 2580; RV64IZFHMIN-NEXT: addiw a1, a1, -1 2581; RV64IZFHMIN-NEXT: and a0, a0, a1 2582; RV64IZFHMIN-NEXT: ret 2583; 2584; RV32IZHINXMIN-LABEL: test_round_ui32: 2585; RV32IZHINXMIN: # %bb.0: 2586; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 2587; RV32IZHINXMIN-NEXT: lui a1, 307200 2588; RV32IZHINXMIN-NEXT: fabs.s a2, a0 2589; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 2590; RV32IZHINXMIN-NEXT: beqz a1, .LBB14_2 2591; RV32IZHINXMIN-NEXT: # %bb.1: 2592; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2593; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2594; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2595; RV32IZHINXMIN-NEXT: .LBB14_2: 2596; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 2597; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 2598; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 2599; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0 2600; RV32IZHINXMIN-NEXT: seqz a0, a0 2601; RV32IZHINXMIN-NEXT: addi a0, a0, -1 2602; RV32IZHINXMIN-NEXT: and a0, a0, a1 2603; RV32IZHINXMIN-NEXT: ret 2604; 2605; RV64IZHINXMIN-LABEL: test_round_ui32: 2606; RV64IZHINXMIN: # %bb.0: 2607; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2608; RV64IZHINXMIN-NEXT: lui a1, 307200 2609; RV64IZHINXMIN-NEXT: fabs.s a2, a0 2610; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 2611; RV64IZHINXMIN-NEXT: beqz a1, .LBB14_2 2612; RV64IZHINXMIN-NEXT: # %bb.1: 2613; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2614; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2615; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2616; RV64IZHINXMIN-NEXT: .LBB14_2: 2617; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 2618; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2619; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 2620; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 2621; RV64IZHINXMIN-NEXT: seqz a0, a0 2622; RV64IZHINXMIN-NEXT: addiw a0, a0, -1 2623; RV64IZHINXMIN-NEXT: and a0, a1, a0 2624; RV64IZHINXMIN-NEXT: ret 2625 %a = call half @llvm.round.f16(half %x) 2626 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a) 2627 ret i32 %b 2628} 2629 2630define i64 @test_round_ui64(half %x) nounwind { 2631; RV32IZFH-LABEL: test_round_ui64: 2632; RV32IZFH: # %bb.0: 2633; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0) 2634; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0) 2635; RV32IZFH-NEXT: fabs.h fa4, fa0 2636; RV32IZFH-NEXT: flt.h a0, fa4, fa5 2637; RV32IZFH-NEXT: beqz a0, .LBB15_2 2638; RV32IZFH-NEXT: # %bb.1: 2639; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm 2640; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm 2641; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 2642; RV32IZFH-NEXT: .LBB15_2: 2643; RV32IZFH-NEXT: addi sp, sp, -16 2644; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2645; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2646; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 2647; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 2648; RV32IZFH-NEXT: fmv.w.x fa5, zero 2649; RV32IZFH-NEXT: fle.s a0, fa5, fs0 2650; RV32IZFH-NEXT: neg s0, a0 2651; RV32IZFH-NEXT: fmv.s fa0, fs0 2652; RV32IZFH-NEXT: call __fixunssfdi 2653; RV32IZFH-NEXT: lui a2, %hi(.LCPI15_1) 2654; RV32IZFH-NEXT: flw fa5, %lo(.LCPI15_1)(a2) 2655; RV32IZFH-NEXT: and a0, s0, a0 2656; RV32IZFH-NEXT: and a1, s0, a1 2657; RV32IZFH-NEXT: flt.s a2, fa5, fs0 2658; RV32IZFH-NEXT: neg a2, a2 2659; RV32IZFH-NEXT: or a0, a2, a0 2660; RV32IZFH-NEXT: or a1, a2, a1 2661; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2662; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2663; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 2664; RV32IZFH-NEXT: addi sp, sp, 16 2665; RV32IZFH-NEXT: ret 2666; 2667; RV64IZFH-LABEL: test_round_ui64: 2668; RV64IZFH: # %bb.0: 2669; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm 2670; RV64IZFH-NEXT: feq.h a1, fa0, fa0 2671; RV64IZFH-NEXT: seqz a1, a1 2672; RV64IZFH-NEXT: addi a1, a1, -1 2673; RV64IZFH-NEXT: and a0, a1, a0 2674; RV64IZFH-NEXT: ret 2675; 2676; RV32IZHINX-LABEL: test_round_ui64: 2677; RV32IZHINX: # %bb.0: 2678; RV32IZHINX-NEXT: li a1, 25 2679; RV32IZHINX-NEXT: slli a1, a1, 10 2680; RV32IZHINX-NEXT: fabs.h a2, a0 2681; RV32IZHINX-NEXT: flt.h a1, a2, a1 2682; RV32IZHINX-NEXT: beqz a1, .LBB15_2 2683; RV32IZHINX-NEXT: # %bb.1: 2684; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm 2685; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm 2686; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 2687; RV32IZHINX-NEXT: .LBB15_2: 2688; RV32IZHINX-NEXT: addi sp, sp, -16 2689; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2690; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2691; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 2692; RV32IZHINX-NEXT: fcvt.s.h s0, a0 2693; RV32IZHINX-NEXT: fle.s a0, zero, s0 2694; RV32IZHINX-NEXT: neg s1, a0 2695; RV32IZHINX-NEXT: mv a0, s0 2696; RV32IZHINX-NEXT: call __fixunssfdi 2697; RV32IZHINX-NEXT: and a0, s1, a0 2698; RV32IZHINX-NEXT: lui a2, 391168 2699; RV32IZHINX-NEXT: and a1, s1, a1 2700; RV32IZHINX-NEXT: addi a2, a2, -1 2701; RV32IZHINX-NEXT: flt.s a2, a2, s0 2702; RV32IZHINX-NEXT: neg a2, a2 2703; RV32IZHINX-NEXT: or a0, a2, a0 2704; RV32IZHINX-NEXT: or a1, a2, a1 2705; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2706; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2707; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2708; RV32IZHINX-NEXT: addi sp, sp, 16 2709; RV32IZHINX-NEXT: ret 2710; 2711; RV64IZHINX-LABEL: test_round_ui64: 2712; RV64IZHINX: # %bb.0: 2713; RV64IZHINX-NEXT: li a1, 25 2714; RV64IZHINX-NEXT: slli a1, a1, 10 2715; RV64IZHINX-NEXT: fabs.h a2, a0 2716; RV64IZHINX-NEXT: flt.h a1, a2, a1 2717; RV64IZHINX-NEXT: beqz a1, .LBB15_2 2718; RV64IZHINX-NEXT: # %bb.1: 2719; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm 2720; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm 2721; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 2722; RV64IZHINX-NEXT: .LBB15_2: 2723; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz 2724; RV64IZHINX-NEXT: feq.h a0, a0, a0 2725; RV64IZHINX-NEXT: seqz a0, a0 2726; RV64IZHINX-NEXT: addi a0, a0, -1 2727; RV64IZHINX-NEXT: and a0, a0, a1 2728; RV64IZHINX-NEXT: ret 2729; 2730; RV32IZFHMIN-LABEL: test_round_ui64: 2731; RV32IZFHMIN: # %bb.0: 2732; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2733; RV32IZFHMIN-NEXT: lui a0, 307200 2734; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 2735; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 2736; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 2737; RV32IZFHMIN-NEXT: beqz a0, .LBB15_2 2738; RV32IZFHMIN-NEXT: # %bb.1: 2739; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2740; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2741; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2742; RV32IZFHMIN-NEXT: .LBB15_2: 2743; RV32IZFHMIN-NEXT: addi sp, sp, -16 2744; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2745; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2746; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 2747; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2748; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 2749; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero 2750; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 2751; RV32IZFHMIN-NEXT: neg s0, a0 2752; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 2753; RV32IZFHMIN-NEXT: call __fixunssfdi 2754; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI15_0) 2755; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI15_0)(a2) 2756; RV32IZFHMIN-NEXT: and a0, s0, a0 2757; RV32IZFHMIN-NEXT: and a1, s0, a1 2758; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 2759; RV32IZFHMIN-NEXT: neg a2, a2 2760; RV32IZFHMIN-NEXT: or a0, a2, a0 2761; RV32IZFHMIN-NEXT: or a1, a2, a1 2762; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2763; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2764; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 2765; RV32IZFHMIN-NEXT: addi sp, sp, 16 2766; RV32IZFHMIN-NEXT: ret 2767; 2768; RV64IZFHMIN-LABEL: test_round_ui64: 2769; RV64IZFHMIN: # %bb.0: 2770; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 2771; RV64IZFHMIN-NEXT: lui a0, 307200 2772; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 2773; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 2774; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 2775; RV64IZFHMIN-NEXT: beqz a0, .LBB15_2 2776; RV64IZFHMIN-NEXT: # %bb.1: 2777; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 2778; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm 2779; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2780; RV64IZFHMIN-NEXT: .LBB15_2: 2781; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 2782; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 2783; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 2784; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 2785; RV64IZFHMIN-NEXT: seqz a1, a1 2786; RV64IZFHMIN-NEXT: addi a1, a1, -1 2787; RV64IZFHMIN-NEXT: and a0, a1, a0 2788; RV64IZFHMIN-NEXT: ret 2789; 2790; RV32IZHINXMIN-LABEL: test_round_ui64: 2791; RV32IZHINXMIN: # %bb.0: 2792; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 2793; RV32IZHINXMIN-NEXT: lui a1, 307200 2794; RV32IZHINXMIN-NEXT: fabs.s a2, a0 2795; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 2796; RV32IZHINXMIN-NEXT: beqz a1, .LBB15_2 2797; RV32IZHINXMIN-NEXT: # %bb.1: 2798; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2799; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2800; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2801; RV32IZHINXMIN-NEXT: .LBB15_2: 2802; RV32IZHINXMIN-NEXT: addi sp, sp, -16 2803; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2804; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2805; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 2806; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 2807; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 2808; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 2809; RV32IZHINXMIN-NEXT: neg s1, a0 2810; RV32IZHINXMIN-NEXT: mv a0, s0 2811; RV32IZHINXMIN-NEXT: call __fixunssfdi 2812; RV32IZHINXMIN-NEXT: and a0, s1, a0 2813; RV32IZHINXMIN-NEXT: lui a2, 391168 2814; RV32IZHINXMIN-NEXT: and a1, s1, a1 2815; RV32IZHINXMIN-NEXT: addi a2, a2, -1 2816; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 2817; RV32IZHINXMIN-NEXT: neg a2, a2 2818; RV32IZHINXMIN-NEXT: or a0, a2, a0 2819; RV32IZHINXMIN-NEXT: or a1, a2, a1 2820; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2821; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2822; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2823; RV32IZHINXMIN-NEXT: addi sp, sp, 16 2824; RV32IZHINXMIN-NEXT: ret 2825; 2826; RV64IZHINXMIN-LABEL: test_round_ui64: 2827; RV64IZHINXMIN: # %bb.0: 2828; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2829; RV64IZHINXMIN-NEXT: lui a1, 307200 2830; RV64IZHINXMIN-NEXT: fabs.s a2, a0 2831; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 2832; RV64IZHINXMIN-NEXT: beqz a1, .LBB15_2 2833; RV64IZHINXMIN-NEXT: # %bb.1: 2834; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm 2835; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm 2836; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2837; RV64IZHINXMIN-NEXT: .LBB15_2: 2838; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 2839; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 2840; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz 2841; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 2842; RV64IZHINXMIN-NEXT: seqz a0, a0 2843; RV64IZHINXMIN-NEXT: addi a0, a0, -1 2844; RV64IZHINXMIN-NEXT: and a0, a0, a1 2845; RV64IZHINXMIN-NEXT: ret 2846 %a = call half @llvm.round.f16(half %x) 2847 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a) 2848 ret i64 %b 2849} 2850 2851define signext i32 @test_roundeven_si32(half %x) { 2852; CHECKIZFH-LABEL: test_roundeven_si32: 2853; CHECKIZFH: # %bb.0: 2854; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne 2855; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 2856; CHECKIZFH-NEXT: seqz a1, a1 2857; CHECKIZFH-NEXT: addi a1, a1, -1 2858; CHECKIZFH-NEXT: and a0, a1, a0 2859; CHECKIZFH-NEXT: ret 2860; 2861; CHECKIZHINX-LABEL: test_roundeven_si32: 2862; CHECKIZHINX: # %bb.0: 2863; CHECKIZHINX-NEXT: li a1, 25 2864; CHECKIZHINX-NEXT: slli a1, a1, 10 2865; CHECKIZHINX-NEXT: fabs.h a2, a0 2866; CHECKIZHINX-NEXT: flt.h a1, a2, a1 2867; CHECKIZHINX-NEXT: beqz a1, .LBB16_2 2868; CHECKIZHINX-NEXT: # %bb.1: 2869; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne 2870; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne 2871; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0 2872; CHECKIZHINX-NEXT: .LBB16_2: 2873; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 2874; CHECKIZHINX-NEXT: feq.h a0, a0, a0 2875; CHECKIZHINX-NEXT: seqz a0, a0 2876; CHECKIZHINX-NEXT: addi a0, a0, -1 2877; CHECKIZHINX-NEXT: and a0, a0, a1 2878; CHECKIZHINX-NEXT: ret 2879; 2880; CHECKIZFHMIN-LABEL: test_roundeven_si32: 2881; CHECKIZFHMIN: # %bb.0: 2882; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 2883; CHECKIZFHMIN-NEXT: lui a0, 307200 2884; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0 2885; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5 2886; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4 2887; CHECKIZFHMIN-NEXT: beqz a0, .LBB16_2 2888; CHECKIZFHMIN-NEXT: # %bb.1: 2889; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 2890; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 2891; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 2892; CHECKIZFHMIN-NEXT: .LBB16_2: 2893; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5 2894; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 2895; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 2896; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 2897; CHECKIZFHMIN-NEXT: seqz a1, a1 2898; CHECKIZFHMIN-NEXT: addi a1, a1, -1 2899; CHECKIZFHMIN-NEXT: and a0, a1, a0 2900; CHECKIZFHMIN-NEXT: ret 2901; 2902; CHECKIZHINXMIN-LABEL: test_roundeven_si32: 2903; CHECKIZHINXMIN: # %bb.0: 2904; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 2905; CHECKIZHINXMIN-NEXT: lui a1, 307200 2906; CHECKIZHINXMIN-NEXT: fabs.s a2, a0 2907; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1 2908; CHECKIZHINXMIN-NEXT: beqz a1, .LBB16_2 2909; CHECKIZHINXMIN-NEXT: # %bb.1: 2910; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 2911; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 2912; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0 2913; CHECKIZHINXMIN-NEXT: .LBB16_2: 2914; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 2915; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 2916; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 2917; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 2918; CHECKIZHINXMIN-NEXT: seqz a0, a0 2919; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 2920; CHECKIZHINXMIN-NEXT: and a0, a0, a1 2921; CHECKIZHINXMIN-NEXT: ret 2922 %a = call half @llvm.roundeven.f16(half %x) 2923 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a) 2924 ret i32 %b 2925} 2926 2927define i64 @test_roundeven_si64(half %x) nounwind { 2928; RV32IZFH-LABEL: test_roundeven_si64: 2929; RV32IZFH: # %bb.0: 2930; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_0) 2931; RV32IZFH-NEXT: flh fa5, %lo(.LCPI17_0)(a0) 2932; RV32IZFH-NEXT: fabs.h fa4, fa0 2933; RV32IZFH-NEXT: flt.h a0, fa4, fa5 2934; RV32IZFH-NEXT: beqz a0, .LBB17_2 2935; RV32IZFH-NEXT: # %bb.1: 2936; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne 2937; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne 2938; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 2939; RV32IZFH-NEXT: .LBB17_2: 2940; RV32IZFH-NEXT: addi sp, sp, -16 2941; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2942; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2943; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 2944; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 2945; RV32IZFH-NEXT: lui a0, 913408 2946; RV32IZFH-NEXT: fmv.w.x fa5, a0 2947; RV32IZFH-NEXT: fle.s s0, fa5, fs0 2948; RV32IZFH-NEXT: fmv.s fa0, fs0 2949; RV32IZFH-NEXT: call __fixsfdi 2950; RV32IZFH-NEXT: lui a3, 524288 2951; RV32IZFH-NEXT: lui a2, 524288 2952; RV32IZFH-NEXT: beqz s0, .LBB17_4 2953; RV32IZFH-NEXT: # %bb.3: 2954; RV32IZFH-NEXT: mv a2, a1 2955; RV32IZFH-NEXT: .LBB17_4: 2956; RV32IZFH-NEXT: lui a1, %hi(.LCPI17_1) 2957; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a1) 2958; RV32IZFH-NEXT: flt.s a1, fa5, fs0 2959; RV32IZFH-NEXT: beqz a1, .LBB17_6 2960; RV32IZFH-NEXT: # %bb.5: 2961; RV32IZFH-NEXT: addi a2, a3, -1 2962; RV32IZFH-NEXT: .LBB17_6: 2963; RV32IZFH-NEXT: feq.s a3, fs0, fs0 2964; RV32IZFH-NEXT: neg a4, s0 2965; RV32IZFH-NEXT: neg a5, a1 2966; RV32IZFH-NEXT: neg a3, a3 2967; RV32IZFH-NEXT: and a0, a4, a0 2968; RV32IZFH-NEXT: and a1, a3, a2 2969; RV32IZFH-NEXT: or a0, a5, a0 2970; RV32IZFH-NEXT: and a0, a3, a0 2971; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2972; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2973; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 2974; RV32IZFH-NEXT: addi sp, sp, 16 2975; RV32IZFH-NEXT: ret 2976; 2977; RV64IZFH-LABEL: test_roundeven_si64: 2978; RV64IZFH: # %bb.0: 2979; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne 2980; RV64IZFH-NEXT: feq.h a1, fa0, fa0 2981; RV64IZFH-NEXT: seqz a1, a1 2982; RV64IZFH-NEXT: addi a1, a1, -1 2983; RV64IZFH-NEXT: and a0, a1, a0 2984; RV64IZFH-NEXT: ret 2985; 2986; RV32IZHINX-LABEL: test_roundeven_si64: 2987; RV32IZHINX: # %bb.0: 2988; RV32IZHINX-NEXT: li a1, 25 2989; RV32IZHINX-NEXT: slli a1, a1, 10 2990; RV32IZHINX-NEXT: fabs.h a2, a0 2991; RV32IZHINX-NEXT: flt.h a1, a2, a1 2992; RV32IZHINX-NEXT: beqz a1, .LBB17_2 2993; RV32IZHINX-NEXT: # %bb.1: 2994; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne 2995; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne 2996; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 2997; RV32IZHINX-NEXT: .LBB17_2: 2998; RV32IZHINX-NEXT: addi sp, sp, -16 2999; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3000; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3001; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3002; RV32IZHINX-NEXT: fcvt.s.h s0, a0 3003; RV32IZHINX-NEXT: lui a0, 913408 3004; RV32IZHINX-NEXT: fle.s s1, a0, s0 3005; RV32IZHINX-NEXT: mv a0, s0 3006; RV32IZHINX-NEXT: call __fixsfdi 3007; RV32IZHINX-NEXT: lui a3, 524288 3008; RV32IZHINX-NEXT: lui a2, 524288 3009; RV32IZHINX-NEXT: beqz s1, .LBB17_4 3010; RV32IZHINX-NEXT: # %bb.3: 3011; RV32IZHINX-NEXT: mv a2, a1 3012; RV32IZHINX-NEXT: .LBB17_4: 3013; RV32IZHINX-NEXT: lui a1, 389120 3014; RV32IZHINX-NEXT: addi a1, a1, -1 3015; RV32IZHINX-NEXT: flt.s a1, a1, s0 3016; RV32IZHINX-NEXT: beqz a1, .LBB17_6 3017; RV32IZHINX-NEXT: # %bb.5: 3018; RV32IZHINX-NEXT: addi a2, a3, -1 3019; RV32IZHINX-NEXT: .LBB17_6: 3020; RV32IZHINX-NEXT: feq.s a3, s0, s0 3021; RV32IZHINX-NEXT: neg a4, s1 3022; RV32IZHINX-NEXT: neg a5, a1 3023; RV32IZHINX-NEXT: neg a3, a3 3024; RV32IZHINX-NEXT: and a0, a4, a0 3025; RV32IZHINX-NEXT: and a1, a3, a2 3026; RV32IZHINX-NEXT: or a0, a5, a0 3027; RV32IZHINX-NEXT: and a0, a3, a0 3028; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3029; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3030; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3031; RV32IZHINX-NEXT: addi sp, sp, 16 3032; RV32IZHINX-NEXT: ret 3033; 3034; RV64IZHINX-LABEL: test_roundeven_si64: 3035; RV64IZHINX: # %bb.0: 3036; RV64IZHINX-NEXT: li a1, 25 3037; RV64IZHINX-NEXT: slli a1, a1, 10 3038; RV64IZHINX-NEXT: fabs.h a2, a0 3039; RV64IZHINX-NEXT: flt.h a1, a2, a1 3040; RV64IZHINX-NEXT: beqz a1, .LBB17_2 3041; RV64IZHINX-NEXT: # %bb.1: 3042; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne 3043; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne 3044; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 3045; RV64IZHINX-NEXT: .LBB17_2: 3046; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz 3047; RV64IZHINX-NEXT: feq.h a0, a0, a0 3048; RV64IZHINX-NEXT: seqz a0, a0 3049; RV64IZHINX-NEXT: addi a0, a0, -1 3050; RV64IZHINX-NEXT: and a0, a0, a1 3051; RV64IZHINX-NEXT: ret 3052; 3053; RV32IZFHMIN-LABEL: test_roundeven_si64: 3054; RV32IZFHMIN: # %bb.0: 3055; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3056; RV32IZFHMIN-NEXT: lui a0, 307200 3057; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 3058; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 3059; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 3060; RV32IZFHMIN-NEXT: beqz a0, .LBB17_2 3061; RV32IZFHMIN-NEXT: # %bb.1: 3062; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 3063; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 3064; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3065; RV32IZFHMIN-NEXT: .LBB17_2: 3066; RV32IZFHMIN-NEXT: addi sp, sp, -16 3067; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3068; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3069; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 3070; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3071; RV32IZFHMIN-NEXT: lui a0, 913408 3072; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 3073; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 3074; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 3075; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 3076; RV32IZFHMIN-NEXT: call __fixsfdi 3077; RV32IZFHMIN-NEXT: lui a3, 524288 3078; RV32IZFHMIN-NEXT: lui a2, 524288 3079; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4 3080; RV32IZFHMIN-NEXT: # %bb.3: 3081; RV32IZFHMIN-NEXT: mv a2, a1 3082; RV32IZFHMIN-NEXT: .LBB17_4: 3083; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI17_0) 3084; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a1) 3085; RV32IZFHMIN-NEXT: flt.s a1, fa5, fs0 3086; RV32IZFHMIN-NEXT: beqz a1, .LBB17_6 3087; RV32IZFHMIN-NEXT: # %bb.5: 3088; RV32IZFHMIN-NEXT: addi a2, a3, -1 3089; RV32IZFHMIN-NEXT: .LBB17_6: 3090; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 3091; RV32IZFHMIN-NEXT: neg a4, s0 3092; RV32IZFHMIN-NEXT: neg a5, a1 3093; RV32IZFHMIN-NEXT: neg a3, a3 3094; RV32IZFHMIN-NEXT: and a0, a4, a0 3095; RV32IZFHMIN-NEXT: and a1, a3, a2 3096; RV32IZFHMIN-NEXT: or a0, a5, a0 3097; RV32IZFHMIN-NEXT: and a0, a3, a0 3098; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3099; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3100; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 3101; RV32IZFHMIN-NEXT: addi sp, sp, 16 3102; RV32IZFHMIN-NEXT: ret 3103; 3104; RV64IZFHMIN-LABEL: test_roundeven_si64: 3105; RV64IZFHMIN: # %bb.0: 3106; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3107; RV64IZFHMIN-NEXT: lui a0, 307200 3108; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 3109; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 3110; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 3111; RV64IZFHMIN-NEXT: beqz a0, .LBB17_2 3112; RV64IZFHMIN-NEXT: # %bb.1: 3113; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 3114; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 3115; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3116; RV64IZFHMIN-NEXT: .LBB17_2: 3117; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3118; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3119; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz 3120; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 3121; RV64IZFHMIN-NEXT: seqz a1, a1 3122; RV64IZFHMIN-NEXT: addi a1, a1, -1 3123; RV64IZFHMIN-NEXT: and a0, a1, a0 3124; RV64IZFHMIN-NEXT: ret 3125; 3126; RV32IZHINXMIN-LABEL: test_roundeven_si64: 3127; RV32IZHINXMIN: # %bb.0: 3128; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 3129; RV32IZHINXMIN-NEXT: lui a1, 307200 3130; RV32IZHINXMIN-NEXT: fabs.s a2, a0 3131; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 3132; RV32IZHINXMIN-NEXT: beqz a1, .LBB17_2 3133; RV32IZHINXMIN-NEXT: # %bb.1: 3134; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 3135; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 3136; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3137; RV32IZHINXMIN-NEXT: .LBB17_2: 3138; RV32IZHINXMIN-NEXT: addi sp, sp, -16 3139; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3140; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3141; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3142; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 3143; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 3144; RV32IZHINXMIN-NEXT: lui a0, 913408 3145; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 3146; RV32IZHINXMIN-NEXT: mv a0, s0 3147; RV32IZHINXMIN-NEXT: call __fixsfdi 3148; RV32IZHINXMIN-NEXT: lui a3, 524288 3149; RV32IZHINXMIN-NEXT: lui a2, 524288 3150; RV32IZHINXMIN-NEXT: beqz s1, .LBB17_4 3151; RV32IZHINXMIN-NEXT: # %bb.3: 3152; RV32IZHINXMIN-NEXT: mv a2, a1 3153; RV32IZHINXMIN-NEXT: .LBB17_4: 3154; RV32IZHINXMIN-NEXT: lui a1, 389120 3155; RV32IZHINXMIN-NEXT: addi a1, a1, -1 3156; RV32IZHINXMIN-NEXT: flt.s a1, a1, s0 3157; RV32IZHINXMIN-NEXT: beqz a1, .LBB17_6 3158; RV32IZHINXMIN-NEXT: # %bb.5: 3159; RV32IZHINXMIN-NEXT: addi a2, a3, -1 3160; RV32IZHINXMIN-NEXT: .LBB17_6: 3161; RV32IZHINXMIN-NEXT: feq.s a3, s0, s0 3162; RV32IZHINXMIN-NEXT: neg a4, s1 3163; RV32IZHINXMIN-NEXT: neg a5, a1 3164; RV32IZHINXMIN-NEXT: neg a3, a3 3165; RV32IZHINXMIN-NEXT: and a0, a4, a0 3166; RV32IZHINXMIN-NEXT: and a1, a3, a2 3167; RV32IZHINXMIN-NEXT: or a0, a5, a0 3168; RV32IZHINXMIN-NEXT: and a0, a3, a0 3169; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3170; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3171; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3172; RV32IZHINXMIN-NEXT: addi sp, sp, 16 3173; RV32IZHINXMIN-NEXT: ret 3174; 3175; RV64IZHINXMIN-LABEL: test_roundeven_si64: 3176; RV64IZHINXMIN: # %bb.0: 3177; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3178; RV64IZHINXMIN-NEXT: lui a1, 307200 3179; RV64IZHINXMIN-NEXT: fabs.s a2, a0 3180; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 3181; RV64IZHINXMIN-NEXT: beqz a1, .LBB17_2 3182; RV64IZHINXMIN-NEXT: # %bb.1: 3183; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 3184; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 3185; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3186; RV64IZHINXMIN-NEXT: .LBB17_2: 3187; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 3188; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3189; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz 3190; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 3191; RV64IZHINXMIN-NEXT: seqz a0, a0 3192; RV64IZHINXMIN-NEXT: addi a0, a0, -1 3193; RV64IZHINXMIN-NEXT: and a0, a0, a1 3194; RV64IZHINXMIN-NEXT: ret 3195 %a = call half @llvm.roundeven.f16(half %x) 3196 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a) 3197 ret i64 %b 3198} 3199 3200define signext i32 @test_roundeven_ui32(half %x) { 3201; CHECKIZFH-LABEL: test_roundeven_ui32: 3202; CHECKIZFH: # %bb.0: 3203; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rne 3204; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 3205; CHECKIZFH-NEXT: seqz a1, a1 3206; CHECKIZFH-NEXT: addi a1, a1, -1 3207; CHECKIZFH-NEXT: and a0, a1, a0 3208; CHECKIZFH-NEXT: ret 3209; 3210; RV32IZHINX-LABEL: test_roundeven_ui32: 3211; RV32IZHINX: # %bb.0: 3212; RV32IZHINX-NEXT: li a1, 25 3213; RV32IZHINX-NEXT: slli a1, a1, 10 3214; RV32IZHINX-NEXT: fabs.h a2, a0 3215; RV32IZHINX-NEXT: flt.h a1, a2, a1 3216; RV32IZHINX-NEXT: beqz a1, .LBB18_2 3217; RV32IZHINX-NEXT: # %bb.1: 3218; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne 3219; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne 3220; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 3221; RV32IZHINX-NEXT: .LBB18_2: 3222; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 3223; RV32IZHINX-NEXT: feq.h a0, a0, a0 3224; RV32IZHINX-NEXT: seqz a0, a0 3225; RV32IZHINX-NEXT: addi a0, a0, -1 3226; RV32IZHINX-NEXT: and a0, a0, a1 3227; RV32IZHINX-NEXT: ret 3228; 3229; RV64IZHINX-LABEL: test_roundeven_ui32: 3230; RV64IZHINX: # %bb.0: 3231; RV64IZHINX-NEXT: li a1, 25 3232; RV64IZHINX-NEXT: slli a1, a1, 10 3233; RV64IZHINX-NEXT: fabs.h a2, a0 3234; RV64IZHINX-NEXT: flt.h a1, a2, a1 3235; RV64IZHINX-NEXT: beqz a1, .LBB18_2 3236; RV64IZHINX-NEXT: # %bb.1: 3237; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne 3238; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne 3239; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 3240; RV64IZHINX-NEXT: .LBB18_2: 3241; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 3242; RV64IZHINX-NEXT: feq.h a0, a0, a0 3243; RV64IZHINX-NEXT: seqz a0, a0 3244; RV64IZHINX-NEXT: addiw a0, a0, -1 3245; RV64IZHINX-NEXT: and a0, a1, a0 3246; RV64IZHINX-NEXT: ret 3247; 3248; RV32IZFHMIN-LABEL: test_roundeven_ui32: 3249; RV32IZFHMIN: # %bb.0: 3250; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3251; RV32IZFHMIN-NEXT: lui a0, 307200 3252; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 3253; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 3254; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 3255; RV32IZFHMIN-NEXT: beqz a0, .LBB18_2 3256; RV32IZFHMIN-NEXT: # %bb.1: 3257; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 3258; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 3259; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3260; RV32IZFHMIN-NEXT: .LBB18_2: 3261; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3262; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3263; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 3264; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5 3265; RV32IZFHMIN-NEXT: seqz a1, a1 3266; RV32IZFHMIN-NEXT: addi a1, a1, -1 3267; RV32IZFHMIN-NEXT: and a0, a1, a0 3268; RV32IZFHMIN-NEXT: ret 3269; 3270; RV64IZFHMIN-LABEL: test_roundeven_ui32: 3271; RV64IZFHMIN: # %bb.0: 3272; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3273; RV64IZFHMIN-NEXT: lui a0, 307200 3274; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 3275; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 3276; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 3277; RV64IZFHMIN-NEXT: beqz a0, .LBB18_2 3278; RV64IZFHMIN-NEXT: # %bb.1: 3279; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 3280; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 3281; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3282; RV64IZFHMIN-NEXT: .LBB18_2: 3283; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3284; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3285; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 3286; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 3287; RV64IZFHMIN-NEXT: seqz a1, a1 3288; RV64IZFHMIN-NEXT: addiw a1, a1, -1 3289; RV64IZFHMIN-NEXT: and a0, a0, a1 3290; RV64IZFHMIN-NEXT: ret 3291; 3292; RV32IZHINXMIN-LABEL: test_roundeven_ui32: 3293; RV32IZHINXMIN: # %bb.0: 3294; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 3295; RV32IZHINXMIN-NEXT: lui a1, 307200 3296; RV32IZHINXMIN-NEXT: fabs.s a2, a0 3297; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 3298; RV32IZHINXMIN-NEXT: beqz a1, .LBB18_2 3299; RV32IZHINXMIN-NEXT: # %bb.1: 3300; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 3301; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 3302; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3303; RV32IZHINXMIN-NEXT: .LBB18_2: 3304; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 3305; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 3306; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 3307; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0 3308; RV32IZHINXMIN-NEXT: seqz a0, a0 3309; RV32IZHINXMIN-NEXT: addi a0, a0, -1 3310; RV32IZHINXMIN-NEXT: and a0, a0, a1 3311; RV32IZHINXMIN-NEXT: ret 3312; 3313; RV64IZHINXMIN-LABEL: test_roundeven_ui32: 3314; RV64IZHINXMIN: # %bb.0: 3315; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3316; RV64IZHINXMIN-NEXT: lui a1, 307200 3317; RV64IZHINXMIN-NEXT: fabs.s a2, a0 3318; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 3319; RV64IZHINXMIN-NEXT: beqz a1, .LBB18_2 3320; RV64IZHINXMIN-NEXT: # %bb.1: 3321; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 3322; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 3323; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3324; RV64IZHINXMIN-NEXT: .LBB18_2: 3325; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 3326; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3327; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 3328; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 3329; RV64IZHINXMIN-NEXT: seqz a0, a0 3330; RV64IZHINXMIN-NEXT: addiw a0, a0, -1 3331; RV64IZHINXMIN-NEXT: and a0, a1, a0 3332; RV64IZHINXMIN-NEXT: ret 3333 %a = call half @llvm.roundeven.f16(half %x) 3334 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a) 3335 ret i32 %b 3336} 3337 3338define i64 @test_roundeven_ui64(half %x) nounwind { 3339; RV32IZFH-LABEL: test_roundeven_ui64: 3340; RV32IZFH: # %bb.0: 3341; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0) 3342; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0) 3343; RV32IZFH-NEXT: fabs.h fa4, fa0 3344; RV32IZFH-NEXT: flt.h a0, fa4, fa5 3345; RV32IZFH-NEXT: beqz a0, .LBB19_2 3346; RV32IZFH-NEXT: # %bb.1: 3347; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne 3348; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne 3349; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 3350; RV32IZFH-NEXT: .LBB19_2: 3351; RV32IZFH-NEXT: addi sp, sp, -16 3352; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3353; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3354; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 3355; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 3356; RV32IZFH-NEXT: fmv.w.x fa5, zero 3357; RV32IZFH-NEXT: fle.s a0, fa5, fs0 3358; RV32IZFH-NEXT: neg s0, a0 3359; RV32IZFH-NEXT: fmv.s fa0, fs0 3360; RV32IZFH-NEXT: call __fixunssfdi 3361; RV32IZFH-NEXT: lui a2, %hi(.LCPI19_1) 3362; RV32IZFH-NEXT: flw fa5, %lo(.LCPI19_1)(a2) 3363; RV32IZFH-NEXT: and a0, s0, a0 3364; RV32IZFH-NEXT: and a1, s0, a1 3365; RV32IZFH-NEXT: flt.s a2, fa5, fs0 3366; RV32IZFH-NEXT: neg a2, a2 3367; RV32IZFH-NEXT: or a0, a2, a0 3368; RV32IZFH-NEXT: or a1, a2, a1 3369; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3370; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3371; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 3372; RV32IZFH-NEXT: addi sp, sp, 16 3373; RV32IZFH-NEXT: ret 3374; 3375; RV64IZFH-LABEL: test_roundeven_ui64: 3376; RV64IZFH: # %bb.0: 3377; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne 3378; RV64IZFH-NEXT: feq.h a1, fa0, fa0 3379; RV64IZFH-NEXT: seqz a1, a1 3380; RV64IZFH-NEXT: addi a1, a1, -1 3381; RV64IZFH-NEXT: and a0, a1, a0 3382; RV64IZFH-NEXT: ret 3383; 3384; RV32IZHINX-LABEL: test_roundeven_ui64: 3385; RV32IZHINX: # %bb.0: 3386; RV32IZHINX-NEXT: li a1, 25 3387; RV32IZHINX-NEXT: slli a1, a1, 10 3388; RV32IZHINX-NEXT: fabs.h a2, a0 3389; RV32IZHINX-NEXT: flt.h a1, a2, a1 3390; RV32IZHINX-NEXT: beqz a1, .LBB19_2 3391; RV32IZHINX-NEXT: # %bb.1: 3392; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne 3393; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne 3394; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 3395; RV32IZHINX-NEXT: .LBB19_2: 3396; RV32IZHINX-NEXT: addi sp, sp, -16 3397; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3398; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3399; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3400; RV32IZHINX-NEXT: fcvt.s.h s0, a0 3401; RV32IZHINX-NEXT: fle.s a0, zero, s0 3402; RV32IZHINX-NEXT: neg s1, a0 3403; RV32IZHINX-NEXT: mv a0, s0 3404; RV32IZHINX-NEXT: call __fixunssfdi 3405; RV32IZHINX-NEXT: and a0, s1, a0 3406; RV32IZHINX-NEXT: lui a2, 391168 3407; RV32IZHINX-NEXT: and a1, s1, a1 3408; RV32IZHINX-NEXT: addi a2, a2, -1 3409; RV32IZHINX-NEXT: flt.s a2, a2, s0 3410; RV32IZHINX-NEXT: neg a2, a2 3411; RV32IZHINX-NEXT: or a0, a2, a0 3412; RV32IZHINX-NEXT: or a1, a2, a1 3413; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3414; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3415; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3416; RV32IZHINX-NEXT: addi sp, sp, 16 3417; RV32IZHINX-NEXT: ret 3418; 3419; RV64IZHINX-LABEL: test_roundeven_ui64: 3420; RV64IZHINX: # %bb.0: 3421; RV64IZHINX-NEXT: li a1, 25 3422; RV64IZHINX-NEXT: slli a1, a1, 10 3423; RV64IZHINX-NEXT: fabs.h a2, a0 3424; RV64IZHINX-NEXT: flt.h a1, a2, a1 3425; RV64IZHINX-NEXT: beqz a1, .LBB19_2 3426; RV64IZHINX-NEXT: # %bb.1: 3427; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne 3428; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne 3429; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 3430; RV64IZHINX-NEXT: .LBB19_2: 3431; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz 3432; RV64IZHINX-NEXT: feq.h a0, a0, a0 3433; RV64IZHINX-NEXT: seqz a0, a0 3434; RV64IZHINX-NEXT: addi a0, a0, -1 3435; RV64IZHINX-NEXT: and a0, a0, a1 3436; RV64IZHINX-NEXT: ret 3437; 3438; RV32IZFHMIN-LABEL: test_roundeven_ui64: 3439; RV32IZFHMIN: # %bb.0: 3440; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3441; RV32IZFHMIN-NEXT: lui a0, 307200 3442; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 3443; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 3444; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 3445; RV32IZFHMIN-NEXT: beqz a0, .LBB19_2 3446; RV32IZFHMIN-NEXT: # %bb.1: 3447; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 3448; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 3449; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3450; RV32IZFHMIN-NEXT: .LBB19_2: 3451; RV32IZFHMIN-NEXT: addi sp, sp, -16 3452; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3453; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3454; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 3455; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3456; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 3457; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero 3458; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 3459; RV32IZFHMIN-NEXT: neg s0, a0 3460; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 3461; RV32IZFHMIN-NEXT: call __fixunssfdi 3462; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI19_0) 3463; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI19_0)(a2) 3464; RV32IZFHMIN-NEXT: and a0, s0, a0 3465; RV32IZFHMIN-NEXT: and a1, s0, a1 3466; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 3467; RV32IZFHMIN-NEXT: neg a2, a2 3468; RV32IZFHMIN-NEXT: or a0, a2, a0 3469; RV32IZFHMIN-NEXT: or a1, a2, a1 3470; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3471; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3472; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 3473; RV32IZFHMIN-NEXT: addi sp, sp, 16 3474; RV32IZFHMIN-NEXT: ret 3475; 3476; RV64IZFHMIN-LABEL: test_roundeven_ui64: 3477; RV64IZFHMIN: # %bb.0: 3478; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3479; RV64IZFHMIN-NEXT: lui a0, 307200 3480; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 3481; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 3482; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 3483; RV64IZFHMIN-NEXT: beqz a0, .LBB19_2 3484; RV64IZFHMIN-NEXT: # %bb.1: 3485; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne 3486; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne 3487; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3488; RV64IZFHMIN-NEXT: .LBB19_2: 3489; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3490; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3491; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 3492; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 3493; RV64IZFHMIN-NEXT: seqz a1, a1 3494; RV64IZFHMIN-NEXT: addi a1, a1, -1 3495; RV64IZFHMIN-NEXT: and a0, a1, a0 3496; RV64IZFHMIN-NEXT: ret 3497; 3498; RV32IZHINXMIN-LABEL: test_roundeven_ui64: 3499; RV32IZHINXMIN: # %bb.0: 3500; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 3501; RV32IZHINXMIN-NEXT: lui a1, 307200 3502; RV32IZHINXMIN-NEXT: fabs.s a2, a0 3503; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 3504; RV32IZHINXMIN-NEXT: beqz a1, .LBB19_2 3505; RV32IZHINXMIN-NEXT: # %bb.1: 3506; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 3507; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 3508; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3509; RV32IZHINXMIN-NEXT: .LBB19_2: 3510; RV32IZHINXMIN-NEXT: addi sp, sp, -16 3511; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3512; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3513; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3514; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 3515; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 3516; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 3517; RV32IZHINXMIN-NEXT: neg s1, a0 3518; RV32IZHINXMIN-NEXT: mv a0, s0 3519; RV32IZHINXMIN-NEXT: call __fixunssfdi 3520; RV32IZHINXMIN-NEXT: and a0, s1, a0 3521; RV32IZHINXMIN-NEXT: lui a2, 391168 3522; RV32IZHINXMIN-NEXT: and a1, s1, a1 3523; RV32IZHINXMIN-NEXT: addi a2, a2, -1 3524; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 3525; RV32IZHINXMIN-NEXT: neg a2, a2 3526; RV32IZHINXMIN-NEXT: or a0, a2, a0 3527; RV32IZHINXMIN-NEXT: or a1, a2, a1 3528; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3529; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3530; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3531; RV32IZHINXMIN-NEXT: addi sp, sp, 16 3532; RV32IZHINXMIN-NEXT: ret 3533; 3534; RV64IZHINXMIN-LABEL: test_roundeven_ui64: 3535; RV64IZHINXMIN: # %bb.0: 3536; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3537; RV64IZHINXMIN-NEXT: lui a1, 307200 3538; RV64IZHINXMIN-NEXT: fabs.s a2, a0 3539; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 3540; RV64IZHINXMIN-NEXT: beqz a1, .LBB19_2 3541; RV64IZHINXMIN-NEXT: # %bb.1: 3542; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne 3543; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne 3544; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3545; RV64IZHINXMIN-NEXT: .LBB19_2: 3546; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 3547; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3548; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz 3549; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 3550; RV64IZHINXMIN-NEXT: seqz a0, a0 3551; RV64IZHINXMIN-NEXT: addi a0, a0, -1 3552; RV64IZHINXMIN-NEXT: and a0, a0, a1 3553; RV64IZHINXMIN-NEXT: ret 3554 %a = call half @llvm.roundeven.f16(half %x) 3555 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a) 3556 ret i64 %b 3557} 3558 3559define signext i32 @test_rint_si32(half %x) { 3560; CHECKIZFH-LABEL: test_rint_si32: 3561; CHECKIZFH: # %bb.0: 3562; CHECKIZFH-NEXT: fcvt.w.h a0, fa0 3563; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 3564; CHECKIZFH-NEXT: seqz a1, a1 3565; CHECKIZFH-NEXT: addi a1, a1, -1 3566; CHECKIZFH-NEXT: and a0, a1, a0 3567; CHECKIZFH-NEXT: ret 3568; 3569; CHECKIZHINX-LABEL: test_rint_si32: 3570; CHECKIZHINX: # %bb.0: 3571; CHECKIZHINX-NEXT: li a1, 25 3572; CHECKIZHINX-NEXT: slli a1, a1, 10 3573; CHECKIZHINX-NEXT: fabs.h a2, a0 3574; CHECKIZHINX-NEXT: flt.h a1, a2, a1 3575; CHECKIZHINX-NEXT: beqz a1, .LBB20_2 3576; CHECKIZHINX-NEXT: # %bb.1: 3577; CHECKIZHINX-NEXT: fcvt.w.h a1, a0 3578; CHECKIZHINX-NEXT: fcvt.h.w a1, a1 3579; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0 3580; CHECKIZHINX-NEXT: .LBB20_2: 3581; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz 3582; CHECKIZHINX-NEXT: feq.h a0, a0, a0 3583; CHECKIZHINX-NEXT: seqz a0, a0 3584; CHECKIZHINX-NEXT: addi a0, a0, -1 3585; CHECKIZHINX-NEXT: and a0, a0, a1 3586; CHECKIZHINX-NEXT: ret 3587; 3588; CHECKIZFHMIN-LABEL: test_rint_si32: 3589; CHECKIZFHMIN: # %bb.0: 3590; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 3591; CHECKIZFHMIN-NEXT: lui a0, 307200 3592; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0 3593; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5 3594; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4 3595; CHECKIZFHMIN-NEXT: beqz a0, .LBB20_2 3596; CHECKIZFHMIN-NEXT: # %bb.1: 3597; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5 3598; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0 3599; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3600; CHECKIZFHMIN-NEXT: .LBB20_2: 3601; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5 3602; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 3603; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 3604; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 3605; CHECKIZFHMIN-NEXT: seqz a1, a1 3606; CHECKIZFHMIN-NEXT: addi a1, a1, -1 3607; CHECKIZFHMIN-NEXT: and a0, a1, a0 3608; CHECKIZFHMIN-NEXT: ret 3609; 3610; CHECKIZHINXMIN-LABEL: test_rint_si32: 3611; CHECKIZHINXMIN: # %bb.0: 3612; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 3613; CHECKIZHINXMIN-NEXT: lui a1, 307200 3614; CHECKIZHINXMIN-NEXT: fabs.s a2, a0 3615; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1 3616; CHECKIZHINXMIN-NEXT: beqz a1, .LBB20_2 3617; CHECKIZHINXMIN-NEXT: # %bb.1: 3618; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0 3619; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1 3620; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3621; CHECKIZHINXMIN-NEXT: .LBB20_2: 3622; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 3623; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 3624; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz 3625; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 3626; CHECKIZHINXMIN-NEXT: seqz a0, a0 3627; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 3628; CHECKIZHINXMIN-NEXT: and a0, a0, a1 3629; CHECKIZHINXMIN-NEXT: ret 3630 %a = call half @llvm.rint.f16(half %x) 3631 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a) 3632 ret i32 %b 3633} 3634 3635define i64 @test_rint_si64(half %x) nounwind { 3636; RV32IZFH-LABEL: test_rint_si64: 3637; RV32IZFH: # %bb.0: 3638; RV32IZFH-NEXT: lui a0, %hi(.LCPI21_0) 3639; RV32IZFH-NEXT: flh fa5, %lo(.LCPI21_0)(a0) 3640; RV32IZFH-NEXT: fabs.h fa4, fa0 3641; RV32IZFH-NEXT: flt.h a0, fa4, fa5 3642; RV32IZFH-NEXT: beqz a0, .LBB21_2 3643; RV32IZFH-NEXT: # %bb.1: 3644; RV32IZFH-NEXT: fcvt.w.h a0, fa0 3645; RV32IZFH-NEXT: fcvt.h.w fa5, a0 3646; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 3647; RV32IZFH-NEXT: .LBB21_2: 3648; RV32IZFH-NEXT: addi sp, sp, -16 3649; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3650; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3651; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 3652; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 3653; RV32IZFH-NEXT: lui a0, 913408 3654; RV32IZFH-NEXT: fmv.w.x fa5, a0 3655; RV32IZFH-NEXT: fle.s s0, fa5, fs0 3656; RV32IZFH-NEXT: fmv.s fa0, fs0 3657; RV32IZFH-NEXT: call __fixsfdi 3658; RV32IZFH-NEXT: lui a3, 524288 3659; RV32IZFH-NEXT: lui a2, 524288 3660; RV32IZFH-NEXT: beqz s0, .LBB21_4 3661; RV32IZFH-NEXT: # %bb.3: 3662; RV32IZFH-NEXT: mv a2, a1 3663; RV32IZFH-NEXT: .LBB21_4: 3664; RV32IZFH-NEXT: lui a1, %hi(.LCPI21_1) 3665; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a1) 3666; RV32IZFH-NEXT: flt.s a1, fa5, fs0 3667; RV32IZFH-NEXT: beqz a1, .LBB21_6 3668; RV32IZFH-NEXT: # %bb.5: 3669; RV32IZFH-NEXT: addi a2, a3, -1 3670; RV32IZFH-NEXT: .LBB21_6: 3671; RV32IZFH-NEXT: feq.s a3, fs0, fs0 3672; RV32IZFH-NEXT: neg a4, s0 3673; RV32IZFH-NEXT: neg a5, a1 3674; RV32IZFH-NEXT: neg a3, a3 3675; RV32IZFH-NEXT: and a0, a4, a0 3676; RV32IZFH-NEXT: and a1, a3, a2 3677; RV32IZFH-NEXT: or a0, a5, a0 3678; RV32IZFH-NEXT: and a0, a3, a0 3679; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3680; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3681; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 3682; RV32IZFH-NEXT: addi sp, sp, 16 3683; RV32IZFH-NEXT: ret 3684; 3685; RV64IZFH-LABEL: test_rint_si64: 3686; RV64IZFH: # %bb.0: 3687; RV64IZFH-NEXT: fcvt.l.h a0, fa0 3688; RV64IZFH-NEXT: feq.h a1, fa0, fa0 3689; RV64IZFH-NEXT: seqz a1, a1 3690; RV64IZFH-NEXT: addi a1, a1, -1 3691; RV64IZFH-NEXT: and a0, a1, a0 3692; RV64IZFH-NEXT: ret 3693; 3694; RV32IZHINX-LABEL: test_rint_si64: 3695; RV32IZHINX: # %bb.0: 3696; RV32IZHINX-NEXT: li a1, 25 3697; RV32IZHINX-NEXT: slli a1, a1, 10 3698; RV32IZHINX-NEXT: fabs.h a2, a0 3699; RV32IZHINX-NEXT: flt.h a1, a2, a1 3700; RV32IZHINX-NEXT: beqz a1, .LBB21_2 3701; RV32IZHINX-NEXT: # %bb.1: 3702; RV32IZHINX-NEXT: fcvt.w.h a1, a0 3703; RV32IZHINX-NEXT: fcvt.h.w a1, a1 3704; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 3705; RV32IZHINX-NEXT: .LBB21_2: 3706; RV32IZHINX-NEXT: addi sp, sp, -16 3707; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3708; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3709; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3710; RV32IZHINX-NEXT: fcvt.s.h s0, a0 3711; RV32IZHINX-NEXT: lui a0, 913408 3712; RV32IZHINX-NEXT: fle.s s1, a0, s0 3713; RV32IZHINX-NEXT: mv a0, s0 3714; RV32IZHINX-NEXT: call __fixsfdi 3715; RV32IZHINX-NEXT: lui a3, 524288 3716; RV32IZHINX-NEXT: lui a2, 524288 3717; RV32IZHINX-NEXT: beqz s1, .LBB21_4 3718; RV32IZHINX-NEXT: # %bb.3: 3719; RV32IZHINX-NEXT: mv a2, a1 3720; RV32IZHINX-NEXT: .LBB21_4: 3721; RV32IZHINX-NEXT: lui a1, 389120 3722; RV32IZHINX-NEXT: addi a1, a1, -1 3723; RV32IZHINX-NEXT: flt.s a1, a1, s0 3724; RV32IZHINX-NEXT: beqz a1, .LBB21_6 3725; RV32IZHINX-NEXT: # %bb.5: 3726; RV32IZHINX-NEXT: addi a2, a3, -1 3727; RV32IZHINX-NEXT: .LBB21_6: 3728; RV32IZHINX-NEXT: feq.s a3, s0, s0 3729; RV32IZHINX-NEXT: neg a4, s1 3730; RV32IZHINX-NEXT: neg a5, a1 3731; RV32IZHINX-NEXT: neg a3, a3 3732; RV32IZHINX-NEXT: and a0, a4, a0 3733; RV32IZHINX-NEXT: and a1, a3, a2 3734; RV32IZHINX-NEXT: or a0, a5, a0 3735; RV32IZHINX-NEXT: and a0, a3, a0 3736; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3737; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3738; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3739; RV32IZHINX-NEXT: addi sp, sp, 16 3740; RV32IZHINX-NEXT: ret 3741; 3742; RV64IZHINX-LABEL: test_rint_si64: 3743; RV64IZHINX: # %bb.0: 3744; RV64IZHINX-NEXT: li a1, 25 3745; RV64IZHINX-NEXT: slli a1, a1, 10 3746; RV64IZHINX-NEXT: fabs.h a2, a0 3747; RV64IZHINX-NEXT: flt.h a1, a2, a1 3748; RV64IZHINX-NEXT: beqz a1, .LBB21_2 3749; RV64IZHINX-NEXT: # %bb.1: 3750; RV64IZHINX-NEXT: fcvt.w.h a1, a0 3751; RV64IZHINX-NEXT: fcvt.h.w a1, a1 3752; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 3753; RV64IZHINX-NEXT: .LBB21_2: 3754; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz 3755; RV64IZHINX-NEXT: feq.h a0, a0, a0 3756; RV64IZHINX-NEXT: seqz a0, a0 3757; RV64IZHINX-NEXT: addi a0, a0, -1 3758; RV64IZHINX-NEXT: and a0, a0, a1 3759; RV64IZHINX-NEXT: ret 3760; 3761; RV32IZFHMIN-LABEL: test_rint_si64: 3762; RV32IZFHMIN: # %bb.0: 3763; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3764; RV32IZFHMIN-NEXT: lui a0, 307200 3765; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 3766; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 3767; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 3768; RV32IZFHMIN-NEXT: beqz a0, .LBB21_2 3769; RV32IZFHMIN-NEXT: # %bb.1: 3770; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5 3771; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0 3772; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3773; RV32IZFHMIN-NEXT: .LBB21_2: 3774; RV32IZFHMIN-NEXT: addi sp, sp, -16 3775; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3776; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3777; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 3778; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3779; RV32IZFHMIN-NEXT: lui a0, 913408 3780; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 3781; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 3782; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 3783; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 3784; RV32IZFHMIN-NEXT: call __fixsfdi 3785; RV32IZFHMIN-NEXT: lui a3, 524288 3786; RV32IZFHMIN-NEXT: lui a2, 524288 3787; RV32IZFHMIN-NEXT: beqz s0, .LBB21_4 3788; RV32IZFHMIN-NEXT: # %bb.3: 3789; RV32IZFHMIN-NEXT: mv a2, a1 3790; RV32IZFHMIN-NEXT: .LBB21_4: 3791; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI21_0) 3792; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a1) 3793; RV32IZFHMIN-NEXT: flt.s a1, fa5, fs0 3794; RV32IZFHMIN-NEXT: beqz a1, .LBB21_6 3795; RV32IZFHMIN-NEXT: # %bb.5: 3796; RV32IZFHMIN-NEXT: addi a2, a3, -1 3797; RV32IZFHMIN-NEXT: .LBB21_6: 3798; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 3799; RV32IZFHMIN-NEXT: neg a4, s0 3800; RV32IZFHMIN-NEXT: neg a5, a1 3801; RV32IZFHMIN-NEXT: neg a3, a3 3802; RV32IZFHMIN-NEXT: and a0, a4, a0 3803; RV32IZFHMIN-NEXT: and a1, a3, a2 3804; RV32IZFHMIN-NEXT: or a0, a5, a0 3805; RV32IZFHMIN-NEXT: and a0, a3, a0 3806; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3807; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3808; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 3809; RV32IZFHMIN-NEXT: addi sp, sp, 16 3810; RV32IZFHMIN-NEXT: ret 3811; 3812; RV64IZFHMIN-LABEL: test_rint_si64: 3813; RV64IZFHMIN: # %bb.0: 3814; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3815; RV64IZFHMIN-NEXT: lui a0, 307200 3816; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 3817; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 3818; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 3819; RV64IZFHMIN-NEXT: beqz a0, .LBB21_2 3820; RV64IZFHMIN-NEXT: # %bb.1: 3821; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5 3822; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0 3823; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3824; RV64IZFHMIN-NEXT: .LBB21_2: 3825; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3826; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3827; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz 3828; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 3829; RV64IZFHMIN-NEXT: seqz a1, a1 3830; RV64IZFHMIN-NEXT: addi a1, a1, -1 3831; RV64IZFHMIN-NEXT: and a0, a1, a0 3832; RV64IZFHMIN-NEXT: ret 3833; 3834; RV32IZHINXMIN-LABEL: test_rint_si64: 3835; RV32IZHINXMIN: # %bb.0: 3836; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 3837; RV32IZHINXMIN-NEXT: lui a1, 307200 3838; RV32IZHINXMIN-NEXT: fabs.s a2, a0 3839; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 3840; RV32IZHINXMIN-NEXT: beqz a1, .LBB21_2 3841; RV32IZHINXMIN-NEXT: # %bb.1: 3842; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0 3843; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1 3844; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3845; RV32IZHINXMIN-NEXT: .LBB21_2: 3846; RV32IZHINXMIN-NEXT: addi sp, sp, -16 3847; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 3848; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 3849; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 3850; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 3851; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 3852; RV32IZHINXMIN-NEXT: lui a0, 913408 3853; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 3854; RV32IZHINXMIN-NEXT: mv a0, s0 3855; RV32IZHINXMIN-NEXT: call __fixsfdi 3856; RV32IZHINXMIN-NEXT: lui a3, 524288 3857; RV32IZHINXMIN-NEXT: lui a2, 524288 3858; RV32IZHINXMIN-NEXT: beqz s1, .LBB21_4 3859; RV32IZHINXMIN-NEXT: # %bb.3: 3860; RV32IZHINXMIN-NEXT: mv a2, a1 3861; RV32IZHINXMIN-NEXT: .LBB21_4: 3862; RV32IZHINXMIN-NEXT: lui a1, 389120 3863; RV32IZHINXMIN-NEXT: addi a1, a1, -1 3864; RV32IZHINXMIN-NEXT: flt.s a1, a1, s0 3865; RV32IZHINXMIN-NEXT: beqz a1, .LBB21_6 3866; RV32IZHINXMIN-NEXT: # %bb.5: 3867; RV32IZHINXMIN-NEXT: addi a2, a3, -1 3868; RV32IZHINXMIN-NEXT: .LBB21_6: 3869; RV32IZHINXMIN-NEXT: feq.s a3, s0, s0 3870; RV32IZHINXMIN-NEXT: neg a4, s1 3871; RV32IZHINXMIN-NEXT: neg a5, a1 3872; RV32IZHINXMIN-NEXT: neg a3, a3 3873; RV32IZHINXMIN-NEXT: and a0, a4, a0 3874; RV32IZHINXMIN-NEXT: and a1, a3, a2 3875; RV32IZHINXMIN-NEXT: or a0, a5, a0 3876; RV32IZHINXMIN-NEXT: and a0, a3, a0 3877; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 3878; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 3879; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 3880; RV32IZHINXMIN-NEXT: addi sp, sp, 16 3881; RV32IZHINXMIN-NEXT: ret 3882; 3883; RV64IZHINXMIN-LABEL: test_rint_si64: 3884; RV64IZHINXMIN: # %bb.0: 3885; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3886; RV64IZHINXMIN-NEXT: lui a1, 307200 3887; RV64IZHINXMIN-NEXT: fabs.s a2, a0 3888; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 3889; RV64IZHINXMIN-NEXT: beqz a1, .LBB21_2 3890; RV64IZHINXMIN-NEXT: # %bb.1: 3891; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0 3892; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1 3893; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 3894; RV64IZHINXMIN-NEXT: .LBB21_2: 3895; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 3896; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 3897; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz 3898; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 3899; RV64IZHINXMIN-NEXT: seqz a0, a0 3900; RV64IZHINXMIN-NEXT: addi a0, a0, -1 3901; RV64IZHINXMIN-NEXT: and a0, a0, a1 3902; RV64IZHINXMIN-NEXT: ret 3903 %a = call half @llvm.rint.f16(half %x) 3904 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a) 3905 ret i64 %b 3906} 3907 3908define signext i32 @test_rint_ui32(half %x) { 3909; CHECKIZFH-LABEL: test_rint_ui32: 3910; CHECKIZFH: # %bb.0: 3911; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0 3912; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 3913; CHECKIZFH-NEXT: seqz a1, a1 3914; CHECKIZFH-NEXT: addi a1, a1, -1 3915; CHECKIZFH-NEXT: and a0, a1, a0 3916; CHECKIZFH-NEXT: ret 3917; 3918; RV32IZHINX-LABEL: test_rint_ui32: 3919; RV32IZHINX: # %bb.0: 3920; RV32IZHINX-NEXT: li a1, 25 3921; RV32IZHINX-NEXT: slli a1, a1, 10 3922; RV32IZHINX-NEXT: fabs.h a2, a0 3923; RV32IZHINX-NEXT: flt.h a1, a2, a1 3924; RV32IZHINX-NEXT: beqz a1, .LBB22_2 3925; RV32IZHINX-NEXT: # %bb.1: 3926; RV32IZHINX-NEXT: fcvt.w.h a1, a0 3927; RV32IZHINX-NEXT: fcvt.h.w a1, a1 3928; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 3929; RV32IZHINX-NEXT: .LBB22_2: 3930; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 3931; RV32IZHINX-NEXT: feq.h a0, a0, a0 3932; RV32IZHINX-NEXT: seqz a0, a0 3933; RV32IZHINX-NEXT: addi a0, a0, -1 3934; RV32IZHINX-NEXT: and a0, a0, a1 3935; RV32IZHINX-NEXT: ret 3936; 3937; RV64IZHINX-LABEL: test_rint_ui32: 3938; RV64IZHINX: # %bb.0: 3939; RV64IZHINX-NEXT: li a1, 25 3940; RV64IZHINX-NEXT: slli a1, a1, 10 3941; RV64IZHINX-NEXT: fabs.h a2, a0 3942; RV64IZHINX-NEXT: flt.h a1, a2, a1 3943; RV64IZHINX-NEXT: beqz a1, .LBB22_2 3944; RV64IZHINX-NEXT: # %bb.1: 3945; RV64IZHINX-NEXT: fcvt.w.h a1, a0 3946; RV64IZHINX-NEXT: fcvt.h.w a1, a1 3947; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 3948; RV64IZHINX-NEXT: .LBB22_2: 3949; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz 3950; RV64IZHINX-NEXT: feq.h a0, a0, a0 3951; RV64IZHINX-NEXT: seqz a0, a0 3952; RV64IZHINX-NEXT: addiw a0, a0, -1 3953; RV64IZHINX-NEXT: and a0, a1, a0 3954; RV64IZHINX-NEXT: ret 3955; 3956; RV32IZFHMIN-LABEL: test_rint_ui32: 3957; RV32IZFHMIN: # %bb.0: 3958; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3959; RV32IZFHMIN-NEXT: lui a0, 307200 3960; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 3961; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 3962; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 3963; RV32IZFHMIN-NEXT: beqz a0, .LBB22_2 3964; RV32IZFHMIN-NEXT: # %bb.1: 3965; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5 3966; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0 3967; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3968; RV32IZFHMIN-NEXT: .LBB22_2: 3969; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3970; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3971; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 3972; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5 3973; RV32IZFHMIN-NEXT: seqz a1, a1 3974; RV32IZFHMIN-NEXT: addi a1, a1, -1 3975; RV32IZFHMIN-NEXT: and a0, a1, a0 3976; RV32IZFHMIN-NEXT: ret 3977; 3978; RV64IZFHMIN-LABEL: test_rint_ui32: 3979; RV64IZFHMIN: # %bb.0: 3980; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 3981; RV64IZFHMIN-NEXT: lui a0, 307200 3982; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 3983; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 3984; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 3985; RV64IZFHMIN-NEXT: beqz a0, .LBB22_2 3986; RV64IZFHMIN-NEXT: # %bb.1: 3987; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5 3988; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0 3989; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 3990; RV64IZFHMIN-NEXT: .LBB22_2: 3991; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 3992; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 3993; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 3994; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 3995; RV64IZFHMIN-NEXT: seqz a1, a1 3996; RV64IZFHMIN-NEXT: addiw a1, a1, -1 3997; RV64IZFHMIN-NEXT: and a0, a0, a1 3998; RV64IZFHMIN-NEXT: ret 3999; 4000; RV32IZHINXMIN-LABEL: test_rint_ui32: 4001; RV32IZHINXMIN: # %bb.0: 4002; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 4003; RV32IZHINXMIN-NEXT: lui a1, 307200 4004; RV32IZHINXMIN-NEXT: fabs.s a2, a0 4005; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 4006; RV32IZHINXMIN-NEXT: beqz a1, .LBB22_2 4007; RV32IZHINXMIN-NEXT: # %bb.1: 4008; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0 4009; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1 4010; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 4011; RV32IZHINXMIN-NEXT: .LBB22_2: 4012; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 4013; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 4014; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 4015; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0 4016; RV32IZHINXMIN-NEXT: seqz a0, a0 4017; RV32IZHINXMIN-NEXT: addi a0, a0, -1 4018; RV32IZHINXMIN-NEXT: and a0, a0, a1 4019; RV32IZHINXMIN-NEXT: ret 4020; 4021; RV64IZHINXMIN-LABEL: test_rint_ui32: 4022; RV64IZHINXMIN: # %bb.0: 4023; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 4024; RV64IZHINXMIN-NEXT: lui a1, 307200 4025; RV64IZHINXMIN-NEXT: fabs.s a2, a0 4026; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 4027; RV64IZHINXMIN-NEXT: beqz a1, .LBB22_2 4028; RV64IZHINXMIN-NEXT: # %bb.1: 4029; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0 4030; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1 4031; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 4032; RV64IZHINXMIN-NEXT: .LBB22_2: 4033; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 4034; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 4035; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz 4036; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 4037; RV64IZHINXMIN-NEXT: seqz a0, a0 4038; RV64IZHINXMIN-NEXT: addiw a0, a0, -1 4039; RV64IZHINXMIN-NEXT: and a0, a1, a0 4040; RV64IZHINXMIN-NEXT: ret 4041 %a = call half @llvm.rint.f16(half %x) 4042 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a) 4043 ret i32 %b 4044} 4045 4046define i64 @test_rint_ui64(half %x) nounwind { 4047; RV32IZFH-LABEL: test_rint_ui64: 4048; RV32IZFH: # %bb.0: 4049; RV32IZFH-NEXT: lui a0, %hi(.LCPI23_0) 4050; RV32IZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0) 4051; RV32IZFH-NEXT: fabs.h fa4, fa0 4052; RV32IZFH-NEXT: flt.h a0, fa4, fa5 4053; RV32IZFH-NEXT: beqz a0, .LBB23_2 4054; RV32IZFH-NEXT: # %bb.1: 4055; RV32IZFH-NEXT: fcvt.w.h a0, fa0 4056; RV32IZFH-NEXT: fcvt.h.w fa5, a0 4057; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 4058; RV32IZFH-NEXT: .LBB23_2: 4059; RV32IZFH-NEXT: addi sp, sp, -16 4060; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4061; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4062; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 4063; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 4064; RV32IZFH-NEXT: fmv.w.x fa5, zero 4065; RV32IZFH-NEXT: fle.s a0, fa5, fs0 4066; RV32IZFH-NEXT: neg s0, a0 4067; RV32IZFH-NEXT: fmv.s fa0, fs0 4068; RV32IZFH-NEXT: call __fixunssfdi 4069; RV32IZFH-NEXT: lui a2, %hi(.LCPI23_1) 4070; RV32IZFH-NEXT: flw fa5, %lo(.LCPI23_1)(a2) 4071; RV32IZFH-NEXT: and a0, s0, a0 4072; RV32IZFH-NEXT: and a1, s0, a1 4073; RV32IZFH-NEXT: flt.s a2, fa5, fs0 4074; RV32IZFH-NEXT: neg a2, a2 4075; RV32IZFH-NEXT: or a0, a2, a0 4076; RV32IZFH-NEXT: or a1, a2, a1 4077; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4078; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4079; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 4080; RV32IZFH-NEXT: addi sp, sp, 16 4081; RV32IZFH-NEXT: ret 4082; 4083; RV64IZFH-LABEL: test_rint_ui64: 4084; RV64IZFH: # %bb.0: 4085; RV64IZFH-NEXT: fcvt.lu.h a0, fa0 4086; RV64IZFH-NEXT: feq.h a1, fa0, fa0 4087; RV64IZFH-NEXT: seqz a1, a1 4088; RV64IZFH-NEXT: addi a1, a1, -1 4089; RV64IZFH-NEXT: and a0, a1, a0 4090; RV64IZFH-NEXT: ret 4091; 4092; RV32IZHINX-LABEL: test_rint_ui64: 4093; RV32IZHINX: # %bb.0: 4094; RV32IZHINX-NEXT: li a1, 25 4095; RV32IZHINX-NEXT: slli a1, a1, 10 4096; RV32IZHINX-NEXT: fabs.h a2, a0 4097; RV32IZHINX-NEXT: flt.h a1, a2, a1 4098; RV32IZHINX-NEXT: beqz a1, .LBB23_2 4099; RV32IZHINX-NEXT: # %bb.1: 4100; RV32IZHINX-NEXT: fcvt.w.h a1, a0 4101; RV32IZHINX-NEXT: fcvt.h.w a1, a1 4102; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 4103; RV32IZHINX-NEXT: .LBB23_2: 4104; RV32IZHINX-NEXT: addi sp, sp, -16 4105; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4106; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4107; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 4108; RV32IZHINX-NEXT: fcvt.s.h s0, a0 4109; RV32IZHINX-NEXT: fle.s a0, zero, s0 4110; RV32IZHINX-NEXT: neg s1, a0 4111; RV32IZHINX-NEXT: mv a0, s0 4112; RV32IZHINX-NEXT: call __fixunssfdi 4113; RV32IZHINX-NEXT: and a0, s1, a0 4114; RV32IZHINX-NEXT: lui a2, 391168 4115; RV32IZHINX-NEXT: and a1, s1, a1 4116; RV32IZHINX-NEXT: addi a2, a2, -1 4117; RV32IZHINX-NEXT: flt.s a2, a2, s0 4118; RV32IZHINX-NEXT: neg a2, a2 4119; RV32IZHINX-NEXT: or a0, a2, a0 4120; RV32IZHINX-NEXT: or a1, a2, a1 4121; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4122; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4123; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 4124; RV32IZHINX-NEXT: addi sp, sp, 16 4125; RV32IZHINX-NEXT: ret 4126; 4127; RV64IZHINX-LABEL: test_rint_ui64: 4128; RV64IZHINX: # %bb.0: 4129; RV64IZHINX-NEXT: li a1, 25 4130; RV64IZHINX-NEXT: slli a1, a1, 10 4131; RV64IZHINX-NEXT: fabs.h a2, a0 4132; RV64IZHINX-NEXT: flt.h a1, a2, a1 4133; RV64IZHINX-NEXT: beqz a1, .LBB23_2 4134; RV64IZHINX-NEXT: # %bb.1: 4135; RV64IZHINX-NEXT: fcvt.w.h a1, a0 4136; RV64IZHINX-NEXT: fcvt.h.w a1, a1 4137; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0 4138; RV64IZHINX-NEXT: .LBB23_2: 4139; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz 4140; RV64IZHINX-NEXT: feq.h a0, a0, a0 4141; RV64IZHINX-NEXT: seqz a0, a0 4142; RV64IZHINX-NEXT: addi a0, a0, -1 4143; RV64IZHINX-NEXT: and a0, a0, a1 4144; RV64IZHINX-NEXT: ret 4145; 4146; RV32IZFHMIN-LABEL: test_rint_ui64: 4147; RV32IZFHMIN: # %bb.0: 4148; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 4149; RV32IZFHMIN-NEXT: lui a0, 307200 4150; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0 4151; RV32IZFHMIN-NEXT: fabs.s fa3, fa5 4152; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4 4153; RV32IZFHMIN-NEXT: beqz a0, .LBB23_2 4154; RV32IZFHMIN-NEXT: # %bb.1: 4155; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5 4156; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0 4157; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 4158; RV32IZFHMIN-NEXT: .LBB23_2: 4159; RV32IZFHMIN-NEXT: addi sp, sp, -16 4160; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4161; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4162; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 4163; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 4164; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 4165; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero 4166; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 4167; RV32IZFHMIN-NEXT: neg s0, a0 4168; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 4169; RV32IZFHMIN-NEXT: call __fixunssfdi 4170; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI23_0) 4171; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI23_0)(a2) 4172; RV32IZFHMIN-NEXT: and a0, s0, a0 4173; RV32IZFHMIN-NEXT: and a1, s0, a1 4174; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 4175; RV32IZFHMIN-NEXT: neg a2, a2 4176; RV32IZFHMIN-NEXT: or a0, a2, a0 4177; RV32IZFHMIN-NEXT: or a1, a2, a1 4178; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4179; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4180; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 4181; RV32IZFHMIN-NEXT: addi sp, sp, 16 4182; RV32IZFHMIN-NEXT: ret 4183; 4184; RV64IZFHMIN-LABEL: test_rint_ui64: 4185; RV64IZFHMIN: # %bb.0: 4186; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 4187; RV64IZFHMIN-NEXT: lui a0, 307200 4188; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 4189; RV64IZFHMIN-NEXT: fabs.s fa3, fa5 4190; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4 4191; RV64IZFHMIN-NEXT: beqz a0, .LBB23_2 4192; RV64IZFHMIN-NEXT: # %bb.1: 4193; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5 4194; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0 4195; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 4196; RV64IZFHMIN-NEXT: .LBB23_2: 4197; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 4198; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 4199; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 4200; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5 4201; RV64IZFHMIN-NEXT: seqz a1, a1 4202; RV64IZFHMIN-NEXT: addi a1, a1, -1 4203; RV64IZFHMIN-NEXT: and a0, a1, a0 4204; RV64IZFHMIN-NEXT: ret 4205; 4206; RV32IZHINXMIN-LABEL: test_rint_ui64: 4207; RV32IZHINXMIN: # %bb.0: 4208; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 4209; RV32IZHINXMIN-NEXT: lui a1, 307200 4210; RV32IZHINXMIN-NEXT: fabs.s a2, a0 4211; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1 4212; RV32IZHINXMIN-NEXT: beqz a1, .LBB23_2 4213; RV32IZHINXMIN-NEXT: # %bb.1: 4214; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0 4215; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1 4216; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 4217; RV32IZHINXMIN-NEXT: .LBB23_2: 4218; RV32IZHINXMIN-NEXT: addi sp, sp, -16 4219; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 4220; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 4221; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 4222; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 4223; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 4224; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 4225; RV32IZHINXMIN-NEXT: neg s1, a0 4226; RV32IZHINXMIN-NEXT: mv a0, s0 4227; RV32IZHINXMIN-NEXT: call __fixunssfdi 4228; RV32IZHINXMIN-NEXT: and a0, s1, a0 4229; RV32IZHINXMIN-NEXT: lui a2, 391168 4230; RV32IZHINXMIN-NEXT: and a1, s1, a1 4231; RV32IZHINXMIN-NEXT: addi a2, a2, -1 4232; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 4233; RV32IZHINXMIN-NEXT: neg a2, a2 4234; RV32IZHINXMIN-NEXT: or a0, a2, a0 4235; RV32IZHINXMIN-NEXT: or a1, a2, a1 4236; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 4237; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 4238; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 4239; RV32IZHINXMIN-NEXT: addi sp, sp, 16 4240; RV32IZHINXMIN-NEXT: ret 4241; 4242; RV64IZHINXMIN-LABEL: test_rint_ui64: 4243; RV64IZHINXMIN: # %bb.0: 4244; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 4245; RV64IZHINXMIN-NEXT: lui a1, 307200 4246; RV64IZHINXMIN-NEXT: fabs.s a2, a0 4247; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1 4248; RV64IZHINXMIN-NEXT: beqz a1, .LBB23_2 4249; RV64IZHINXMIN-NEXT: # %bb.1: 4250; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0 4251; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1 4252; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0 4253; RV64IZHINXMIN-NEXT: .LBB23_2: 4254; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 4255; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 4256; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz 4257; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0 4258; RV64IZHINXMIN-NEXT: seqz a0, a0 4259; RV64IZHINXMIN-NEXT: addi a0, a0, -1 4260; RV64IZHINXMIN-NEXT: and a0, a0, a1 4261; RV64IZHINXMIN-NEXT: ret 4262 %a = call half @llvm.rint.f16(half %x) 4263 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a) 4264 ret i64 %b 4265} 4266 4267declare half @llvm.floor.f16(half) 4268declare half @llvm.ceil.f16(half) 4269declare half @llvm.trunc.f16(half) 4270declare half @llvm.round.f16(half) 4271declare half @llvm.roundeven.f16(half) 4272declare half @llvm.rint.f16(half) 4273declare i32 @llvm.fptosi.sat.i32.f16(half) 4274declare i64 @llvm.fptosi.sat.i64.f16(half) 4275declare i32 @llvm.fptoui.sat.i32.f16(half) 4276declare i64 @llvm.fptoui.sat.i64.f16(half) 4277