xref: /llvm-project/llvm/test/CodeGen/RISCV/half-isnan.ll (revision 773b0aaa49170a97b4de7968c4b6dbc7673aba23)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
7; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINX %s
8; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
9; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINX %s
10; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
11; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
12; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
13; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
14; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
15; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN %s
16; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
17; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN %s
18
19define zeroext i1 @half_is_nan(half %a) nounwind {
20; CHECK-LABEL: half_is_nan:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    feq.h a0, fa0, fa0
23; CHECK-NEXT:    xori a0, a0, 1
24; CHECK-NEXT:    ret
25;
26; CHECKIZHINX-LABEL: half_is_nan:
27; CHECKIZHINX:       # %bb.0:
28; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
29; CHECKIZHINX-NEXT:    xori a0, a0, 1
30; CHECKIZHINX-NEXT:    ret
31;
32; CHECKIZFHMIN-LABEL: half_is_nan:
33; CHECKIZFHMIN:       # %bb.0:
34; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
35; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa5
36; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
37; CHECKIZFHMIN-NEXT:    ret
38;
39; CHECKIZHINXMIN-LABEL: half_is_nan:
40; CHECKIZHINXMIN:       # %bb.0:
41; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
42; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
43; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
44; CHECKIZHINXMIN-NEXT:    ret
45  %1 = fcmp uno half %a, 0.000000e+00
46  ret i1 %1
47}
48
49define zeroext i1 @half_not_nan(half %a) nounwind {
50; CHECK-LABEL: half_not_nan:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    feq.h a0, fa0, fa0
53; CHECK-NEXT:    ret
54;
55; CHECKIZHINX-LABEL: half_not_nan:
56; CHECKIZHINX:       # %bb.0:
57; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
58; CHECKIZHINX-NEXT:    ret
59;
60; CHECKIZFHMIN-LABEL: half_not_nan:
61; CHECKIZFHMIN:       # %bb.0:
62; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
63; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa5
64; CHECKIZFHMIN-NEXT:    ret
65;
66; CHECKIZHINXMIN-LABEL: half_not_nan:
67; CHECKIZHINXMIN:       # %bb.0:
68; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
69; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
70; CHECKIZHINXMIN-NEXT:    ret
71  %1 = fcmp ord half %a, 0.000000e+00
72  ret i1 %1
73}
74