1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ 3; RUN: -target-abi ilp32f < %s \ 4; RUN: | FileCheck -check-prefix=RV32IZFH %s 5; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ 6; RUN: -target-abi lp64f < %s \ 7; RUN: | FileCheck -check-prefix=RV64IZFH %s 8; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \ 9; RUN: -target-abi ilp32 < %s \ 10; RUN: | FileCheck -check-prefix=RV32IZHINX %s 11; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \ 12; RUN: -target-abi lp64 < %s \ 13; RUN: | FileCheck -check-prefix=RV64IZHINX %s 14; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ 15; RUN: -target-abi ilp32f < %s \ 16; RUN: | FileCheck -check-prefix=RV32IZFHMIN %s 17; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ 18; RUN: -target-abi lp64f < %s \ 19; RUN: | FileCheck -check-prefix=RV64IZFHMIN %s 20; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \ 21; RUN: -target-abi ilp32 < %s \ 22; RUN: | FileCheck -check-prefix=RV32IZHINXMIN %s 23; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \ 24; RUN: -target-abi lp64 < %s \ 25; RUN: | FileCheck -check-prefix=RV64IZHINXMIN %s 26 27define half @frem_f16(half %a, half %b) nounwind { 28; RV32IZFH-LABEL: frem_f16: 29; RV32IZFH: # %bb.0: 30; RV32IZFH-NEXT: addi sp, sp, -16 31; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 32; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 33; RV32IZFH-NEXT: fcvt.s.h fa1, fa1 34; RV32IZFH-NEXT: call fmodf 35; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 36; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 37; RV32IZFH-NEXT: addi sp, sp, 16 38; RV32IZFH-NEXT: ret 39; 40; RV64IZFH-LABEL: frem_f16: 41; RV64IZFH: # %bb.0: 42; RV64IZFH-NEXT: addi sp, sp, -16 43; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 44; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 45; RV64IZFH-NEXT: fcvt.s.h fa1, fa1 46; RV64IZFH-NEXT: call fmodf 47; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 48; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 49; RV64IZFH-NEXT: addi sp, sp, 16 50; RV64IZFH-NEXT: ret 51; 52; RV32IZHINX-LABEL: frem_f16: 53; RV32IZHINX: # %bb.0: 54; RV32IZHINX-NEXT: addi sp, sp, -16 55; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 56; RV32IZHINX-NEXT: fcvt.s.h a0, a0 57; RV32IZHINX-NEXT: fcvt.s.h a1, a1 58; RV32IZHINX-NEXT: call fmodf 59; RV32IZHINX-NEXT: fcvt.h.s a0, a0 60; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 61; RV32IZHINX-NEXT: addi sp, sp, 16 62; RV32IZHINX-NEXT: ret 63; 64; RV64IZHINX-LABEL: frem_f16: 65; RV64IZHINX: # %bb.0: 66; RV64IZHINX-NEXT: addi sp, sp, -16 67; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 68; RV64IZHINX-NEXT: fcvt.s.h a0, a0 69; RV64IZHINX-NEXT: fcvt.s.h a1, a1 70; RV64IZHINX-NEXT: call fmodf 71; RV64IZHINX-NEXT: fcvt.h.s a0, a0 72; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 73; RV64IZHINX-NEXT: addi sp, sp, 16 74; RV64IZHINX-NEXT: ret 75; 76; RV32IZFHMIN-LABEL: frem_f16: 77; RV32IZFHMIN: # %bb.0: 78; RV32IZFHMIN-NEXT: addi sp, sp, -16 79; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 80; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0 81; RV32IZFHMIN-NEXT: fcvt.s.h fa1, fa1 82; RV32IZFHMIN-NEXT: call fmodf 83; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0 84; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 85; RV32IZFHMIN-NEXT: addi sp, sp, 16 86; RV32IZFHMIN-NEXT: ret 87; 88; RV64IZFHMIN-LABEL: frem_f16: 89; RV64IZFHMIN: # %bb.0: 90; RV64IZFHMIN-NEXT: addi sp, sp, -16 91; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 92; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0 93; RV64IZFHMIN-NEXT: fcvt.s.h fa1, fa1 94; RV64IZFHMIN-NEXT: call fmodf 95; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0 96; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 97; RV64IZFHMIN-NEXT: addi sp, sp, 16 98; RV64IZFHMIN-NEXT: ret 99; 100; RV32IZHINXMIN-LABEL: frem_f16: 101; RV32IZHINXMIN: # %bb.0: 102; RV32IZHINXMIN-NEXT: addi sp, sp, -16 103; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 104; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 105; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 106; RV32IZHINXMIN-NEXT: call fmodf 107; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 108; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 109; RV32IZHINXMIN-NEXT: addi sp, sp, 16 110; RV32IZHINXMIN-NEXT: ret 111; 112; RV64IZHINXMIN-LABEL: frem_f16: 113; RV64IZHINXMIN: # %bb.0: 114; RV64IZHINXMIN-NEXT: addi sp, sp, -16 115; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 116; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 117; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 118; RV64IZHINXMIN-NEXT: call fmodf 119; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 120; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 121; RV64IZHINXMIN-NEXT: addi sp, sp, 16 122; RV64IZHINXMIN-NEXT: ret 123 %1 = frem half %a, %b 124 ret half %1 125} 126