1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ 3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s 4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ 5; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s 6; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \ 7; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \ 9; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s 10; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ 11; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=RV32I %s 12; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ 13; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=RV64I %s 14; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ 15; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s 16; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ 17; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s 18; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ 19; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s 20; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ 21; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s 22; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \ 23; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s 24; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \ 25; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s 26 27define i32 @fcmp_false(half %a, half %b) nounwind { 28; CHECKIZFH-LABEL: fcmp_false: 29; CHECKIZFH: # %bb.0: 30; CHECKIZFH-NEXT: li a0, 0 31; CHECKIZFH-NEXT: ret 32; 33; CHECKIZHINX-LABEL: fcmp_false: 34; CHECKIZHINX: # %bb.0: 35; CHECKIZHINX-NEXT: li a0, 0 36; CHECKIZHINX-NEXT: ret 37; 38; RV32I-LABEL: fcmp_false: 39; RV32I: # %bb.0: 40; RV32I-NEXT: li a0, 0 41; RV32I-NEXT: ret 42; 43; RV64I-LABEL: fcmp_false: 44; RV64I: # %bb.0: 45; RV64I-NEXT: li a0, 0 46; RV64I-NEXT: ret 47; 48; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_false: 49; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 50; CHECKIZFHMIN-ILP32F-LP64F-NEXT: li a0, 0 51; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 52; 53; CHECKIZFHMIN-LABEL: fcmp_false: 54; CHECKIZFHMIN: # %bb.0: 55; CHECKIZFHMIN-NEXT: li a0, 0 56; CHECKIZFHMIN-NEXT: ret 57; 58; CHECKIZHINXMIN-LABEL: fcmp_false: 59; CHECKIZHINXMIN: # %bb.0: 60; CHECKIZHINXMIN-NEXT: li a0, 0 61; CHECKIZHINXMIN-NEXT: ret 62 %1 = fcmp false half %a, %b 63 %2 = zext i1 %1 to i32 64 ret i32 %2 65} 66 67define i32 @fcmp_oeq(half %a, half %b) nounwind { 68; CHECKIZFH-LABEL: fcmp_oeq: 69; CHECKIZFH: # %bb.0: 70; CHECKIZFH-NEXT: feq.h a0, fa0, fa1 71; CHECKIZFH-NEXT: ret 72; 73; CHECKIZHINX-LABEL: fcmp_oeq: 74; CHECKIZHINX: # %bb.0: 75; CHECKIZHINX-NEXT: feq.h a0, a0, a1 76; CHECKIZHINX-NEXT: ret 77; 78; RV32I-LABEL: fcmp_oeq: 79; RV32I: # %bb.0: 80; RV32I-NEXT: fmv.h.x fa5, a1 81; RV32I-NEXT: fmv.h.x fa4, a0 82; RV32I-NEXT: feq.h a0, fa4, fa5 83; RV32I-NEXT: ret 84; 85; RV64I-LABEL: fcmp_oeq: 86; RV64I: # %bb.0: 87; RV64I-NEXT: fmv.h.x fa5, a1 88; RV64I-NEXT: fmv.h.x fa4, a0 89; RV64I-NEXT: feq.h a0, fa4, fa5 90; RV64I-NEXT: ret 91; 92; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_oeq: 93; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 94; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 95; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 96; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa4, fa5 97; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 98; 99; CHECKIZFHMIN-LABEL: fcmp_oeq: 100; CHECKIZFHMIN: # %bb.0: 101; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 102; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 103; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 104; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 105; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4 106; CHECKIZFHMIN-NEXT: ret 107; 108; CHECKIZHINXMIN-LABEL: fcmp_oeq: 109; CHECKIZHINXMIN: # %bb.0: 110; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 111; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 112; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a1 113; CHECKIZHINXMIN-NEXT: ret 114 %1 = fcmp oeq half %a, %b 115 %2 = zext i1 %1 to i32 116 ret i32 %2 117} 118 119define i32 @fcmp_ogt(half %a, half %b) nounwind { 120; CHECKIZFH-LABEL: fcmp_ogt: 121; CHECKIZFH: # %bb.0: 122; CHECKIZFH-NEXT: flt.h a0, fa1, fa0 123; CHECKIZFH-NEXT: ret 124; 125; CHECKIZHINX-LABEL: fcmp_ogt: 126; CHECKIZHINX: # %bb.0: 127; CHECKIZHINX-NEXT: flt.h a0, a1, a0 128; CHECKIZHINX-NEXT: ret 129; 130; RV32I-LABEL: fcmp_ogt: 131; RV32I: # %bb.0: 132; RV32I-NEXT: fmv.h.x fa5, a0 133; RV32I-NEXT: fmv.h.x fa4, a1 134; RV32I-NEXT: flt.h a0, fa4, fa5 135; RV32I-NEXT: ret 136; 137; RV64I-LABEL: fcmp_ogt: 138; RV64I: # %bb.0: 139; RV64I-NEXT: fmv.h.x fa5, a0 140; RV64I-NEXT: fmv.h.x fa4, a1 141; RV64I-NEXT: flt.h a0, fa4, fa5 142; RV64I-NEXT: ret 143; 144; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ogt: 145; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 146; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 147; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 148; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 149; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 150; 151; CHECKIZFHMIN-LABEL: fcmp_ogt: 152; CHECKIZFHMIN: # %bb.0: 153; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 154; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 155; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 156; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 157; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 158; CHECKIZFHMIN-NEXT: ret 159; 160; CHECKIZHINXMIN-LABEL: fcmp_ogt: 161; CHECKIZHINXMIN: # %bb.0: 162; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 163; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 164; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 165; CHECKIZHINXMIN-NEXT: ret 166 %1 = fcmp ogt half %a, %b 167 %2 = zext i1 %1 to i32 168 ret i32 %2 169} 170 171define i32 @fcmp_oge(half %a, half %b) nounwind { 172; CHECKIZFH-LABEL: fcmp_oge: 173; CHECKIZFH: # %bb.0: 174; CHECKIZFH-NEXT: fle.h a0, fa1, fa0 175; CHECKIZFH-NEXT: ret 176; 177; CHECKIZHINX-LABEL: fcmp_oge: 178; CHECKIZHINX: # %bb.0: 179; CHECKIZHINX-NEXT: fle.h a0, a1, a0 180; CHECKIZHINX-NEXT: ret 181; 182; RV32I-LABEL: fcmp_oge: 183; RV32I: # %bb.0: 184; RV32I-NEXT: fmv.h.x fa5, a0 185; RV32I-NEXT: fmv.h.x fa4, a1 186; RV32I-NEXT: fle.h a0, fa4, fa5 187; RV32I-NEXT: ret 188; 189; RV64I-LABEL: fcmp_oge: 190; RV64I: # %bb.0: 191; RV64I-NEXT: fmv.h.x fa5, a0 192; RV64I-NEXT: fmv.h.x fa4, a1 193; RV64I-NEXT: fle.h a0, fa4, fa5 194; RV64I-NEXT: ret 195; 196; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_oge: 197; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 198; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 199; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 200; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 201; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 202; 203; CHECKIZFHMIN-LABEL: fcmp_oge: 204; CHECKIZFHMIN: # %bb.0: 205; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 206; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 207; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 208; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 209; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 210; CHECKIZFHMIN-NEXT: ret 211; 212; CHECKIZHINXMIN-LABEL: fcmp_oge: 213; CHECKIZHINXMIN: # %bb.0: 214; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 215; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 216; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a0 217; CHECKIZHINXMIN-NEXT: ret 218 %1 = fcmp oge half %a, %b 219 %2 = zext i1 %1 to i32 220 ret i32 %2 221} 222 223define i32 @fcmp_olt(half %a, half %b) nounwind { 224; CHECKIZFH-LABEL: fcmp_olt: 225; CHECKIZFH: # %bb.0: 226; CHECKIZFH-NEXT: flt.h a0, fa0, fa1 227; CHECKIZFH-NEXT: ret 228; 229; CHECKIZHINX-LABEL: fcmp_olt: 230; CHECKIZHINX: # %bb.0: 231; CHECKIZHINX-NEXT: flt.h a0, a0, a1 232; CHECKIZHINX-NEXT: ret 233; 234; RV32I-LABEL: fcmp_olt: 235; RV32I: # %bb.0: 236; RV32I-NEXT: fmv.h.x fa5, a1 237; RV32I-NEXT: fmv.h.x fa4, a0 238; RV32I-NEXT: flt.h a0, fa4, fa5 239; RV32I-NEXT: ret 240; 241; RV64I-LABEL: fcmp_olt: 242; RV64I: # %bb.0: 243; RV64I-NEXT: fmv.h.x fa5, a1 244; RV64I-NEXT: fmv.h.x fa4, a0 245; RV64I-NEXT: flt.h a0, fa4, fa5 246; RV64I-NEXT: ret 247; 248; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_olt: 249; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 250; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 251; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 252; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 253; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 254; 255; CHECKIZFHMIN-LABEL: fcmp_olt: 256; CHECKIZFHMIN: # %bb.0: 257; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 258; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 259; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 260; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 261; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 262; CHECKIZFHMIN-NEXT: ret 263; 264; CHECKIZHINXMIN-LABEL: fcmp_olt: 265; CHECKIZHINXMIN: # %bb.0: 266; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 267; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 268; CHECKIZHINXMIN-NEXT: flt.s a0, a0, a1 269; CHECKIZHINXMIN-NEXT: ret 270 %1 = fcmp olt half %a, %b 271 %2 = zext i1 %1 to i32 272 ret i32 %2 273} 274 275define i32 @fcmp_ole(half %a, half %b) nounwind { 276; CHECKIZFH-LABEL: fcmp_ole: 277; CHECKIZFH: # %bb.0: 278; CHECKIZFH-NEXT: fle.h a0, fa0, fa1 279; CHECKIZFH-NEXT: ret 280; 281; CHECKIZHINX-LABEL: fcmp_ole: 282; CHECKIZHINX: # %bb.0: 283; CHECKIZHINX-NEXT: fle.h a0, a0, a1 284; CHECKIZHINX-NEXT: ret 285; 286; RV32I-LABEL: fcmp_ole: 287; RV32I: # %bb.0: 288; RV32I-NEXT: fmv.h.x fa5, a1 289; RV32I-NEXT: fmv.h.x fa4, a0 290; RV32I-NEXT: fle.h a0, fa4, fa5 291; RV32I-NEXT: ret 292; 293; RV64I-LABEL: fcmp_ole: 294; RV64I: # %bb.0: 295; RV64I-NEXT: fmv.h.x fa5, a1 296; RV64I-NEXT: fmv.h.x fa4, a0 297; RV64I-NEXT: fle.h a0, fa4, fa5 298; RV64I-NEXT: ret 299; 300; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ole: 301; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 302; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 303; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 304; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 305; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 306; 307; CHECKIZFHMIN-LABEL: fcmp_ole: 308; CHECKIZFHMIN: # %bb.0: 309; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 310; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 311; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 312; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 313; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 314; CHECKIZFHMIN-NEXT: ret 315; 316; CHECKIZHINXMIN-LABEL: fcmp_ole: 317; CHECKIZHINXMIN: # %bb.0: 318; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 319; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 320; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1 321; CHECKIZHINXMIN-NEXT: ret 322 %1 = fcmp ole half %a, %b 323 %2 = zext i1 %1 to i32 324 ret i32 %2 325} 326 327define i32 @fcmp_one(half %a, half %b) nounwind { 328; CHECKIZFH-LABEL: fcmp_one: 329; CHECKIZFH: # %bb.0: 330; CHECKIZFH-NEXT: flt.h a0, fa0, fa1 331; CHECKIZFH-NEXT: flt.h a1, fa1, fa0 332; CHECKIZFH-NEXT: or a0, a1, a0 333; CHECKIZFH-NEXT: ret 334; 335; CHECKIZHINX-LABEL: fcmp_one: 336; CHECKIZHINX: # %bb.0: 337; CHECKIZHINX-NEXT: flt.h a2, a0, a1 338; CHECKIZHINX-NEXT: flt.h a0, a1, a0 339; CHECKIZHINX-NEXT: or a0, a0, a2 340; CHECKIZHINX-NEXT: ret 341; 342; RV32I-LABEL: fcmp_one: 343; RV32I: # %bb.0: 344; RV32I-NEXT: fmv.h.x fa5, a1 345; RV32I-NEXT: fmv.h.x fa4, a0 346; RV32I-NEXT: flt.h a0, fa4, fa5 347; RV32I-NEXT: flt.h a1, fa5, fa4 348; RV32I-NEXT: or a0, a1, a0 349; RV32I-NEXT: ret 350; 351; RV64I-LABEL: fcmp_one: 352; RV64I: # %bb.0: 353; RV64I-NEXT: fmv.h.x fa5, a1 354; RV64I-NEXT: fmv.h.x fa4, a0 355; RV64I-NEXT: flt.h a0, fa4, fa5 356; RV64I-NEXT: flt.h a1, fa5, fa4 357; RV64I-NEXT: or a0, a1, a0 358; RV64I-NEXT: ret 359; 360; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_one: 361; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 362; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 363; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 364; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 365; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a1, fa5, fa4 366; CHECKIZFHMIN-ILP32F-LP64F-NEXT: or a0, a1, a0 367; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 368; 369; CHECKIZFHMIN-LABEL: fcmp_one: 370; CHECKIZFHMIN: # %bb.0: 371; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 372; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 373; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 374; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 375; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 376; CHECKIZFHMIN-NEXT: flt.s a1, fa4, fa5 377; CHECKIZFHMIN-NEXT: or a0, a1, a0 378; CHECKIZFHMIN-NEXT: ret 379; 380; CHECKIZHINXMIN-LABEL: fcmp_one: 381; CHECKIZHINXMIN: # %bb.0: 382; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 383; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 384; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1 385; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 386; CHECKIZHINXMIN-NEXT: or a0, a0, a2 387; CHECKIZHINXMIN-NEXT: ret 388 %1 = fcmp one half %a, %b 389 %2 = zext i1 %1 to i32 390 ret i32 %2 391} 392 393define i32 @fcmp_ord(half %a, half %b) nounwind { 394; CHECKIZFH-LABEL: fcmp_ord: 395; CHECKIZFH: # %bb.0: 396; CHECKIZFH-NEXT: feq.h a0, fa1, fa1 397; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 398; CHECKIZFH-NEXT: and a0, a1, a0 399; CHECKIZFH-NEXT: ret 400; 401; CHECKIZHINX-LABEL: fcmp_ord: 402; CHECKIZHINX: # %bb.0: 403; CHECKIZHINX-NEXT: feq.h a1, a1, a1 404; CHECKIZHINX-NEXT: feq.h a0, a0, a0 405; CHECKIZHINX-NEXT: and a0, a0, a1 406; CHECKIZHINX-NEXT: ret 407; 408; RV32I-LABEL: fcmp_ord: 409; RV32I: # %bb.0: 410; RV32I-NEXT: fmv.h.x fa5, a0 411; RV32I-NEXT: fmv.h.x fa4, a1 412; RV32I-NEXT: feq.h a0, fa4, fa4 413; RV32I-NEXT: feq.h a1, fa5, fa5 414; RV32I-NEXT: and a0, a1, a0 415; RV32I-NEXT: ret 416; 417; RV64I-LABEL: fcmp_ord: 418; RV64I: # %bb.0: 419; RV64I-NEXT: fmv.h.x fa5, a0 420; RV64I-NEXT: fmv.h.x fa4, a1 421; RV64I-NEXT: feq.h a0, fa4, fa4 422; RV64I-NEXT: feq.h a1, fa5, fa5 423; RV64I-NEXT: and a0, a1, a0 424; RV64I-NEXT: ret 425; 426; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ord: 427; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 428; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 429; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 430; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa5, fa5 431; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a1, fa4, fa4 432; CHECKIZFHMIN-ILP32F-LP64F-NEXT: and a0, a1, a0 433; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 434; 435; CHECKIZFHMIN-LABEL: fcmp_ord: 436; CHECKIZFHMIN: # %bb.0: 437; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 438; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 439; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 440; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 441; CHECKIZFHMIN-NEXT: feq.s a0, fa4, fa4 442; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 443; CHECKIZFHMIN-NEXT: and a0, a1, a0 444; CHECKIZFHMIN-NEXT: ret 445; 446; CHECKIZHINXMIN-LABEL: fcmp_ord: 447; CHECKIZHINXMIN: # %bb.0: 448; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 449; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 450; CHECKIZHINXMIN-NEXT: feq.s a1, a1, a1 451; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 452; CHECKIZHINXMIN-NEXT: and a0, a0, a1 453; CHECKIZHINXMIN-NEXT: ret 454 %1 = fcmp ord half %a, %b 455 %2 = zext i1 %1 to i32 456 ret i32 %2 457} 458 459define i32 @fcmp_ueq(half %a, half %b) nounwind { 460; CHECKIZFH-LABEL: fcmp_ueq: 461; CHECKIZFH: # %bb.0: 462; CHECKIZFH-NEXT: flt.h a0, fa0, fa1 463; CHECKIZFH-NEXT: flt.h a1, fa1, fa0 464; CHECKIZFH-NEXT: or a0, a1, a0 465; CHECKIZFH-NEXT: xori a0, a0, 1 466; CHECKIZFH-NEXT: ret 467; 468; CHECKIZHINX-LABEL: fcmp_ueq: 469; CHECKIZHINX: # %bb.0: 470; CHECKIZHINX-NEXT: flt.h a2, a0, a1 471; CHECKIZHINX-NEXT: flt.h a0, a1, a0 472; CHECKIZHINX-NEXT: or a0, a0, a2 473; CHECKIZHINX-NEXT: xori a0, a0, 1 474; CHECKIZHINX-NEXT: ret 475; 476; RV32I-LABEL: fcmp_ueq: 477; RV32I: # %bb.0: 478; RV32I-NEXT: fmv.h.x fa5, a1 479; RV32I-NEXT: fmv.h.x fa4, a0 480; RV32I-NEXT: flt.h a0, fa4, fa5 481; RV32I-NEXT: flt.h a1, fa5, fa4 482; RV32I-NEXT: or a0, a1, a0 483; RV32I-NEXT: xori a0, a0, 1 484; RV32I-NEXT: ret 485; 486; RV64I-LABEL: fcmp_ueq: 487; RV64I: # %bb.0: 488; RV64I-NEXT: fmv.h.x fa5, a1 489; RV64I-NEXT: fmv.h.x fa4, a0 490; RV64I-NEXT: flt.h a0, fa4, fa5 491; RV64I-NEXT: flt.h a1, fa5, fa4 492; RV64I-NEXT: or a0, a1, a0 493; RV64I-NEXT: xori a0, a0, 1 494; RV64I-NEXT: ret 495; 496; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ueq: 497; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 498; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 499; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 500; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 501; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a1, fa5, fa4 502; CHECKIZFHMIN-ILP32F-LP64F-NEXT: or a0, a1, a0 503; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 504; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 505; 506; CHECKIZFHMIN-LABEL: fcmp_ueq: 507; CHECKIZFHMIN: # %bb.0: 508; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 509; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 510; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 511; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 512; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 513; CHECKIZFHMIN-NEXT: flt.s a1, fa4, fa5 514; CHECKIZFHMIN-NEXT: or a0, a1, a0 515; CHECKIZFHMIN-NEXT: xori a0, a0, 1 516; CHECKIZFHMIN-NEXT: ret 517; 518; CHECKIZHINXMIN-LABEL: fcmp_ueq: 519; CHECKIZHINXMIN: # %bb.0: 520; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 521; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 522; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1 523; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 524; CHECKIZHINXMIN-NEXT: or a0, a0, a2 525; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 526; CHECKIZHINXMIN-NEXT: ret 527 %1 = fcmp ueq half %a, %b 528 %2 = zext i1 %1 to i32 529 ret i32 %2 530} 531 532define i32 @fcmp_ugt(half %a, half %b) nounwind { 533; CHECKIZFH-LABEL: fcmp_ugt: 534; CHECKIZFH: # %bb.0: 535; CHECKIZFH-NEXT: fle.h a0, fa0, fa1 536; CHECKIZFH-NEXT: xori a0, a0, 1 537; CHECKIZFH-NEXT: ret 538; 539; CHECKIZHINX-LABEL: fcmp_ugt: 540; CHECKIZHINX: # %bb.0: 541; CHECKIZHINX-NEXT: fle.h a0, a0, a1 542; CHECKIZHINX-NEXT: xori a0, a0, 1 543; CHECKIZHINX-NEXT: ret 544; 545; RV32I-LABEL: fcmp_ugt: 546; RV32I: # %bb.0: 547; RV32I-NEXT: fmv.h.x fa5, a1 548; RV32I-NEXT: fmv.h.x fa4, a0 549; RV32I-NEXT: fle.h a0, fa4, fa5 550; RV32I-NEXT: xori a0, a0, 1 551; RV32I-NEXT: ret 552; 553; RV64I-LABEL: fcmp_ugt: 554; RV64I: # %bb.0: 555; RV64I-NEXT: fmv.h.x fa5, a1 556; RV64I-NEXT: fmv.h.x fa4, a0 557; RV64I-NEXT: fle.h a0, fa4, fa5 558; RV64I-NEXT: xori a0, a0, 1 559; RV64I-NEXT: ret 560; 561; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ugt: 562; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 563; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 564; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 565; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 566; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 567; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 568; 569; CHECKIZFHMIN-LABEL: fcmp_ugt: 570; CHECKIZFHMIN: # %bb.0: 571; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 572; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 573; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 574; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 575; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 576; CHECKIZFHMIN-NEXT: xori a0, a0, 1 577; CHECKIZFHMIN-NEXT: ret 578; 579; CHECKIZHINXMIN-LABEL: fcmp_ugt: 580; CHECKIZHINXMIN: # %bb.0: 581; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 582; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 583; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1 584; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 585; CHECKIZHINXMIN-NEXT: ret 586 %1 = fcmp ugt half %a, %b 587 %2 = zext i1 %1 to i32 588 ret i32 %2 589} 590 591define i32 @fcmp_uge(half %a, half %b) nounwind { 592; CHECKIZFH-LABEL: fcmp_uge: 593; CHECKIZFH: # %bb.0: 594; CHECKIZFH-NEXT: flt.h a0, fa0, fa1 595; CHECKIZFH-NEXT: xori a0, a0, 1 596; CHECKIZFH-NEXT: ret 597; 598; CHECKIZHINX-LABEL: fcmp_uge: 599; CHECKIZHINX: # %bb.0: 600; CHECKIZHINX-NEXT: flt.h a0, a0, a1 601; CHECKIZHINX-NEXT: xori a0, a0, 1 602; CHECKIZHINX-NEXT: ret 603; 604; RV32I-LABEL: fcmp_uge: 605; RV32I: # %bb.0: 606; RV32I-NEXT: fmv.h.x fa5, a1 607; RV32I-NEXT: fmv.h.x fa4, a0 608; RV32I-NEXT: flt.h a0, fa4, fa5 609; RV32I-NEXT: xori a0, a0, 1 610; RV32I-NEXT: ret 611; 612; RV64I-LABEL: fcmp_uge: 613; RV64I: # %bb.0: 614; RV64I-NEXT: fmv.h.x fa5, a1 615; RV64I-NEXT: fmv.h.x fa4, a0 616; RV64I-NEXT: flt.h a0, fa4, fa5 617; RV64I-NEXT: xori a0, a0, 1 618; RV64I-NEXT: ret 619; 620; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uge: 621; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 622; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 623; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 624; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 625; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 626; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 627; 628; CHECKIZFHMIN-LABEL: fcmp_uge: 629; CHECKIZFHMIN: # %bb.0: 630; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 631; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 632; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 633; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 634; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 635; CHECKIZFHMIN-NEXT: xori a0, a0, 1 636; CHECKIZFHMIN-NEXT: ret 637; 638; CHECKIZHINXMIN-LABEL: fcmp_uge: 639; CHECKIZHINXMIN: # %bb.0: 640; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 641; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 642; CHECKIZHINXMIN-NEXT: flt.s a0, a0, a1 643; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 644; CHECKIZHINXMIN-NEXT: ret 645 %1 = fcmp uge half %a, %b 646 %2 = zext i1 %1 to i32 647 ret i32 %2 648} 649 650define i32 @fcmp_ult(half %a, half %b) nounwind { 651; CHECKIZFH-LABEL: fcmp_ult: 652; CHECKIZFH: # %bb.0: 653; CHECKIZFH-NEXT: fle.h a0, fa1, fa0 654; CHECKIZFH-NEXT: xori a0, a0, 1 655; CHECKIZFH-NEXT: ret 656; 657; CHECKIZHINX-LABEL: fcmp_ult: 658; CHECKIZHINX: # %bb.0: 659; CHECKIZHINX-NEXT: fle.h a0, a1, a0 660; CHECKIZHINX-NEXT: xori a0, a0, 1 661; CHECKIZHINX-NEXT: ret 662; 663; RV32I-LABEL: fcmp_ult: 664; RV32I: # %bb.0: 665; RV32I-NEXT: fmv.h.x fa5, a0 666; RV32I-NEXT: fmv.h.x fa4, a1 667; RV32I-NEXT: fle.h a0, fa4, fa5 668; RV32I-NEXT: xori a0, a0, 1 669; RV32I-NEXT: ret 670; 671; RV64I-LABEL: fcmp_ult: 672; RV64I: # %bb.0: 673; RV64I-NEXT: fmv.h.x fa5, a0 674; RV64I-NEXT: fmv.h.x fa4, a1 675; RV64I-NEXT: fle.h a0, fa4, fa5 676; RV64I-NEXT: xori a0, a0, 1 677; RV64I-NEXT: ret 678; 679; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ult: 680; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 681; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 682; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 683; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 684; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 685; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 686; 687; CHECKIZFHMIN-LABEL: fcmp_ult: 688; CHECKIZFHMIN: # %bb.0: 689; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 690; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 691; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 692; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 693; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 694; CHECKIZFHMIN-NEXT: xori a0, a0, 1 695; CHECKIZFHMIN-NEXT: ret 696; 697; CHECKIZHINXMIN-LABEL: fcmp_ult: 698; CHECKIZHINXMIN: # %bb.0: 699; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 700; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 701; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a0 702; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 703; CHECKIZHINXMIN-NEXT: ret 704 %1 = fcmp ult half %a, %b 705 %2 = zext i1 %1 to i32 706 ret i32 %2 707} 708 709define i32 @fcmp_ule(half %a, half %b) nounwind { 710; CHECKIZFH-LABEL: fcmp_ule: 711; CHECKIZFH: # %bb.0: 712; CHECKIZFH-NEXT: flt.h a0, fa1, fa0 713; CHECKIZFH-NEXT: xori a0, a0, 1 714; CHECKIZFH-NEXT: ret 715; 716; CHECKIZHINX-LABEL: fcmp_ule: 717; CHECKIZHINX: # %bb.0: 718; CHECKIZHINX-NEXT: flt.h a0, a1, a0 719; CHECKIZHINX-NEXT: xori a0, a0, 1 720; CHECKIZHINX-NEXT: ret 721; 722; RV32I-LABEL: fcmp_ule: 723; RV32I: # %bb.0: 724; RV32I-NEXT: fmv.h.x fa5, a0 725; RV32I-NEXT: fmv.h.x fa4, a1 726; RV32I-NEXT: flt.h a0, fa4, fa5 727; RV32I-NEXT: xori a0, a0, 1 728; RV32I-NEXT: ret 729; 730; RV64I-LABEL: fcmp_ule: 731; RV64I: # %bb.0: 732; RV64I-NEXT: fmv.h.x fa5, a0 733; RV64I-NEXT: fmv.h.x fa4, a1 734; RV64I-NEXT: flt.h a0, fa4, fa5 735; RV64I-NEXT: xori a0, a0, 1 736; RV64I-NEXT: ret 737; 738; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ule: 739; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 740; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 741; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 742; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 743; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 744; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 745; 746; CHECKIZFHMIN-LABEL: fcmp_ule: 747; CHECKIZFHMIN: # %bb.0: 748; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 749; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 750; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 751; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 752; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 753; CHECKIZFHMIN-NEXT: xori a0, a0, 1 754; CHECKIZFHMIN-NEXT: ret 755; 756; CHECKIZHINXMIN-LABEL: fcmp_ule: 757; CHECKIZHINXMIN: # %bb.0: 758; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 759; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 760; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 761; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 762; CHECKIZHINXMIN-NEXT: ret 763 %1 = fcmp ule half %a, %b 764 %2 = zext i1 %1 to i32 765 ret i32 %2 766} 767 768define i32 @fcmp_une(half %a, half %b) nounwind { 769; CHECKIZFH-LABEL: fcmp_une: 770; CHECKIZFH: # %bb.0: 771; CHECKIZFH-NEXT: feq.h a0, fa0, fa1 772; CHECKIZFH-NEXT: xori a0, a0, 1 773; CHECKIZFH-NEXT: ret 774; 775; CHECKIZHINX-LABEL: fcmp_une: 776; CHECKIZHINX: # %bb.0: 777; CHECKIZHINX-NEXT: feq.h a0, a0, a1 778; CHECKIZHINX-NEXT: xori a0, a0, 1 779; CHECKIZHINX-NEXT: ret 780; 781; RV32I-LABEL: fcmp_une: 782; RV32I: # %bb.0: 783; RV32I-NEXT: fmv.h.x fa5, a1 784; RV32I-NEXT: fmv.h.x fa4, a0 785; RV32I-NEXT: feq.h a0, fa4, fa5 786; RV32I-NEXT: xori a0, a0, 1 787; RV32I-NEXT: ret 788; 789; RV64I-LABEL: fcmp_une: 790; RV64I: # %bb.0: 791; RV64I-NEXT: fmv.h.x fa5, a1 792; RV64I-NEXT: fmv.h.x fa4, a0 793; RV64I-NEXT: feq.h a0, fa4, fa5 794; RV64I-NEXT: xori a0, a0, 1 795; RV64I-NEXT: ret 796; 797; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_une: 798; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 799; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 800; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 801; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa4, fa5 802; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 803; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 804; 805; CHECKIZFHMIN-LABEL: fcmp_une: 806; CHECKIZFHMIN: # %bb.0: 807; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 808; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 809; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 810; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 811; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4 812; CHECKIZFHMIN-NEXT: xori a0, a0, 1 813; CHECKIZFHMIN-NEXT: ret 814; 815; CHECKIZHINXMIN-LABEL: fcmp_une: 816; CHECKIZHINXMIN: # %bb.0: 817; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 818; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 819; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a1 820; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 821; CHECKIZHINXMIN-NEXT: ret 822 %1 = fcmp une half %a, %b 823 %2 = zext i1 %1 to i32 824 ret i32 %2 825} 826 827define i32 @fcmp_uno(half %a, half %b) nounwind { 828; CHECKIZFH-LABEL: fcmp_uno: 829; CHECKIZFH: # %bb.0: 830; CHECKIZFH-NEXT: feq.h a0, fa1, fa1 831; CHECKIZFH-NEXT: feq.h a1, fa0, fa0 832; CHECKIZFH-NEXT: and a0, a1, a0 833; CHECKIZFH-NEXT: xori a0, a0, 1 834; CHECKIZFH-NEXT: ret 835; 836; CHECKIZHINX-LABEL: fcmp_uno: 837; CHECKIZHINX: # %bb.0: 838; CHECKIZHINX-NEXT: feq.h a1, a1, a1 839; CHECKIZHINX-NEXT: feq.h a0, a0, a0 840; CHECKIZHINX-NEXT: and a0, a0, a1 841; CHECKIZHINX-NEXT: xori a0, a0, 1 842; CHECKIZHINX-NEXT: ret 843; 844; RV32I-LABEL: fcmp_uno: 845; RV32I: # %bb.0: 846; RV32I-NEXT: fmv.h.x fa5, a0 847; RV32I-NEXT: fmv.h.x fa4, a1 848; RV32I-NEXT: feq.h a0, fa4, fa4 849; RV32I-NEXT: feq.h a1, fa5, fa5 850; RV32I-NEXT: and a0, a1, a0 851; RV32I-NEXT: xori a0, a0, 1 852; RV32I-NEXT: ret 853; 854; RV64I-LABEL: fcmp_uno: 855; RV64I: # %bb.0: 856; RV64I-NEXT: fmv.h.x fa5, a0 857; RV64I-NEXT: fmv.h.x fa4, a1 858; RV64I-NEXT: feq.h a0, fa4, fa4 859; RV64I-NEXT: feq.h a1, fa5, fa5 860; RV64I-NEXT: and a0, a1, a0 861; RV64I-NEXT: xori a0, a0, 1 862; RV64I-NEXT: ret 863; 864; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uno: 865; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 866; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 867; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 868; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a0, fa5, fa5 869; CHECKIZFHMIN-ILP32F-LP64F-NEXT: feq.s a1, fa4, fa4 870; CHECKIZFHMIN-ILP32F-LP64F-NEXT: and a0, a1, a0 871; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 872; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 873; 874; CHECKIZFHMIN-LABEL: fcmp_uno: 875; CHECKIZFHMIN: # %bb.0: 876; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 877; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 878; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 879; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 880; CHECKIZFHMIN-NEXT: feq.s a0, fa4, fa4 881; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5 882; CHECKIZFHMIN-NEXT: and a0, a1, a0 883; CHECKIZFHMIN-NEXT: xori a0, a0, 1 884; CHECKIZFHMIN-NEXT: ret 885; 886; CHECKIZHINXMIN-LABEL: fcmp_uno: 887; CHECKIZHINXMIN: # %bb.0: 888; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 889; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 890; CHECKIZHINXMIN-NEXT: feq.s a1, a1, a1 891; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0 892; CHECKIZHINXMIN-NEXT: and a0, a0, a1 893; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 894; CHECKIZHINXMIN-NEXT: ret 895 %1 = fcmp uno half %a, %b 896 %2 = zext i1 %1 to i32 897 ret i32 %2 898} 899 900define i32 @fcmp_true(half %a, half %b) nounwind { 901; CHECKIZFH-LABEL: fcmp_true: 902; CHECKIZFH: # %bb.0: 903; CHECKIZFH-NEXT: li a0, 1 904; CHECKIZFH-NEXT: ret 905; 906; CHECKIZHINX-LABEL: fcmp_true: 907; CHECKIZHINX: # %bb.0: 908; CHECKIZHINX-NEXT: li a0, 1 909; CHECKIZHINX-NEXT: ret 910; 911; RV32I-LABEL: fcmp_true: 912; RV32I: # %bb.0: 913; RV32I-NEXT: li a0, 1 914; RV32I-NEXT: ret 915; 916; RV64I-LABEL: fcmp_true: 917; RV64I: # %bb.0: 918; RV64I-NEXT: li a0, 1 919; RV64I-NEXT: ret 920; 921; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_true: 922; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: 923; CHECKIZFHMIN-ILP32F-LP64F-NEXT: li a0, 1 924; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret 925; 926; CHECKIZFHMIN-LABEL: fcmp_true: 927; CHECKIZFHMIN: # %bb.0: 928; CHECKIZFHMIN-NEXT: li a0, 1 929; CHECKIZFHMIN-NEXT: ret 930; 931; CHECKIZHINXMIN-LABEL: fcmp_true: 932; CHECKIZHINXMIN: # %bb.0: 933; CHECKIZHINXMIN-NEXT: li a0, 1 934; CHECKIZHINXMIN-NEXT: ret 935 %1 = fcmp true half %a, %b 936 %2 = zext i1 %1 to i32 937 ret i32 %2 938} 939