1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f,+d -stop-after=finalize-isel < %s \ 3; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=RV32IF %s 4; RUN: llc -mtriple=riscv64 -mattr=+f,+d -stop-after=finalize-isel < %s \ 5; RUN: -target-abi=lp64d | FileCheck -check-prefixes=RV64IF %s 6 7; Make sure an implicit FRM dependency is added to instructions with dynamic 8; rounding. 9 10define float @fadd_s(float %a, float %b) nounwind { 11 ; RV32IF-LABEL: name: fadd_s 12 ; RV32IF: bb.0 (%ir-block.0): 13 ; RV32IF-NEXT: liveins: $f10_f, $f11_f 14 ; RV32IF-NEXT: {{ $}} 15 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f 16 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f 17 ; RV32IF-NEXT: %2:fpr32 = nofpexcept FADD_S [[COPY1]], [[COPY]], 7, implicit $frm 18 ; RV32IF-NEXT: $f10_f = COPY %2 19 ; RV32IF-NEXT: PseudoRET implicit $f10_f 20 ; RV64IF-LABEL: name: fadd_s 21 ; RV64IF: bb.0 (%ir-block.0): 22 ; RV64IF-NEXT: liveins: $f10_f, $f11_f 23 ; RV64IF-NEXT: {{ $}} 24 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f 25 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f 26 ; RV64IF-NEXT: %2:fpr32 = nofpexcept FADD_S [[COPY1]], [[COPY]], 7, implicit $frm 27 ; RV64IF-NEXT: $f10_f = COPY %2 28 ; RV64IF-NEXT: PseudoRET implicit $f10_f 29 %1 = fadd float %a, %b 30 ret float %1 31} 32 33declare float @llvm.fma.f32(float, float, float) 34 35define float @fmadd_s(float %a, float %b, float %c) nounwind { 36 ; RV32IF-LABEL: name: fmadd_s 37 ; RV32IF: bb.0 (%ir-block.0): 38 ; RV32IF-NEXT: liveins: $f10_f, $f11_f, $f12_f 39 ; RV32IF-NEXT: {{ $}} 40 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f12_f 41 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 42 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f 43 ; RV32IF-NEXT: %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm 44 ; RV32IF-NEXT: $f10_f = COPY %3 45 ; RV32IF-NEXT: PseudoRET implicit $f10_f 46 ; RV64IF-LABEL: name: fmadd_s 47 ; RV64IF: bb.0 (%ir-block.0): 48 ; RV64IF-NEXT: liveins: $f10_f, $f11_f, $f12_f 49 ; RV64IF-NEXT: {{ $}} 50 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f12_f 51 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f 52 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f 53 ; RV64IF-NEXT: %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm 54 ; RV64IF-NEXT: $f10_f = COPY %3 55 ; RV64IF-NEXT: PseudoRET implicit $f10_f 56 %1 = call float @llvm.fma.f32(float %a, float %b, float %c) 57 ret float %1 58} 59 60; This uses rtz instead of dyn rounding mode so shouldn't have an FRM dependncy. 61define i32 @fcvt_w_s(float %a) nounwind { 62 ; RV32IF-LABEL: name: fcvt_w_s 63 ; RV32IF: bb.0 (%ir-block.0): 64 ; RV32IF-NEXT: liveins: $f10_f 65 ; RV32IF-NEXT: {{ $}} 66 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 67 ; RV32IF-NEXT: %1:gpr = nofpexcept FCVT_W_S [[COPY]], 1 68 ; RV32IF-NEXT: $x10 = COPY %1 69 ; RV32IF-NEXT: PseudoRET implicit $x10 70 ; RV64IF-LABEL: name: fcvt_w_s 71 ; RV64IF: bb.0 (%ir-block.0): 72 ; RV64IF-NEXT: liveins: $f10_f 73 ; RV64IF-NEXT: {{ $}} 74 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f 75 ; RV64IF-NEXT: %1:gpr = nofpexcept FCVT_W_S [[COPY]], 1 76 ; RV64IF-NEXT: $x10 = COPY %1 77 ; RV64IF-NEXT: PseudoRET implicit $x10 78 %1 = fptosi float %a to i32 79 ret i32 %1 80} 81 82; This doesn't use a rounding mode since i32 can be represented exactly as a 83; double. 84define double @fcvt_d_w(i32 %a) nounwind { 85 ; RV32IF-LABEL: name: fcvt_d_w 86 ; RV32IF: bb.0 (%ir-block.0): 87 ; RV32IF-NEXT: liveins: $x10 88 ; RV32IF-NEXT: {{ $}} 89 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 90 ; RV32IF-NEXT: %1:fpr64 = nofpexcept FCVT_D_W [[COPY]] 91 ; RV32IF-NEXT: $f10_d = COPY %1 92 ; RV32IF-NEXT: PseudoRET implicit $f10_d 93 ; RV64IF-LABEL: name: fcvt_d_w 94 ; RV64IF: bb.0 (%ir-block.0): 95 ; RV64IF-NEXT: liveins: $x10 96 ; RV64IF-NEXT: {{ $}} 97 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 98 ; RV64IF-NEXT: %1:fpr64 = nofpexcept FCVT_D_W [[COPY]] 99 ; RV64IF-NEXT: $f10_d = COPY %1 100 ; RV64IF-NEXT: PseudoRET implicit $f10_d 101 %1 = sitofp i32 %a to double 102 ret double %1 103} 104