xref: /llvm-project/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
7; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s
8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
9; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s
10
11define signext i32 @test_floor_si32(float %x) {
12; CHECKIF-LABEL: test_floor_si32:
13; CHECKIF:       # %bb.0:
14; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rdn
15; CHECKIF-NEXT:    feq.s a1, fa0, fa0
16; CHECKIF-NEXT:    seqz a1, a1
17; CHECKIF-NEXT:    addi a1, a1, -1
18; CHECKIF-NEXT:    and a0, a1, a0
19; CHECKIF-NEXT:    ret
20;
21; CHECKIZFINX-LABEL: test_floor_si32:
22; CHECKIZFINX:       # %bb.0:
23; CHECKIZFINX-NEXT:    fcvt.w.s a1, a0, rdn
24; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
25; CHECKIZFINX-NEXT:    seqz a0, a0
26; CHECKIZFINX-NEXT:    addi a0, a0, -1
27; CHECKIZFINX-NEXT:    and a0, a0, a1
28; CHECKIZFINX-NEXT:    ret
29  %a = call float @llvm.floor.f32(float %x)
30  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
31  ret i32 %b
32}
33
34define i64 @test_floor_si64(float %x) nounwind {
35; RV32IF-LABEL: test_floor_si64:
36; RV32IF:       # %bb.0:
37; RV32IF-NEXT:    addi sp, sp, -16
38; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
39; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
40; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
41; RV32IF-NEXT:    fmv.s fs0, fa0
42; RV32IF-NEXT:    lui a0, 307200
43; RV32IF-NEXT:    fmv.w.x fa5, a0
44; RV32IF-NEXT:    fabs.s fa4, fa0
45; RV32IF-NEXT:    flt.s a0, fa4, fa5
46; RV32IF-NEXT:    beqz a0, .LBB1_2
47; RV32IF-NEXT:  # %bb.1:
48; RV32IF-NEXT:    fcvt.w.s a0, fs0, rdn
49; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
50; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
51; RV32IF-NEXT:  .LBB1_2:
52; RV32IF-NEXT:    lui a0, 913408
53; RV32IF-NEXT:    fmv.w.x fa5, a0
54; RV32IF-NEXT:    fle.s s0, fa5, fs0
55; RV32IF-NEXT:    fmv.s fa0, fs0
56; RV32IF-NEXT:    call __fixsfdi
57; RV32IF-NEXT:    lui a3, 524288
58; RV32IF-NEXT:    lui a2, 524288
59; RV32IF-NEXT:    beqz s0, .LBB1_4
60; RV32IF-NEXT:  # %bb.3:
61; RV32IF-NEXT:    mv a2, a1
62; RV32IF-NEXT:  .LBB1_4:
63; RV32IF-NEXT:    lui a1, %hi(.LCPI1_0)
64; RV32IF-NEXT:    flw fa5, %lo(.LCPI1_0)(a1)
65; RV32IF-NEXT:    flt.s a1, fa5, fs0
66; RV32IF-NEXT:    beqz a1, .LBB1_6
67; RV32IF-NEXT:  # %bb.5:
68; RV32IF-NEXT:    addi a2, a3, -1
69; RV32IF-NEXT:  .LBB1_6:
70; RV32IF-NEXT:    feq.s a3, fs0, fs0
71; RV32IF-NEXT:    neg a4, s0
72; RV32IF-NEXT:    neg a5, a1
73; RV32IF-NEXT:    neg a3, a3
74; RV32IF-NEXT:    and a0, a4, a0
75; RV32IF-NEXT:    and a1, a3, a2
76; RV32IF-NEXT:    or a0, a5, a0
77; RV32IF-NEXT:    and a0, a3, a0
78; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
79; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
80; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
81; RV32IF-NEXT:    addi sp, sp, 16
82; RV32IF-NEXT:    ret
83;
84; RV64IF-LABEL: test_floor_si64:
85; RV64IF:       # %bb.0:
86; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
87; RV64IF-NEXT:    feq.s a1, fa0, fa0
88; RV64IF-NEXT:    seqz a1, a1
89; RV64IF-NEXT:    addi a1, a1, -1
90; RV64IF-NEXT:    and a0, a1, a0
91; RV64IF-NEXT:    ret
92;
93; RV32IZFINX-LABEL: test_floor_si64:
94; RV32IZFINX:       # %bb.0:
95; RV32IZFINX-NEXT:    addi sp, sp, -16
96; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
97; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
98; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
99; RV32IZFINX-NEXT:    mv s0, a0
100; RV32IZFINX-NEXT:    lui a0, 307200
101; RV32IZFINX-NEXT:    fabs.s a1, s0
102; RV32IZFINX-NEXT:    flt.s a0, a1, a0
103; RV32IZFINX-NEXT:    beqz a0, .LBB1_2
104; RV32IZFINX-NEXT:  # %bb.1:
105; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rdn
106; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rdn
107; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
108; RV32IZFINX-NEXT:  .LBB1_2:
109; RV32IZFINX-NEXT:    lui a0, 913408
110; RV32IZFINX-NEXT:    fle.s s1, a0, s0
111; RV32IZFINX-NEXT:    mv a0, s0
112; RV32IZFINX-NEXT:    call __fixsfdi
113; RV32IZFINX-NEXT:    lui a3, 524288
114; RV32IZFINX-NEXT:    lui a2, 524288
115; RV32IZFINX-NEXT:    beqz s1, .LBB1_4
116; RV32IZFINX-NEXT:  # %bb.3:
117; RV32IZFINX-NEXT:    mv a2, a1
118; RV32IZFINX-NEXT:  .LBB1_4:
119; RV32IZFINX-NEXT:    lui a1, 389120
120; RV32IZFINX-NEXT:    addi a1, a1, -1
121; RV32IZFINX-NEXT:    flt.s a1, a1, s0
122; RV32IZFINX-NEXT:    beqz a1, .LBB1_6
123; RV32IZFINX-NEXT:  # %bb.5:
124; RV32IZFINX-NEXT:    addi a2, a3, -1
125; RV32IZFINX-NEXT:  .LBB1_6:
126; RV32IZFINX-NEXT:    feq.s a3, s0, s0
127; RV32IZFINX-NEXT:    neg a4, s1
128; RV32IZFINX-NEXT:    neg a5, a1
129; RV32IZFINX-NEXT:    neg a3, a3
130; RV32IZFINX-NEXT:    and a0, a4, a0
131; RV32IZFINX-NEXT:    and a1, a3, a2
132; RV32IZFINX-NEXT:    or a0, a5, a0
133; RV32IZFINX-NEXT:    and a0, a3, a0
134; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
135; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
136; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
137; RV32IZFINX-NEXT:    addi sp, sp, 16
138; RV32IZFINX-NEXT:    ret
139;
140; RV64IZFINX-LABEL: test_floor_si64:
141; RV64IZFINX:       # %bb.0:
142; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rdn
143; RV64IZFINX-NEXT:    feq.s a0, a0, a0
144; RV64IZFINX-NEXT:    seqz a0, a0
145; RV64IZFINX-NEXT:    addi a0, a0, -1
146; RV64IZFINX-NEXT:    and a0, a0, a1
147; RV64IZFINX-NEXT:    ret
148  %a = call float @llvm.floor.f32(float %x)
149  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
150  ret i64 %b
151}
152
153define signext i32 @test_floor_ui32(float %x) {
154; CHECKIF-LABEL: test_floor_ui32:
155; CHECKIF:       # %bb.0:
156; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rdn
157; CHECKIF-NEXT:    feq.s a1, fa0, fa0
158; CHECKIF-NEXT:    seqz a1, a1
159; CHECKIF-NEXT:    addi a1, a1, -1
160; CHECKIF-NEXT:    and a0, a1, a0
161; CHECKIF-NEXT:    ret
162;
163; CHECKIZFINX-LABEL: test_floor_ui32:
164; CHECKIZFINX:       # %bb.0:
165; CHECKIZFINX-NEXT:    fcvt.wu.s a1, a0, rdn
166; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
167; CHECKIZFINX-NEXT:    seqz a0, a0
168; CHECKIZFINX-NEXT:    addi a0, a0, -1
169; CHECKIZFINX-NEXT:    and a0, a0, a1
170; CHECKIZFINX-NEXT:    ret
171  %a = call float @llvm.floor.f32(float %x)
172  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
173  ret i32 %b
174}
175
176define i64 @test_floor_ui64(float %x) nounwind {
177; RV32IF-LABEL: test_floor_ui64:
178; RV32IF:       # %bb.0:
179; RV32IF-NEXT:    addi sp, sp, -16
180; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
181; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
182; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
183; RV32IF-NEXT:    fmv.s fs0, fa0
184; RV32IF-NEXT:    lui a0, 307200
185; RV32IF-NEXT:    fmv.w.x fa5, a0
186; RV32IF-NEXT:    fabs.s fa4, fa0
187; RV32IF-NEXT:    flt.s a0, fa4, fa5
188; RV32IF-NEXT:    beqz a0, .LBB3_2
189; RV32IF-NEXT:  # %bb.1:
190; RV32IF-NEXT:    fcvt.w.s a0, fs0, rdn
191; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
192; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
193; RV32IF-NEXT:  .LBB3_2:
194; RV32IF-NEXT:    fmv.w.x fa5, zero
195; RV32IF-NEXT:    fle.s a0, fa5, fs0
196; RV32IF-NEXT:    neg s0, a0
197; RV32IF-NEXT:    fmv.s fa0, fs0
198; RV32IF-NEXT:    call __fixunssfdi
199; RV32IF-NEXT:    lui a2, %hi(.LCPI3_0)
200; RV32IF-NEXT:    flw fa5, %lo(.LCPI3_0)(a2)
201; RV32IF-NEXT:    and a0, s0, a0
202; RV32IF-NEXT:    and a1, s0, a1
203; RV32IF-NEXT:    flt.s a2, fa5, fs0
204; RV32IF-NEXT:    neg a2, a2
205; RV32IF-NEXT:    or a0, a2, a0
206; RV32IF-NEXT:    or a1, a2, a1
207; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
208; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
209; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
210; RV32IF-NEXT:    addi sp, sp, 16
211; RV32IF-NEXT:    ret
212;
213; RV64IF-LABEL: test_floor_ui64:
214; RV64IF:       # %bb.0:
215; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
216; RV64IF-NEXT:    feq.s a1, fa0, fa0
217; RV64IF-NEXT:    seqz a1, a1
218; RV64IF-NEXT:    addi a1, a1, -1
219; RV64IF-NEXT:    and a0, a1, a0
220; RV64IF-NEXT:    ret
221;
222; RV32IZFINX-LABEL: test_floor_ui64:
223; RV32IZFINX:       # %bb.0:
224; RV32IZFINX-NEXT:    addi sp, sp, -16
225; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
226; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
227; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
228; RV32IZFINX-NEXT:    mv s0, a0
229; RV32IZFINX-NEXT:    lui a0, 307200
230; RV32IZFINX-NEXT:    fabs.s a1, s0
231; RV32IZFINX-NEXT:    flt.s a0, a1, a0
232; RV32IZFINX-NEXT:    beqz a0, .LBB3_2
233; RV32IZFINX-NEXT:  # %bb.1:
234; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rdn
235; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rdn
236; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
237; RV32IZFINX-NEXT:  .LBB3_2:
238; RV32IZFINX-NEXT:    fle.s a0, zero, s0
239; RV32IZFINX-NEXT:    neg s1, a0
240; RV32IZFINX-NEXT:    mv a0, s0
241; RV32IZFINX-NEXT:    call __fixunssfdi
242; RV32IZFINX-NEXT:    and a0, s1, a0
243; RV32IZFINX-NEXT:    lui a2, 391168
244; RV32IZFINX-NEXT:    and a1, s1, a1
245; RV32IZFINX-NEXT:    addi a2, a2, -1
246; RV32IZFINX-NEXT:    flt.s a2, a2, s0
247; RV32IZFINX-NEXT:    neg a2, a2
248; RV32IZFINX-NEXT:    or a0, a2, a0
249; RV32IZFINX-NEXT:    or a1, a2, a1
250; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
251; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
252; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
253; RV32IZFINX-NEXT:    addi sp, sp, 16
254; RV32IZFINX-NEXT:    ret
255;
256; RV64IZFINX-LABEL: test_floor_ui64:
257; RV64IZFINX:       # %bb.0:
258; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rdn
259; RV64IZFINX-NEXT:    feq.s a0, a0, a0
260; RV64IZFINX-NEXT:    seqz a0, a0
261; RV64IZFINX-NEXT:    addi a0, a0, -1
262; RV64IZFINX-NEXT:    and a0, a0, a1
263; RV64IZFINX-NEXT:    ret
264  %a = call float @llvm.floor.f32(float %x)
265  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
266  ret i64 %b
267}
268
269define signext i32 @test_ceil_si32(float %x) {
270; CHECKIF-LABEL: test_ceil_si32:
271; CHECKIF:       # %bb.0:
272; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rup
273; CHECKIF-NEXT:    feq.s a1, fa0, fa0
274; CHECKIF-NEXT:    seqz a1, a1
275; CHECKIF-NEXT:    addi a1, a1, -1
276; CHECKIF-NEXT:    and a0, a1, a0
277; CHECKIF-NEXT:    ret
278;
279; CHECKIZFINX-LABEL: test_ceil_si32:
280; CHECKIZFINX:       # %bb.0:
281; CHECKIZFINX-NEXT:    fcvt.w.s a1, a0, rup
282; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
283; CHECKIZFINX-NEXT:    seqz a0, a0
284; CHECKIZFINX-NEXT:    addi a0, a0, -1
285; CHECKIZFINX-NEXT:    and a0, a0, a1
286; CHECKIZFINX-NEXT:    ret
287  %a = call float @llvm.ceil.f32(float %x)
288  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
289  ret i32 %b
290}
291
292define i64 @test_ceil_si64(float %x) nounwind {
293; RV32IF-LABEL: test_ceil_si64:
294; RV32IF:       # %bb.0:
295; RV32IF-NEXT:    addi sp, sp, -16
296; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
297; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
298; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
299; RV32IF-NEXT:    fmv.s fs0, fa0
300; RV32IF-NEXT:    lui a0, 307200
301; RV32IF-NEXT:    fmv.w.x fa5, a0
302; RV32IF-NEXT:    fabs.s fa4, fa0
303; RV32IF-NEXT:    flt.s a0, fa4, fa5
304; RV32IF-NEXT:    beqz a0, .LBB5_2
305; RV32IF-NEXT:  # %bb.1:
306; RV32IF-NEXT:    fcvt.w.s a0, fs0, rup
307; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
308; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
309; RV32IF-NEXT:  .LBB5_2:
310; RV32IF-NEXT:    lui a0, 913408
311; RV32IF-NEXT:    fmv.w.x fa5, a0
312; RV32IF-NEXT:    fle.s s0, fa5, fs0
313; RV32IF-NEXT:    fmv.s fa0, fs0
314; RV32IF-NEXT:    call __fixsfdi
315; RV32IF-NEXT:    lui a3, 524288
316; RV32IF-NEXT:    lui a2, 524288
317; RV32IF-NEXT:    beqz s0, .LBB5_4
318; RV32IF-NEXT:  # %bb.3:
319; RV32IF-NEXT:    mv a2, a1
320; RV32IF-NEXT:  .LBB5_4:
321; RV32IF-NEXT:    lui a1, %hi(.LCPI5_0)
322; RV32IF-NEXT:    flw fa5, %lo(.LCPI5_0)(a1)
323; RV32IF-NEXT:    flt.s a1, fa5, fs0
324; RV32IF-NEXT:    beqz a1, .LBB5_6
325; RV32IF-NEXT:  # %bb.5:
326; RV32IF-NEXT:    addi a2, a3, -1
327; RV32IF-NEXT:  .LBB5_6:
328; RV32IF-NEXT:    feq.s a3, fs0, fs0
329; RV32IF-NEXT:    neg a4, s0
330; RV32IF-NEXT:    neg a5, a1
331; RV32IF-NEXT:    neg a3, a3
332; RV32IF-NEXT:    and a0, a4, a0
333; RV32IF-NEXT:    and a1, a3, a2
334; RV32IF-NEXT:    or a0, a5, a0
335; RV32IF-NEXT:    and a0, a3, a0
336; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
337; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
338; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
339; RV32IF-NEXT:    addi sp, sp, 16
340; RV32IF-NEXT:    ret
341;
342; RV64IF-LABEL: test_ceil_si64:
343; RV64IF:       # %bb.0:
344; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
345; RV64IF-NEXT:    feq.s a1, fa0, fa0
346; RV64IF-NEXT:    seqz a1, a1
347; RV64IF-NEXT:    addi a1, a1, -1
348; RV64IF-NEXT:    and a0, a1, a0
349; RV64IF-NEXT:    ret
350;
351; RV32IZFINX-LABEL: test_ceil_si64:
352; RV32IZFINX:       # %bb.0:
353; RV32IZFINX-NEXT:    addi sp, sp, -16
354; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
355; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
356; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
357; RV32IZFINX-NEXT:    mv s0, a0
358; RV32IZFINX-NEXT:    lui a0, 307200
359; RV32IZFINX-NEXT:    fabs.s a1, s0
360; RV32IZFINX-NEXT:    flt.s a0, a1, a0
361; RV32IZFINX-NEXT:    beqz a0, .LBB5_2
362; RV32IZFINX-NEXT:  # %bb.1:
363; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rup
364; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rup
365; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
366; RV32IZFINX-NEXT:  .LBB5_2:
367; RV32IZFINX-NEXT:    lui a0, 913408
368; RV32IZFINX-NEXT:    fle.s s1, a0, s0
369; RV32IZFINX-NEXT:    mv a0, s0
370; RV32IZFINX-NEXT:    call __fixsfdi
371; RV32IZFINX-NEXT:    lui a3, 524288
372; RV32IZFINX-NEXT:    lui a2, 524288
373; RV32IZFINX-NEXT:    beqz s1, .LBB5_4
374; RV32IZFINX-NEXT:  # %bb.3:
375; RV32IZFINX-NEXT:    mv a2, a1
376; RV32IZFINX-NEXT:  .LBB5_4:
377; RV32IZFINX-NEXT:    lui a1, 389120
378; RV32IZFINX-NEXT:    addi a1, a1, -1
379; RV32IZFINX-NEXT:    flt.s a1, a1, s0
380; RV32IZFINX-NEXT:    beqz a1, .LBB5_6
381; RV32IZFINX-NEXT:  # %bb.5:
382; RV32IZFINX-NEXT:    addi a2, a3, -1
383; RV32IZFINX-NEXT:  .LBB5_6:
384; RV32IZFINX-NEXT:    feq.s a3, s0, s0
385; RV32IZFINX-NEXT:    neg a4, s1
386; RV32IZFINX-NEXT:    neg a5, a1
387; RV32IZFINX-NEXT:    neg a3, a3
388; RV32IZFINX-NEXT:    and a0, a4, a0
389; RV32IZFINX-NEXT:    and a1, a3, a2
390; RV32IZFINX-NEXT:    or a0, a5, a0
391; RV32IZFINX-NEXT:    and a0, a3, a0
392; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
393; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
394; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
395; RV32IZFINX-NEXT:    addi sp, sp, 16
396; RV32IZFINX-NEXT:    ret
397;
398; RV64IZFINX-LABEL: test_ceil_si64:
399; RV64IZFINX:       # %bb.0:
400; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rup
401; RV64IZFINX-NEXT:    feq.s a0, a0, a0
402; RV64IZFINX-NEXT:    seqz a0, a0
403; RV64IZFINX-NEXT:    addi a0, a0, -1
404; RV64IZFINX-NEXT:    and a0, a0, a1
405; RV64IZFINX-NEXT:    ret
406  %a = call float @llvm.ceil.f32(float %x)
407  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
408  ret i64 %b
409}
410
411define signext i32 @test_ceil_ui32(float %x) {
412; CHECKIF-LABEL: test_ceil_ui32:
413; CHECKIF:       # %bb.0:
414; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rup
415; CHECKIF-NEXT:    feq.s a1, fa0, fa0
416; CHECKIF-NEXT:    seqz a1, a1
417; CHECKIF-NEXT:    addi a1, a1, -1
418; CHECKIF-NEXT:    and a0, a1, a0
419; CHECKIF-NEXT:    ret
420;
421; CHECKIZFINX-LABEL: test_ceil_ui32:
422; CHECKIZFINX:       # %bb.0:
423; CHECKIZFINX-NEXT:    fcvt.wu.s a1, a0, rup
424; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
425; CHECKIZFINX-NEXT:    seqz a0, a0
426; CHECKIZFINX-NEXT:    addi a0, a0, -1
427; CHECKIZFINX-NEXT:    and a0, a0, a1
428; CHECKIZFINX-NEXT:    ret
429  %a = call float @llvm.ceil.f32(float %x)
430  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
431  ret i32 %b
432}
433
434define i64 @test_ceil_ui64(float %x) nounwind {
435; RV32IF-LABEL: test_ceil_ui64:
436; RV32IF:       # %bb.0:
437; RV32IF-NEXT:    addi sp, sp, -16
438; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
439; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
440; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
441; RV32IF-NEXT:    fmv.s fs0, fa0
442; RV32IF-NEXT:    lui a0, 307200
443; RV32IF-NEXT:    fmv.w.x fa5, a0
444; RV32IF-NEXT:    fabs.s fa4, fa0
445; RV32IF-NEXT:    flt.s a0, fa4, fa5
446; RV32IF-NEXT:    beqz a0, .LBB7_2
447; RV32IF-NEXT:  # %bb.1:
448; RV32IF-NEXT:    fcvt.w.s a0, fs0, rup
449; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
450; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
451; RV32IF-NEXT:  .LBB7_2:
452; RV32IF-NEXT:    fmv.w.x fa5, zero
453; RV32IF-NEXT:    fle.s a0, fa5, fs0
454; RV32IF-NEXT:    neg s0, a0
455; RV32IF-NEXT:    fmv.s fa0, fs0
456; RV32IF-NEXT:    call __fixunssfdi
457; RV32IF-NEXT:    lui a2, %hi(.LCPI7_0)
458; RV32IF-NEXT:    flw fa5, %lo(.LCPI7_0)(a2)
459; RV32IF-NEXT:    and a0, s0, a0
460; RV32IF-NEXT:    and a1, s0, a1
461; RV32IF-NEXT:    flt.s a2, fa5, fs0
462; RV32IF-NEXT:    neg a2, a2
463; RV32IF-NEXT:    or a0, a2, a0
464; RV32IF-NEXT:    or a1, a2, a1
465; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
466; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
467; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
468; RV32IF-NEXT:    addi sp, sp, 16
469; RV32IF-NEXT:    ret
470;
471; RV64IF-LABEL: test_ceil_ui64:
472; RV64IF:       # %bb.0:
473; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
474; RV64IF-NEXT:    feq.s a1, fa0, fa0
475; RV64IF-NEXT:    seqz a1, a1
476; RV64IF-NEXT:    addi a1, a1, -1
477; RV64IF-NEXT:    and a0, a1, a0
478; RV64IF-NEXT:    ret
479;
480; RV32IZFINX-LABEL: test_ceil_ui64:
481; RV32IZFINX:       # %bb.0:
482; RV32IZFINX-NEXT:    addi sp, sp, -16
483; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
484; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
485; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
486; RV32IZFINX-NEXT:    mv s0, a0
487; RV32IZFINX-NEXT:    lui a0, 307200
488; RV32IZFINX-NEXT:    fabs.s a1, s0
489; RV32IZFINX-NEXT:    flt.s a0, a1, a0
490; RV32IZFINX-NEXT:    beqz a0, .LBB7_2
491; RV32IZFINX-NEXT:  # %bb.1:
492; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rup
493; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rup
494; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
495; RV32IZFINX-NEXT:  .LBB7_2:
496; RV32IZFINX-NEXT:    fle.s a0, zero, s0
497; RV32IZFINX-NEXT:    neg s1, a0
498; RV32IZFINX-NEXT:    mv a0, s0
499; RV32IZFINX-NEXT:    call __fixunssfdi
500; RV32IZFINX-NEXT:    and a0, s1, a0
501; RV32IZFINX-NEXT:    lui a2, 391168
502; RV32IZFINX-NEXT:    and a1, s1, a1
503; RV32IZFINX-NEXT:    addi a2, a2, -1
504; RV32IZFINX-NEXT:    flt.s a2, a2, s0
505; RV32IZFINX-NEXT:    neg a2, a2
506; RV32IZFINX-NEXT:    or a0, a2, a0
507; RV32IZFINX-NEXT:    or a1, a2, a1
508; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
509; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
510; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
511; RV32IZFINX-NEXT:    addi sp, sp, 16
512; RV32IZFINX-NEXT:    ret
513;
514; RV64IZFINX-LABEL: test_ceil_ui64:
515; RV64IZFINX:       # %bb.0:
516; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rup
517; RV64IZFINX-NEXT:    feq.s a0, a0, a0
518; RV64IZFINX-NEXT:    seqz a0, a0
519; RV64IZFINX-NEXT:    addi a0, a0, -1
520; RV64IZFINX-NEXT:    and a0, a0, a1
521; RV64IZFINX-NEXT:    ret
522  %a = call float @llvm.ceil.f32(float %x)
523  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
524  ret i64 %b
525}
526
527define signext i32 @test_trunc_si32(float %x) {
528; CHECKIF-LABEL: test_trunc_si32:
529; CHECKIF:       # %bb.0:
530; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rtz
531; CHECKIF-NEXT:    feq.s a1, fa0, fa0
532; CHECKIF-NEXT:    seqz a1, a1
533; CHECKIF-NEXT:    addi a1, a1, -1
534; CHECKIF-NEXT:    and a0, a1, a0
535; CHECKIF-NEXT:    ret
536;
537; CHECKIZFINX-LABEL: test_trunc_si32:
538; CHECKIZFINX:       # %bb.0:
539; CHECKIZFINX-NEXT:    fcvt.w.s a1, a0, rtz
540; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
541; CHECKIZFINX-NEXT:    seqz a0, a0
542; CHECKIZFINX-NEXT:    addi a0, a0, -1
543; CHECKIZFINX-NEXT:    and a0, a0, a1
544; CHECKIZFINX-NEXT:    ret
545  %a = call float @llvm.trunc.f32(float %x)
546  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
547  ret i32 %b
548}
549
550define i64 @test_trunc_si64(float %x) nounwind {
551; RV32IF-LABEL: test_trunc_si64:
552; RV32IF:       # %bb.0:
553; RV32IF-NEXT:    addi sp, sp, -16
554; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
555; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
556; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
557; RV32IF-NEXT:    fmv.s fs0, fa0
558; RV32IF-NEXT:    lui a0, 307200
559; RV32IF-NEXT:    fmv.w.x fa5, a0
560; RV32IF-NEXT:    fabs.s fa4, fa0
561; RV32IF-NEXT:    flt.s a0, fa4, fa5
562; RV32IF-NEXT:    beqz a0, .LBB9_2
563; RV32IF-NEXT:  # %bb.1:
564; RV32IF-NEXT:    fcvt.w.s a0, fs0, rtz
565; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
566; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
567; RV32IF-NEXT:  .LBB9_2:
568; RV32IF-NEXT:    lui a0, 913408
569; RV32IF-NEXT:    fmv.w.x fa5, a0
570; RV32IF-NEXT:    fle.s s0, fa5, fs0
571; RV32IF-NEXT:    fmv.s fa0, fs0
572; RV32IF-NEXT:    call __fixsfdi
573; RV32IF-NEXT:    lui a3, 524288
574; RV32IF-NEXT:    lui a2, 524288
575; RV32IF-NEXT:    beqz s0, .LBB9_4
576; RV32IF-NEXT:  # %bb.3:
577; RV32IF-NEXT:    mv a2, a1
578; RV32IF-NEXT:  .LBB9_4:
579; RV32IF-NEXT:    lui a1, %hi(.LCPI9_0)
580; RV32IF-NEXT:    flw fa5, %lo(.LCPI9_0)(a1)
581; RV32IF-NEXT:    flt.s a1, fa5, fs0
582; RV32IF-NEXT:    beqz a1, .LBB9_6
583; RV32IF-NEXT:  # %bb.5:
584; RV32IF-NEXT:    addi a2, a3, -1
585; RV32IF-NEXT:  .LBB9_6:
586; RV32IF-NEXT:    feq.s a3, fs0, fs0
587; RV32IF-NEXT:    neg a4, s0
588; RV32IF-NEXT:    neg a5, a1
589; RV32IF-NEXT:    neg a3, a3
590; RV32IF-NEXT:    and a0, a4, a0
591; RV32IF-NEXT:    and a1, a3, a2
592; RV32IF-NEXT:    or a0, a5, a0
593; RV32IF-NEXT:    and a0, a3, a0
594; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
595; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
596; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
597; RV32IF-NEXT:    addi sp, sp, 16
598; RV32IF-NEXT:    ret
599;
600; RV64IF-LABEL: test_trunc_si64:
601; RV64IF:       # %bb.0:
602; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
603; RV64IF-NEXT:    feq.s a1, fa0, fa0
604; RV64IF-NEXT:    seqz a1, a1
605; RV64IF-NEXT:    addi a1, a1, -1
606; RV64IF-NEXT:    and a0, a1, a0
607; RV64IF-NEXT:    ret
608;
609; RV32IZFINX-LABEL: test_trunc_si64:
610; RV32IZFINX:       # %bb.0:
611; RV32IZFINX-NEXT:    addi sp, sp, -16
612; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
613; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
614; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
615; RV32IZFINX-NEXT:    mv s0, a0
616; RV32IZFINX-NEXT:    lui a0, 307200
617; RV32IZFINX-NEXT:    fabs.s a1, s0
618; RV32IZFINX-NEXT:    flt.s a0, a1, a0
619; RV32IZFINX-NEXT:    beqz a0, .LBB9_2
620; RV32IZFINX-NEXT:  # %bb.1:
621; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rtz
622; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rtz
623; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
624; RV32IZFINX-NEXT:  .LBB9_2:
625; RV32IZFINX-NEXT:    lui a0, 913408
626; RV32IZFINX-NEXT:    fle.s s1, a0, s0
627; RV32IZFINX-NEXT:    mv a0, s0
628; RV32IZFINX-NEXT:    call __fixsfdi
629; RV32IZFINX-NEXT:    lui a3, 524288
630; RV32IZFINX-NEXT:    lui a2, 524288
631; RV32IZFINX-NEXT:    beqz s1, .LBB9_4
632; RV32IZFINX-NEXT:  # %bb.3:
633; RV32IZFINX-NEXT:    mv a2, a1
634; RV32IZFINX-NEXT:  .LBB9_4:
635; RV32IZFINX-NEXT:    lui a1, 389120
636; RV32IZFINX-NEXT:    addi a1, a1, -1
637; RV32IZFINX-NEXT:    flt.s a1, a1, s0
638; RV32IZFINX-NEXT:    beqz a1, .LBB9_6
639; RV32IZFINX-NEXT:  # %bb.5:
640; RV32IZFINX-NEXT:    addi a2, a3, -1
641; RV32IZFINX-NEXT:  .LBB9_6:
642; RV32IZFINX-NEXT:    feq.s a3, s0, s0
643; RV32IZFINX-NEXT:    neg a4, s1
644; RV32IZFINX-NEXT:    neg a5, a1
645; RV32IZFINX-NEXT:    neg a3, a3
646; RV32IZFINX-NEXT:    and a0, a4, a0
647; RV32IZFINX-NEXT:    and a1, a3, a2
648; RV32IZFINX-NEXT:    or a0, a5, a0
649; RV32IZFINX-NEXT:    and a0, a3, a0
650; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
651; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
652; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
653; RV32IZFINX-NEXT:    addi sp, sp, 16
654; RV32IZFINX-NEXT:    ret
655;
656; RV64IZFINX-LABEL: test_trunc_si64:
657; RV64IZFINX:       # %bb.0:
658; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rtz
659; RV64IZFINX-NEXT:    feq.s a0, a0, a0
660; RV64IZFINX-NEXT:    seqz a0, a0
661; RV64IZFINX-NEXT:    addi a0, a0, -1
662; RV64IZFINX-NEXT:    and a0, a0, a1
663; RV64IZFINX-NEXT:    ret
664  %a = call float @llvm.trunc.f32(float %x)
665  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
666  ret i64 %b
667}
668
669define signext i32 @test_trunc_ui32(float %x) {
670; CHECKIF-LABEL: test_trunc_ui32:
671; CHECKIF:       # %bb.0:
672; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
673; CHECKIF-NEXT:    feq.s a1, fa0, fa0
674; CHECKIF-NEXT:    seqz a1, a1
675; CHECKIF-NEXT:    addi a1, a1, -1
676; CHECKIF-NEXT:    and a0, a1, a0
677; CHECKIF-NEXT:    ret
678;
679; CHECKIZFINX-LABEL: test_trunc_ui32:
680; CHECKIZFINX:       # %bb.0:
681; CHECKIZFINX-NEXT:    fcvt.wu.s a1, a0, rtz
682; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
683; CHECKIZFINX-NEXT:    seqz a0, a0
684; CHECKIZFINX-NEXT:    addi a0, a0, -1
685; CHECKIZFINX-NEXT:    and a0, a0, a1
686; CHECKIZFINX-NEXT:    ret
687  %a = call float @llvm.trunc.f32(float %x)
688  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
689  ret i32 %b
690}
691
692define i64 @test_trunc_ui64(float %x) nounwind {
693; RV32IF-LABEL: test_trunc_ui64:
694; RV32IF:       # %bb.0:
695; RV32IF-NEXT:    addi sp, sp, -16
696; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
697; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
698; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
699; RV32IF-NEXT:    fmv.s fs0, fa0
700; RV32IF-NEXT:    lui a0, 307200
701; RV32IF-NEXT:    fmv.w.x fa5, a0
702; RV32IF-NEXT:    fabs.s fa4, fa0
703; RV32IF-NEXT:    flt.s a0, fa4, fa5
704; RV32IF-NEXT:    beqz a0, .LBB11_2
705; RV32IF-NEXT:  # %bb.1:
706; RV32IF-NEXT:    fcvt.w.s a0, fs0, rtz
707; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
708; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
709; RV32IF-NEXT:  .LBB11_2:
710; RV32IF-NEXT:    fmv.w.x fa5, zero
711; RV32IF-NEXT:    fle.s a0, fa5, fs0
712; RV32IF-NEXT:    neg s0, a0
713; RV32IF-NEXT:    fmv.s fa0, fs0
714; RV32IF-NEXT:    call __fixunssfdi
715; RV32IF-NEXT:    lui a2, %hi(.LCPI11_0)
716; RV32IF-NEXT:    flw fa5, %lo(.LCPI11_0)(a2)
717; RV32IF-NEXT:    and a0, s0, a0
718; RV32IF-NEXT:    and a1, s0, a1
719; RV32IF-NEXT:    flt.s a2, fa5, fs0
720; RV32IF-NEXT:    neg a2, a2
721; RV32IF-NEXT:    or a0, a2, a0
722; RV32IF-NEXT:    or a1, a2, a1
723; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
724; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
725; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
726; RV32IF-NEXT:    addi sp, sp, 16
727; RV32IF-NEXT:    ret
728;
729; RV64IF-LABEL: test_trunc_ui64:
730; RV64IF:       # %bb.0:
731; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
732; RV64IF-NEXT:    feq.s a1, fa0, fa0
733; RV64IF-NEXT:    seqz a1, a1
734; RV64IF-NEXT:    addi a1, a1, -1
735; RV64IF-NEXT:    and a0, a1, a0
736; RV64IF-NEXT:    ret
737;
738; RV32IZFINX-LABEL: test_trunc_ui64:
739; RV32IZFINX:       # %bb.0:
740; RV32IZFINX-NEXT:    addi sp, sp, -16
741; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
742; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
743; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
744; RV32IZFINX-NEXT:    mv s0, a0
745; RV32IZFINX-NEXT:    lui a0, 307200
746; RV32IZFINX-NEXT:    fabs.s a1, s0
747; RV32IZFINX-NEXT:    flt.s a0, a1, a0
748; RV32IZFINX-NEXT:    beqz a0, .LBB11_2
749; RV32IZFINX-NEXT:  # %bb.1:
750; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rtz
751; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rtz
752; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
753; RV32IZFINX-NEXT:  .LBB11_2:
754; RV32IZFINX-NEXT:    fle.s a0, zero, s0
755; RV32IZFINX-NEXT:    neg s1, a0
756; RV32IZFINX-NEXT:    mv a0, s0
757; RV32IZFINX-NEXT:    call __fixunssfdi
758; RV32IZFINX-NEXT:    and a0, s1, a0
759; RV32IZFINX-NEXT:    lui a2, 391168
760; RV32IZFINX-NEXT:    and a1, s1, a1
761; RV32IZFINX-NEXT:    addi a2, a2, -1
762; RV32IZFINX-NEXT:    flt.s a2, a2, s0
763; RV32IZFINX-NEXT:    neg a2, a2
764; RV32IZFINX-NEXT:    or a0, a2, a0
765; RV32IZFINX-NEXT:    or a1, a2, a1
766; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
767; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
768; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
769; RV32IZFINX-NEXT:    addi sp, sp, 16
770; RV32IZFINX-NEXT:    ret
771;
772; RV64IZFINX-LABEL: test_trunc_ui64:
773; RV64IZFINX:       # %bb.0:
774; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rtz
775; RV64IZFINX-NEXT:    feq.s a0, a0, a0
776; RV64IZFINX-NEXT:    seqz a0, a0
777; RV64IZFINX-NEXT:    addi a0, a0, -1
778; RV64IZFINX-NEXT:    and a0, a0, a1
779; RV64IZFINX-NEXT:    ret
780  %a = call float @llvm.trunc.f32(float %x)
781  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
782  ret i64 %b
783}
784
785define signext i32 @test_round_si32(float %x) {
786; CHECKIF-LABEL: test_round_si32:
787; CHECKIF:       # %bb.0:
788; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rmm
789; CHECKIF-NEXT:    feq.s a1, fa0, fa0
790; CHECKIF-NEXT:    seqz a1, a1
791; CHECKIF-NEXT:    addi a1, a1, -1
792; CHECKIF-NEXT:    and a0, a1, a0
793; CHECKIF-NEXT:    ret
794;
795; CHECKIZFINX-LABEL: test_round_si32:
796; CHECKIZFINX:       # %bb.0:
797; CHECKIZFINX-NEXT:    fcvt.w.s a1, a0, rmm
798; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
799; CHECKIZFINX-NEXT:    seqz a0, a0
800; CHECKIZFINX-NEXT:    addi a0, a0, -1
801; CHECKIZFINX-NEXT:    and a0, a0, a1
802; CHECKIZFINX-NEXT:    ret
803  %a = call float @llvm.round.f32(float %x)
804  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
805  ret i32 %b
806}
807
808define i64 @test_round_si64(float %x) nounwind {
809; RV32IF-LABEL: test_round_si64:
810; RV32IF:       # %bb.0:
811; RV32IF-NEXT:    addi sp, sp, -16
812; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
813; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
814; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
815; RV32IF-NEXT:    fmv.s fs0, fa0
816; RV32IF-NEXT:    lui a0, 307200
817; RV32IF-NEXT:    fmv.w.x fa5, a0
818; RV32IF-NEXT:    fabs.s fa4, fa0
819; RV32IF-NEXT:    flt.s a0, fa4, fa5
820; RV32IF-NEXT:    beqz a0, .LBB13_2
821; RV32IF-NEXT:  # %bb.1:
822; RV32IF-NEXT:    fcvt.w.s a0, fs0, rmm
823; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
824; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
825; RV32IF-NEXT:  .LBB13_2:
826; RV32IF-NEXT:    lui a0, 913408
827; RV32IF-NEXT:    fmv.w.x fa5, a0
828; RV32IF-NEXT:    fle.s s0, fa5, fs0
829; RV32IF-NEXT:    fmv.s fa0, fs0
830; RV32IF-NEXT:    call __fixsfdi
831; RV32IF-NEXT:    lui a3, 524288
832; RV32IF-NEXT:    lui a2, 524288
833; RV32IF-NEXT:    beqz s0, .LBB13_4
834; RV32IF-NEXT:  # %bb.3:
835; RV32IF-NEXT:    mv a2, a1
836; RV32IF-NEXT:  .LBB13_4:
837; RV32IF-NEXT:    lui a1, %hi(.LCPI13_0)
838; RV32IF-NEXT:    flw fa5, %lo(.LCPI13_0)(a1)
839; RV32IF-NEXT:    flt.s a1, fa5, fs0
840; RV32IF-NEXT:    beqz a1, .LBB13_6
841; RV32IF-NEXT:  # %bb.5:
842; RV32IF-NEXT:    addi a2, a3, -1
843; RV32IF-NEXT:  .LBB13_6:
844; RV32IF-NEXT:    feq.s a3, fs0, fs0
845; RV32IF-NEXT:    neg a4, s0
846; RV32IF-NEXT:    neg a5, a1
847; RV32IF-NEXT:    neg a3, a3
848; RV32IF-NEXT:    and a0, a4, a0
849; RV32IF-NEXT:    and a1, a3, a2
850; RV32IF-NEXT:    or a0, a5, a0
851; RV32IF-NEXT:    and a0, a3, a0
852; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
853; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
854; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
855; RV32IF-NEXT:    addi sp, sp, 16
856; RV32IF-NEXT:    ret
857;
858; RV64IF-LABEL: test_round_si64:
859; RV64IF:       # %bb.0:
860; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
861; RV64IF-NEXT:    feq.s a1, fa0, fa0
862; RV64IF-NEXT:    seqz a1, a1
863; RV64IF-NEXT:    addi a1, a1, -1
864; RV64IF-NEXT:    and a0, a1, a0
865; RV64IF-NEXT:    ret
866;
867; RV32IZFINX-LABEL: test_round_si64:
868; RV32IZFINX:       # %bb.0:
869; RV32IZFINX-NEXT:    addi sp, sp, -16
870; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
871; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
872; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
873; RV32IZFINX-NEXT:    mv s0, a0
874; RV32IZFINX-NEXT:    lui a0, 307200
875; RV32IZFINX-NEXT:    fabs.s a1, s0
876; RV32IZFINX-NEXT:    flt.s a0, a1, a0
877; RV32IZFINX-NEXT:    beqz a0, .LBB13_2
878; RV32IZFINX-NEXT:  # %bb.1:
879; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rmm
880; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rmm
881; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
882; RV32IZFINX-NEXT:  .LBB13_2:
883; RV32IZFINX-NEXT:    lui a0, 913408
884; RV32IZFINX-NEXT:    fle.s s1, a0, s0
885; RV32IZFINX-NEXT:    mv a0, s0
886; RV32IZFINX-NEXT:    call __fixsfdi
887; RV32IZFINX-NEXT:    lui a3, 524288
888; RV32IZFINX-NEXT:    lui a2, 524288
889; RV32IZFINX-NEXT:    beqz s1, .LBB13_4
890; RV32IZFINX-NEXT:  # %bb.3:
891; RV32IZFINX-NEXT:    mv a2, a1
892; RV32IZFINX-NEXT:  .LBB13_4:
893; RV32IZFINX-NEXT:    lui a1, 389120
894; RV32IZFINX-NEXT:    addi a1, a1, -1
895; RV32IZFINX-NEXT:    flt.s a1, a1, s0
896; RV32IZFINX-NEXT:    beqz a1, .LBB13_6
897; RV32IZFINX-NEXT:  # %bb.5:
898; RV32IZFINX-NEXT:    addi a2, a3, -1
899; RV32IZFINX-NEXT:  .LBB13_6:
900; RV32IZFINX-NEXT:    feq.s a3, s0, s0
901; RV32IZFINX-NEXT:    neg a4, s1
902; RV32IZFINX-NEXT:    neg a5, a1
903; RV32IZFINX-NEXT:    neg a3, a3
904; RV32IZFINX-NEXT:    and a0, a4, a0
905; RV32IZFINX-NEXT:    and a1, a3, a2
906; RV32IZFINX-NEXT:    or a0, a5, a0
907; RV32IZFINX-NEXT:    and a0, a3, a0
908; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
909; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
910; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
911; RV32IZFINX-NEXT:    addi sp, sp, 16
912; RV32IZFINX-NEXT:    ret
913;
914; RV64IZFINX-LABEL: test_round_si64:
915; RV64IZFINX:       # %bb.0:
916; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rmm
917; RV64IZFINX-NEXT:    feq.s a0, a0, a0
918; RV64IZFINX-NEXT:    seqz a0, a0
919; RV64IZFINX-NEXT:    addi a0, a0, -1
920; RV64IZFINX-NEXT:    and a0, a0, a1
921; RV64IZFINX-NEXT:    ret
922  %a = call float @llvm.round.f32(float %x)
923  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
924  ret i64 %b
925}
926
927define signext i32 @test_round_ui32(float %x) {
928; CHECKIF-LABEL: test_round_ui32:
929; CHECKIF:       # %bb.0:
930; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rmm
931; CHECKIF-NEXT:    feq.s a1, fa0, fa0
932; CHECKIF-NEXT:    seqz a1, a1
933; CHECKIF-NEXT:    addi a1, a1, -1
934; CHECKIF-NEXT:    and a0, a1, a0
935; CHECKIF-NEXT:    ret
936;
937; CHECKIZFINX-LABEL: test_round_ui32:
938; CHECKIZFINX:       # %bb.0:
939; CHECKIZFINX-NEXT:    fcvt.wu.s a1, a0, rmm
940; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
941; CHECKIZFINX-NEXT:    seqz a0, a0
942; CHECKIZFINX-NEXT:    addi a0, a0, -1
943; CHECKIZFINX-NEXT:    and a0, a0, a1
944; CHECKIZFINX-NEXT:    ret
945  %a = call float @llvm.round.f32(float %x)
946  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
947  ret i32 %b
948}
949
950define i64 @test_round_ui64(float %x) nounwind {
951; RV32IF-LABEL: test_round_ui64:
952; RV32IF:       # %bb.0:
953; RV32IF-NEXT:    addi sp, sp, -16
954; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
955; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
956; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
957; RV32IF-NEXT:    fmv.s fs0, fa0
958; RV32IF-NEXT:    lui a0, 307200
959; RV32IF-NEXT:    fmv.w.x fa5, a0
960; RV32IF-NEXT:    fabs.s fa4, fa0
961; RV32IF-NEXT:    flt.s a0, fa4, fa5
962; RV32IF-NEXT:    beqz a0, .LBB15_2
963; RV32IF-NEXT:  # %bb.1:
964; RV32IF-NEXT:    fcvt.w.s a0, fs0, rmm
965; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
966; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
967; RV32IF-NEXT:  .LBB15_2:
968; RV32IF-NEXT:    fmv.w.x fa5, zero
969; RV32IF-NEXT:    fle.s a0, fa5, fs0
970; RV32IF-NEXT:    neg s0, a0
971; RV32IF-NEXT:    fmv.s fa0, fs0
972; RV32IF-NEXT:    call __fixunssfdi
973; RV32IF-NEXT:    lui a2, %hi(.LCPI15_0)
974; RV32IF-NEXT:    flw fa5, %lo(.LCPI15_0)(a2)
975; RV32IF-NEXT:    and a0, s0, a0
976; RV32IF-NEXT:    and a1, s0, a1
977; RV32IF-NEXT:    flt.s a2, fa5, fs0
978; RV32IF-NEXT:    neg a2, a2
979; RV32IF-NEXT:    or a0, a2, a0
980; RV32IF-NEXT:    or a1, a2, a1
981; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
982; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
983; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
984; RV32IF-NEXT:    addi sp, sp, 16
985; RV32IF-NEXT:    ret
986;
987; RV64IF-LABEL: test_round_ui64:
988; RV64IF:       # %bb.0:
989; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
990; RV64IF-NEXT:    feq.s a1, fa0, fa0
991; RV64IF-NEXT:    seqz a1, a1
992; RV64IF-NEXT:    addi a1, a1, -1
993; RV64IF-NEXT:    and a0, a1, a0
994; RV64IF-NEXT:    ret
995;
996; RV32IZFINX-LABEL: test_round_ui64:
997; RV32IZFINX:       # %bb.0:
998; RV32IZFINX-NEXT:    addi sp, sp, -16
999; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1000; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1001; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1002; RV32IZFINX-NEXT:    mv s0, a0
1003; RV32IZFINX-NEXT:    lui a0, 307200
1004; RV32IZFINX-NEXT:    fabs.s a1, s0
1005; RV32IZFINX-NEXT:    flt.s a0, a1, a0
1006; RV32IZFINX-NEXT:    beqz a0, .LBB15_2
1007; RV32IZFINX-NEXT:  # %bb.1:
1008; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rmm
1009; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rmm
1010; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
1011; RV32IZFINX-NEXT:  .LBB15_2:
1012; RV32IZFINX-NEXT:    fle.s a0, zero, s0
1013; RV32IZFINX-NEXT:    neg s1, a0
1014; RV32IZFINX-NEXT:    mv a0, s0
1015; RV32IZFINX-NEXT:    call __fixunssfdi
1016; RV32IZFINX-NEXT:    and a0, s1, a0
1017; RV32IZFINX-NEXT:    lui a2, 391168
1018; RV32IZFINX-NEXT:    and a1, s1, a1
1019; RV32IZFINX-NEXT:    addi a2, a2, -1
1020; RV32IZFINX-NEXT:    flt.s a2, a2, s0
1021; RV32IZFINX-NEXT:    neg a2, a2
1022; RV32IZFINX-NEXT:    or a0, a2, a0
1023; RV32IZFINX-NEXT:    or a1, a2, a1
1024; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1025; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1026; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1027; RV32IZFINX-NEXT:    addi sp, sp, 16
1028; RV32IZFINX-NEXT:    ret
1029;
1030; RV64IZFINX-LABEL: test_round_ui64:
1031; RV64IZFINX:       # %bb.0:
1032; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rmm
1033; RV64IZFINX-NEXT:    feq.s a0, a0, a0
1034; RV64IZFINX-NEXT:    seqz a0, a0
1035; RV64IZFINX-NEXT:    addi a0, a0, -1
1036; RV64IZFINX-NEXT:    and a0, a0, a1
1037; RV64IZFINX-NEXT:    ret
1038  %a = call float @llvm.round.f32(float %x)
1039  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
1040  ret i64 %b
1041}
1042
1043define signext i32 @test_roundeven_si32(float %x) {
1044; CHECKIF-LABEL: test_roundeven_si32:
1045; CHECKIF:       # %bb.0:
1046; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rne
1047; CHECKIF-NEXT:    feq.s a1, fa0, fa0
1048; CHECKIF-NEXT:    seqz a1, a1
1049; CHECKIF-NEXT:    addi a1, a1, -1
1050; CHECKIF-NEXT:    and a0, a1, a0
1051; CHECKIF-NEXT:    ret
1052;
1053; CHECKIZFINX-LABEL: test_roundeven_si32:
1054; CHECKIZFINX:       # %bb.0:
1055; CHECKIZFINX-NEXT:    fcvt.w.s a1, a0, rne
1056; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
1057; CHECKIZFINX-NEXT:    seqz a0, a0
1058; CHECKIZFINX-NEXT:    addi a0, a0, -1
1059; CHECKIZFINX-NEXT:    and a0, a0, a1
1060; CHECKIZFINX-NEXT:    ret
1061  %a = call float @llvm.roundeven.f32(float %x)
1062  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
1063  ret i32 %b
1064}
1065
1066define i64 @test_roundeven_si64(float %x) nounwind {
1067; RV32IF-LABEL: test_roundeven_si64:
1068; RV32IF:       # %bb.0:
1069; RV32IF-NEXT:    addi sp, sp, -16
1070; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1071; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1072; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
1073; RV32IF-NEXT:    fmv.s fs0, fa0
1074; RV32IF-NEXT:    lui a0, 307200
1075; RV32IF-NEXT:    fmv.w.x fa5, a0
1076; RV32IF-NEXT:    fabs.s fa4, fa0
1077; RV32IF-NEXT:    flt.s a0, fa4, fa5
1078; RV32IF-NEXT:    beqz a0, .LBB17_2
1079; RV32IF-NEXT:  # %bb.1:
1080; RV32IF-NEXT:    fcvt.w.s a0, fs0, rne
1081; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
1082; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
1083; RV32IF-NEXT:  .LBB17_2:
1084; RV32IF-NEXT:    lui a0, 913408
1085; RV32IF-NEXT:    fmv.w.x fa5, a0
1086; RV32IF-NEXT:    fle.s s0, fa5, fs0
1087; RV32IF-NEXT:    fmv.s fa0, fs0
1088; RV32IF-NEXT:    call __fixsfdi
1089; RV32IF-NEXT:    lui a3, 524288
1090; RV32IF-NEXT:    lui a2, 524288
1091; RV32IF-NEXT:    beqz s0, .LBB17_4
1092; RV32IF-NEXT:  # %bb.3:
1093; RV32IF-NEXT:    mv a2, a1
1094; RV32IF-NEXT:  .LBB17_4:
1095; RV32IF-NEXT:    lui a1, %hi(.LCPI17_0)
1096; RV32IF-NEXT:    flw fa5, %lo(.LCPI17_0)(a1)
1097; RV32IF-NEXT:    flt.s a1, fa5, fs0
1098; RV32IF-NEXT:    beqz a1, .LBB17_6
1099; RV32IF-NEXT:  # %bb.5:
1100; RV32IF-NEXT:    addi a2, a3, -1
1101; RV32IF-NEXT:  .LBB17_6:
1102; RV32IF-NEXT:    feq.s a3, fs0, fs0
1103; RV32IF-NEXT:    neg a4, s0
1104; RV32IF-NEXT:    neg a5, a1
1105; RV32IF-NEXT:    neg a3, a3
1106; RV32IF-NEXT:    and a0, a4, a0
1107; RV32IF-NEXT:    and a1, a3, a2
1108; RV32IF-NEXT:    or a0, a5, a0
1109; RV32IF-NEXT:    and a0, a3, a0
1110; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1111; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1112; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
1113; RV32IF-NEXT:    addi sp, sp, 16
1114; RV32IF-NEXT:    ret
1115;
1116; RV64IF-LABEL: test_roundeven_si64:
1117; RV64IF:       # %bb.0:
1118; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
1119; RV64IF-NEXT:    feq.s a1, fa0, fa0
1120; RV64IF-NEXT:    seqz a1, a1
1121; RV64IF-NEXT:    addi a1, a1, -1
1122; RV64IF-NEXT:    and a0, a1, a0
1123; RV64IF-NEXT:    ret
1124;
1125; RV32IZFINX-LABEL: test_roundeven_si64:
1126; RV32IZFINX:       # %bb.0:
1127; RV32IZFINX-NEXT:    addi sp, sp, -16
1128; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1129; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1130; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1131; RV32IZFINX-NEXT:    mv s0, a0
1132; RV32IZFINX-NEXT:    lui a0, 307200
1133; RV32IZFINX-NEXT:    fabs.s a1, s0
1134; RV32IZFINX-NEXT:    flt.s a0, a1, a0
1135; RV32IZFINX-NEXT:    beqz a0, .LBB17_2
1136; RV32IZFINX-NEXT:  # %bb.1:
1137; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rne
1138; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rne
1139; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
1140; RV32IZFINX-NEXT:  .LBB17_2:
1141; RV32IZFINX-NEXT:    lui a0, 913408
1142; RV32IZFINX-NEXT:    fle.s s1, a0, s0
1143; RV32IZFINX-NEXT:    mv a0, s0
1144; RV32IZFINX-NEXT:    call __fixsfdi
1145; RV32IZFINX-NEXT:    lui a3, 524288
1146; RV32IZFINX-NEXT:    lui a2, 524288
1147; RV32IZFINX-NEXT:    beqz s1, .LBB17_4
1148; RV32IZFINX-NEXT:  # %bb.3:
1149; RV32IZFINX-NEXT:    mv a2, a1
1150; RV32IZFINX-NEXT:  .LBB17_4:
1151; RV32IZFINX-NEXT:    lui a1, 389120
1152; RV32IZFINX-NEXT:    addi a1, a1, -1
1153; RV32IZFINX-NEXT:    flt.s a1, a1, s0
1154; RV32IZFINX-NEXT:    beqz a1, .LBB17_6
1155; RV32IZFINX-NEXT:  # %bb.5:
1156; RV32IZFINX-NEXT:    addi a2, a3, -1
1157; RV32IZFINX-NEXT:  .LBB17_6:
1158; RV32IZFINX-NEXT:    feq.s a3, s0, s0
1159; RV32IZFINX-NEXT:    neg a4, s1
1160; RV32IZFINX-NEXT:    neg a5, a1
1161; RV32IZFINX-NEXT:    neg a3, a3
1162; RV32IZFINX-NEXT:    and a0, a4, a0
1163; RV32IZFINX-NEXT:    and a1, a3, a2
1164; RV32IZFINX-NEXT:    or a0, a5, a0
1165; RV32IZFINX-NEXT:    and a0, a3, a0
1166; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1167; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1168; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1169; RV32IZFINX-NEXT:    addi sp, sp, 16
1170; RV32IZFINX-NEXT:    ret
1171;
1172; RV64IZFINX-LABEL: test_roundeven_si64:
1173; RV64IZFINX:       # %bb.0:
1174; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rne
1175; RV64IZFINX-NEXT:    feq.s a0, a0, a0
1176; RV64IZFINX-NEXT:    seqz a0, a0
1177; RV64IZFINX-NEXT:    addi a0, a0, -1
1178; RV64IZFINX-NEXT:    and a0, a0, a1
1179; RV64IZFINX-NEXT:    ret
1180  %a = call float @llvm.roundeven.f32(float %x)
1181  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
1182  ret i64 %b
1183}
1184
1185define signext i32 @test_roundeven_ui32(float %x) {
1186; CHECKIF-LABEL: test_roundeven_ui32:
1187; CHECKIF:       # %bb.0:
1188; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rne
1189; CHECKIF-NEXT:    feq.s a1, fa0, fa0
1190; CHECKIF-NEXT:    seqz a1, a1
1191; CHECKIF-NEXT:    addi a1, a1, -1
1192; CHECKIF-NEXT:    and a0, a1, a0
1193; CHECKIF-NEXT:    ret
1194;
1195; CHECKIZFINX-LABEL: test_roundeven_ui32:
1196; CHECKIZFINX:       # %bb.0:
1197; CHECKIZFINX-NEXT:    fcvt.wu.s a1, a0, rne
1198; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
1199; CHECKIZFINX-NEXT:    seqz a0, a0
1200; CHECKIZFINX-NEXT:    addi a0, a0, -1
1201; CHECKIZFINX-NEXT:    and a0, a0, a1
1202; CHECKIZFINX-NEXT:    ret
1203  %a = call float @llvm.roundeven.f32(float %x)
1204  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
1205  ret i32 %b
1206}
1207
1208define i64 @test_roundeven_ui64(float %x) nounwind {
1209; RV32IF-LABEL: test_roundeven_ui64:
1210; RV32IF:       # %bb.0:
1211; RV32IF-NEXT:    addi sp, sp, -16
1212; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1213; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1214; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
1215; RV32IF-NEXT:    fmv.s fs0, fa0
1216; RV32IF-NEXT:    lui a0, 307200
1217; RV32IF-NEXT:    fmv.w.x fa5, a0
1218; RV32IF-NEXT:    fabs.s fa4, fa0
1219; RV32IF-NEXT:    flt.s a0, fa4, fa5
1220; RV32IF-NEXT:    beqz a0, .LBB19_2
1221; RV32IF-NEXT:  # %bb.1:
1222; RV32IF-NEXT:    fcvt.w.s a0, fs0, rne
1223; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
1224; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
1225; RV32IF-NEXT:  .LBB19_2:
1226; RV32IF-NEXT:    fmv.w.x fa5, zero
1227; RV32IF-NEXT:    fle.s a0, fa5, fs0
1228; RV32IF-NEXT:    neg s0, a0
1229; RV32IF-NEXT:    fmv.s fa0, fs0
1230; RV32IF-NEXT:    call __fixunssfdi
1231; RV32IF-NEXT:    lui a2, %hi(.LCPI19_0)
1232; RV32IF-NEXT:    flw fa5, %lo(.LCPI19_0)(a2)
1233; RV32IF-NEXT:    and a0, s0, a0
1234; RV32IF-NEXT:    and a1, s0, a1
1235; RV32IF-NEXT:    flt.s a2, fa5, fs0
1236; RV32IF-NEXT:    neg a2, a2
1237; RV32IF-NEXT:    or a0, a2, a0
1238; RV32IF-NEXT:    or a1, a2, a1
1239; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1240; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1241; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
1242; RV32IF-NEXT:    addi sp, sp, 16
1243; RV32IF-NEXT:    ret
1244;
1245; RV64IF-LABEL: test_roundeven_ui64:
1246; RV64IF:       # %bb.0:
1247; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
1248; RV64IF-NEXT:    feq.s a1, fa0, fa0
1249; RV64IF-NEXT:    seqz a1, a1
1250; RV64IF-NEXT:    addi a1, a1, -1
1251; RV64IF-NEXT:    and a0, a1, a0
1252; RV64IF-NEXT:    ret
1253;
1254; RV32IZFINX-LABEL: test_roundeven_ui64:
1255; RV32IZFINX:       # %bb.0:
1256; RV32IZFINX-NEXT:    addi sp, sp, -16
1257; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1258; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1259; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1260; RV32IZFINX-NEXT:    mv s0, a0
1261; RV32IZFINX-NEXT:    lui a0, 307200
1262; RV32IZFINX-NEXT:    fabs.s a1, s0
1263; RV32IZFINX-NEXT:    flt.s a0, a1, a0
1264; RV32IZFINX-NEXT:    beqz a0, .LBB19_2
1265; RV32IZFINX-NEXT:  # %bb.1:
1266; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rne
1267; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rne
1268; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
1269; RV32IZFINX-NEXT:  .LBB19_2:
1270; RV32IZFINX-NEXT:    fle.s a0, zero, s0
1271; RV32IZFINX-NEXT:    neg s1, a0
1272; RV32IZFINX-NEXT:    mv a0, s0
1273; RV32IZFINX-NEXT:    call __fixunssfdi
1274; RV32IZFINX-NEXT:    and a0, s1, a0
1275; RV32IZFINX-NEXT:    lui a2, 391168
1276; RV32IZFINX-NEXT:    and a1, s1, a1
1277; RV32IZFINX-NEXT:    addi a2, a2, -1
1278; RV32IZFINX-NEXT:    flt.s a2, a2, s0
1279; RV32IZFINX-NEXT:    neg a2, a2
1280; RV32IZFINX-NEXT:    or a0, a2, a0
1281; RV32IZFINX-NEXT:    or a1, a2, a1
1282; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1283; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1284; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1285; RV32IZFINX-NEXT:    addi sp, sp, 16
1286; RV32IZFINX-NEXT:    ret
1287;
1288; RV64IZFINX-LABEL: test_roundeven_ui64:
1289; RV64IZFINX:       # %bb.0:
1290; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rne
1291; RV64IZFINX-NEXT:    feq.s a0, a0, a0
1292; RV64IZFINX-NEXT:    seqz a0, a0
1293; RV64IZFINX-NEXT:    addi a0, a0, -1
1294; RV64IZFINX-NEXT:    and a0, a0, a1
1295; RV64IZFINX-NEXT:    ret
1296  %a = call float @llvm.roundeven.f32(float %x)
1297  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
1298  ret i64 %b
1299}
1300
1301define signext i32 @test_rint_si32(float %x) {
1302; CHECKIF-LABEL: test_rint_si32:
1303; CHECKIF:       # %bb.0:
1304; CHECKIF-NEXT:    fcvt.w.s a0, fa0
1305; CHECKIF-NEXT:    feq.s a1, fa0, fa0
1306; CHECKIF-NEXT:    seqz a1, a1
1307; CHECKIF-NEXT:    addi a1, a1, -1
1308; CHECKIF-NEXT:    and a0, a1, a0
1309; CHECKIF-NEXT:    ret
1310;
1311; CHECKIZFINX-LABEL: test_rint_si32:
1312; CHECKIZFINX:       # %bb.0:
1313; CHECKIZFINX-NEXT:    fcvt.w.s a1, a0
1314; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
1315; CHECKIZFINX-NEXT:    seqz a0, a0
1316; CHECKIZFINX-NEXT:    addi a0, a0, -1
1317; CHECKIZFINX-NEXT:    and a0, a0, a1
1318; CHECKIZFINX-NEXT:    ret
1319  %a = call float @llvm.rint.f32(float %x)
1320  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
1321  ret i32 %b
1322}
1323
1324define i64 @test_rint_si64(float %x) nounwind {
1325; RV32IF-LABEL: test_rint_si64:
1326; RV32IF:       # %bb.0:
1327; RV32IF-NEXT:    addi sp, sp, -16
1328; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1329; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1330; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
1331; RV32IF-NEXT:    fmv.s fs0, fa0
1332; RV32IF-NEXT:    lui a0, 307200
1333; RV32IF-NEXT:    fmv.w.x fa5, a0
1334; RV32IF-NEXT:    fabs.s fa4, fa0
1335; RV32IF-NEXT:    flt.s a0, fa4, fa5
1336; RV32IF-NEXT:    beqz a0, .LBB21_2
1337; RV32IF-NEXT:  # %bb.1:
1338; RV32IF-NEXT:    fcvt.w.s a0, fs0
1339; RV32IF-NEXT:    fcvt.s.w fa5, a0
1340; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
1341; RV32IF-NEXT:  .LBB21_2:
1342; RV32IF-NEXT:    lui a0, 913408
1343; RV32IF-NEXT:    fmv.w.x fa5, a0
1344; RV32IF-NEXT:    fle.s s0, fa5, fs0
1345; RV32IF-NEXT:    fmv.s fa0, fs0
1346; RV32IF-NEXT:    call __fixsfdi
1347; RV32IF-NEXT:    lui a3, 524288
1348; RV32IF-NEXT:    lui a2, 524288
1349; RV32IF-NEXT:    beqz s0, .LBB21_4
1350; RV32IF-NEXT:  # %bb.3:
1351; RV32IF-NEXT:    mv a2, a1
1352; RV32IF-NEXT:  .LBB21_4:
1353; RV32IF-NEXT:    lui a1, %hi(.LCPI21_0)
1354; RV32IF-NEXT:    flw fa5, %lo(.LCPI21_0)(a1)
1355; RV32IF-NEXT:    flt.s a1, fa5, fs0
1356; RV32IF-NEXT:    beqz a1, .LBB21_6
1357; RV32IF-NEXT:  # %bb.5:
1358; RV32IF-NEXT:    addi a2, a3, -1
1359; RV32IF-NEXT:  .LBB21_6:
1360; RV32IF-NEXT:    feq.s a3, fs0, fs0
1361; RV32IF-NEXT:    neg a4, s0
1362; RV32IF-NEXT:    neg a5, a1
1363; RV32IF-NEXT:    neg a3, a3
1364; RV32IF-NEXT:    and a0, a4, a0
1365; RV32IF-NEXT:    and a1, a3, a2
1366; RV32IF-NEXT:    or a0, a5, a0
1367; RV32IF-NEXT:    and a0, a3, a0
1368; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1369; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1370; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
1371; RV32IF-NEXT:    addi sp, sp, 16
1372; RV32IF-NEXT:    ret
1373;
1374; RV64IF-LABEL: test_rint_si64:
1375; RV64IF:       # %bb.0:
1376; RV64IF-NEXT:    fcvt.l.s a0, fa0
1377; RV64IF-NEXT:    feq.s a1, fa0, fa0
1378; RV64IF-NEXT:    seqz a1, a1
1379; RV64IF-NEXT:    addi a1, a1, -1
1380; RV64IF-NEXT:    and a0, a1, a0
1381; RV64IF-NEXT:    ret
1382;
1383; RV32IZFINX-LABEL: test_rint_si64:
1384; RV32IZFINX:       # %bb.0:
1385; RV32IZFINX-NEXT:    addi sp, sp, -16
1386; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1387; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1388; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1389; RV32IZFINX-NEXT:    mv s0, a0
1390; RV32IZFINX-NEXT:    lui a0, 307200
1391; RV32IZFINX-NEXT:    fabs.s a1, s0
1392; RV32IZFINX-NEXT:    flt.s a0, a1, a0
1393; RV32IZFINX-NEXT:    beqz a0, .LBB21_2
1394; RV32IZFINX-NEXT:  # %bb.1:
1395; RV32IZFINX-NEXT:    fcvt.w.s a0, s0
1396; RV32IZFINX-NEXT:    fcvt.s.w a0, a0
1397; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
1398; RV32IZFINX-NEXT:  .LBB21_2:
1399; RV32IZFINX-NEXT:    lui a0, 913408
1400; RV32IZFINX-NEXT:    fle.s s1, a0, s0
1401; RV32IZFINX-NEXT:    mv a0, s0
1402; RV32IZFINX-NEXT:    call __fixsfdi
1403; RV32IZFINX-NEXT:    lui a3, 524288
1404; RV32IZFINX-NEXT:    lui a2, 524288
1405; RV32IZFINX-NEXT:    beqz s1, .LBB21_4
1406; RV32IZFINX-NEXT:  # %bb.3:
1407; RV32IZFINX-NEXT:    mv a2, a1
1408; RV32IZFINX-NEXT:  .LBB21_4:
1409; RV32IZFINX-NEXT:    lui a1, 389120
1410; RV32IZFINX-NEXT:    addi a1, a1, -1
1411; RV32IZFINX-NEXT:    flt.s a1, a1, s0
1412; RV32IZFINX-NEXT:    beqz a1, .LBB21_6
1413; RV32IZFINX-NEXT:  # %bb.5:
1414; RV32IZFINX-NEXT:    addi a2, a3, -1
1415; RV32IZFINX-NEXT:  .LBB21_6:
1416; RV32IZFINX-NEXT:    feq.s a3, s0, s0
1417; RV32IZFINX-NEXT:    neg a4, s1
1418; RV32IZFINX-NEXT:    neg a5, a1
1419; RV32IZFINX-NEXT:    neg a3, a3
1420; RV32IZFINX-NEXT:    and a0, a4, a0
1421; RV32IZFINX-NEXT:    and a1, a3, a2
1422; RV32IZFINX-NEXT:    or a0, a5, a0
1423; RV32IZFINX-NEXT:    and a0, a3, a0
1424; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1425; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1426; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1427; RV32IZFINX-NEXT:    addi sp, sp, 16
1428; RV32IZFINX-NEXT:    ret
1429;
1430; RV64IZFINX-LABEL: test_rint_si64:
1431; RV64IZFINX:       # %bb.0:
1432; RV64IZFINX-NEXT:    fcvt.l.s a1, a0
1433; RV64IZFINX-NEXT:    feq.s a0, a0, a0
1434; RV64IZFINX-NEXT:    seqz a0, a0
1435; RV64IZFINX-NEXT:    addi a0, a0, -1
1436; RV64IZFINX-NEXT:    and a0, a0, a1
1437; RV64IZFINX-NEXT:    ret
1438  %a = call float @llvm.rint.f32(float %x)
1439  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
1440  ret i64 %b
1441}
1442
1443define signext i32 @test_rint_ui32(float %x) {
1444; CHECKIF-LABEL: test_rint_ui32:
1445; CHECKIF:       # %bb.0:
1446; CHECKIF-NEXT:    fcvt.wu.s a0, fa0
1447; CHECKIF-NEXT:    feq.s a1, fa0, fa0
1448; CHECKIF-NEXT:    seqz a1, a1
1449; CHECKIF-NEXT:    addi a1, a1, -1
1450; CHECKIF-NEXT:    and a0, a1, a0
1451; CHECKIF-NEXT:    ret
1452;
1453; CHECKIZFINX-LABEL: test_rint_ui32:
1454; CHECKIZFINX:       # %bb.0:
1455; CHECKIZFINX-NEXT:    fcvt.wu.s a1, a0
1456; CHECKIZFINX-NEXT:    feq.s a0, a0, a0
1457; CHECKIZFINX-NEXT:    seqz a0, a0
1458; CHECKIZFINX-NEXT:    addi a0, a0, -1
1459; CHECKIZFINX-NEXT:    and a0, a0, a1
1460; CHECKIZFINX-NEXT:    ret
1461  %a = call float @llvm.rint.f32(float %x)
1462  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
1463  ret i32 %b
1464}
1465
1466define i64 @test_rint_ui64(float %x) nounwind {
1467; RV32IF-LABEL: test_rint_ui64:
1468; RV32IF:       # %bb.0:
1469; RV32IF-NEXT:    addi sp, sp, -16
1470; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1471; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1472; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
1473; RV32IF-NEXT:    fmv.s fs0, fa0
1474; RV32IF-NEXT:    lui a0, 307200
1475; RV32IF-NEXT:    fmv.w.x fa5, a0
1476; RV32IF-NEXT:    fabs.s fa4, fa0
1477; RV32IF-NEXT:    flt.s a0, fa4, fa5
1478; RV32IF-NEXT:    beqz a0, .LBB23_2
1479; RV32IF-NEXT:  # %bb.1:
1480; RV32IF-NEXT:    fcvt.w.s a0, fs0
1481; RV32IF-NEXT:    fcvt.s.w fa5, a0
1482; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
1483; RV32IF-NEXT:  .LBB23_2:
1484; RV32IF-NEXT:    fmv.w.x fa5, zero
1485; RV32IF-NEXT:    fle.s a0, fa5, fs0
1486; RV32IF-NEXT:    neg s0, a0
1487; RV32IF-NEXT:    fmv.s fa0, fs0
1488; RV32IF-NEXT:    call __fixunssfdi
1489; RV32IF-NEXT:    lui a2, %hi(.LCPI23_0)
1490; RV32IF-NEXT:    flw fa5, %lo(.LCPI23_0)(a2)
1491; RV32IF-NEXT:    and a0, s0, a0
1492; RV32IF-NEXT:    and a1, s0, a1
1493; RV32IF-NEXT:    flt.s a2, fa5, fs0
1494; RV32IF-NEXT:    neg a2, a2
1495; RV32IF-NEXT:    or a0, a2, a0
1496; RV32IF-NEXT:    or a1, a2, a1
1497; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1498; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1499; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
1500; RV32IF-NEXT:    addi sp, sp, 16
1501; RV32IF-NEXT:    ret
1502;
1503; RV64IF-LABEL: test_rint_ui64:
1504; RV64IF:       # %bb.0:
1505; RV64IF-NEXT:    fcvt.lu.s a0, fa0
1506; RV64IF-NEXT:    feq.s a1, fa0, fa0
1507; RV64IF-NEXT:    seqz a1, a1
1508; RV64IF-NEXT:    addi a1, a1, -1
1509; RV64IF-NEXT:    and a0, a1, a0
1510; RV64IF-NEXT:    ret
1511;
1512; RV32IZFINX-LABEL: test_rint_ui64:
1513; RV32IZFINX:       # %bb.0:
1514; RV32IZFINX-NEXT:    addi sp, sp, -16
1515; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1516; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1517; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1518; RV32IZFINX-NEXT:    mv s0, a0
1519; RV32IZFINX-NEXT:    lui a0, 307200
1520; RV32IZFINX-NEXT:    fabs.s a1, s0
1521; RV32IZFINX-NEXT:    flt.s a0, a1, a0
1522; RV32IZFINX-NEXT:    beqz a0, .LBB23_2
1523; RV32IZFINX-NEXT:  # %bb.1:
1524; RV32IZFINX-NEXT:    fcvt.w.s a0, s0
1525; RV32IZFINX-NEXT:    fcvt.s.w a0, a0
1526; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
1527; RV32IZFINX-NEXT:  .LBB23_2:
1528; RV32IZFINX-NEXT:    fle.s a0, zero, s0
1529; RV32IZFINX-NEXT:    neg s1, a0
1530; RV32IZFINX-NEXT:    mv a0, s0
1531; RV32IZFINX-NEXT:    call __fixunssfdi
1532; RV32IZFINX-NEXT:    and a0, s1, a0
1533; RV32IZFINX-NEXT:    lui a2, 391168
1534; RV32IZFINX-NEXT:    and a1, s1, a1
1535; RV32IZFINX-NEXT:    addi a2, a2, -1
1536; RV32IZFINX-NEXT:    flt.s a2, a2, s0
1537; RV32IZFINX-NEXT:    neg a2, a2
1538; RV32IZFINX-NEXT:    or a0, a2, a0
1539; RV32IZFINX-NEXT:    or a1, a2, a1
1540; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1541; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1542; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1543; RV32IZFINX-NEXT:    addi sp, sp, 16
1544; RV32IZFINX-NEXT:    ret
1545;
1546; RV64IZFINX-LABEL: test_rint_ui64:
1547; RV64IZFINX:       # %bb.0:
1548; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0
1549; RV64IZFINX-NEXT:    feq.s a0, a0, a0
1550; RV64IZFINX-NEXT:    seqz a0, a0
1551; RV64IZFINX-NEXT:    addi a0, a0, -1
1552; RV64IZFINX-NEXT:    and a0, a0, a1
1553; RV64IZFINX-NEXT:    ret
1554  %a = call float @llvm.rint.f32(float %x)
1555  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
1556  ret i64 %b
1557}
1558
1559declare float @llvm.floor.f32(float)
1560declare float @llvm.ceil.f32(float)
1561declare float @llvm.trunc.f32(float)
1562declare float @llvm.round.f32(float)
1563declare float @llvm.roundeven.f32(float)
1564declare float @llvm.rint.f32(float)
1565declare i32 @llvm.fptosi.sat.i32.f32(float)
1566declare i64 @llvm.fptosi.sat.i64.f32(float)
1567declare i32 @llvm.fptoui.sat.i32.f32(float)
1568declare i64 @llvm.fptoui.sat.i64.f32(float)
1569