1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ 3; RUN: -verify-machineinstrs -target-abi=ilp32f \ 4; RUN: | FileCheck -check-prefix=RV32IF %s 5; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \ 6; RUN: -verify-machineinstrs -target-abi=ilp32 \ 7; RUN: | FileCheck -check-prefix=RV32IZFINX %s 8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ 9; RUN: -verify-machineinstrs -target-abi=ilp32f \ 10; RUN: | FileCheck -check-prefix=RV32IF %s 11; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ 12; RUN: -verify-machineinstrs -target-abi=ilp32 \ 13; RUN: | FileCheck -check-prefix=RV32I %s 14; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ 15; RUN: -verify-machineinstrs -target-abi=lp64f \ 16; RUN: | FileCheck -check-prefix=RV64IF %s 17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \ 18; RUN: -verify-machineinstrs -target-abi=lp64 \ 19; RUN: | FileCheck -check-prefix=RV64IZFINX %s 20; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ 21; RUN: -verify-machineinstrs -target-abi=lp64d \ 22; RUN: | FileCheck -check-prefix=RV64IF %s 23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ 24; RUN: -verify-machineinstrs -target-abi=lp64 \ 25; RUN: | FileCheck -check-prefix=RV64I %s 26 27declare float @llvm.minimum.f32(float, float) 28 29define float @fminimum_f32(float %a, float %b) nounwind { 30; RV32IF-LABEL: fminimum_f32: 31; RV32IF: # %bb.0: 32; RV32IF-NEXT: feq.s a0, fa0, fa0 33; RV32IF-NEXT: fmv.s fa5, fa1 34; RV32IF-NEXT: beqz a0, .LBB0_3 35; RV32IF-NEXT: # %bb.1: 36; RV32IF-NEXT: feq.s a0, fa1, fa1 37; RV32IF-NEXT: beqz a0, .LBB0_4 38; RV32IF-NEXT: .LBB0_2: 39; RV32IF-NEXT: fmin.s fa0, fa0, fa5 40; RV32IF-NEXT: ret 41; RV32IF-NEXT: .LBB0_3: 42; RV32IF-NEXT: fmv.s fa5, fa0 43; RV32IF-NEXT: feq.s a0, fa1, fa1 44; RV32IF-NEXT: bnez a0, .LBB0_2 45; RV32IF-NEXT: .LBB0_4: 46; RV32IF-NEXT: fmin.s fa0, fa1, fa5 47; RV32IF-NEXT: ret 48; 49; RV32IZFINX-LABEL: fminimum_f32: 50; RV32IZFINX: # %bb.0: 51; RV32IZFINX-NEXT: feq.s a3, a0, a0 52; RV32IZFINX-NEXT: mv a2, a1 53; RV32IZFINX-NEXT: beqz a3, .LBB0_3 54; RV32IZFINX-NEXT: # %bb.1: 55; RV32IZFINX-NEXT: feq.s a3, a1, a1 56; RV32IZFINX-NEXT: beqz a3, .LBB0_4 57; RV32IZFINX-NEXT: .LBB0_2: 58; RV32IZFINX-NEXT: fmin.s a0, a0, a2 59; RV32IZFINX-NEXT: ret 60; RV32IZFINX-NEXT: .LBB0_3: 61; RV32IZFINX-NEXT: mv a2, a0 62; RV32IZFINX-NEXT: feq.s a3, a1, a1 63; RV32IZFINX-NEXT: bnez a3, .LBB0_2 64; RV32IZFINX-NEXT: .LBB0_4: 65; RV32IZFINX-NEXT: fmin.s a0, a1, a2 66; RV32IZFINX-NEXT: ret 67; 68; RV32I-LABEL: fminimum_f32: 69; RV32I: # %bb.0: 70; RV32I-NEXT: addi sp, sp, -16 71; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 72; RV32I-NEXT: call fminimumf 73; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 74; RV32I-NEXT: addi sp, sp, 16 75; RV32I-NEXT: ret 76; 77; RV64IF-LABEL: fminimum_f32: 78; RV64IF: # %bb.0: 79; RV64IF-NEXT: feq.s a0, fa0, fa0 80; RV64IF-NEXT: fmv.s fa5, fa1 81; RV64IF-NEXT: beqz a0, .LBB0_3 82; RV64IF-NEXT: # %bb.1: 83; RV64IF-NEXT: feq.s a0, fa1, fa1 84; RV64IF-NEXT: beqz a0, .LBB0_4 85; RV64IF-NEXT: .LBB0_2: 86; RV64IF-NEXT: fmin.s fa0, fa0, fa5 87; RV64IF-NEXT: ret 88; RV64IF-NEXT: .LBB0_3: 89; RV64IF-NEXT: fmv.s fa5, fa0 90; RV64IF-NEXT: feq.s a0, fa1, fa1 91; RV64IF-NEXT: bnez a0, .LBB0_2 92; RV64IF-NEXT: .LBB0_4: 93; RV64IF-NEXT: fmin.s fa0, fa1, fa5 94; RV64IF-NEXT: ret 95; 96; RV64IZFINX-LABEL: fminimum_f32: 97; RV64IZFINX: # %bb.0: 98; RV64IZFINX-NEXT: feq.s a3, a0, a0 99; RV64IZFINX-NEXT: mv a2, a1 100; RV64IZFINX-NEXT: beqz a3, .LBB0_3 101; RV64IZFINX-NEXT: # %bb.1: 102; RV64IZFINX-NEXT: feq.s a3, a1, a1 103; RV64IZFINX-NEXT: beqz a3, .LBB0_4 104; RV64IZFINX-NEXT: .LBB0_2: 105; RV64IZFINX-NEXT: fmin.s a0, a0, a2 106; RV64IZFINX-NEXT: ret 107; RV64IZFINX-NEXT: .LBB0_3: 108; RV64IZFINX-NEXT: mv a2, a0 109; RV64IZFINX-NEXT: feq.s a3, a1, a1 110; RV64IZFINX-NEXT: bnez a3, .LBB0_2 111; RV64IZFINX-NEXT: .LBB0_4: 112; RV64IZFINX-NEXT: fmin.s a0, a1, a2 113; RV64IZFINX-NEXT: ret 114; 115; RV64I-LABEL: fminimum_f32: 116; RV64I: # %bb.0: 117; RV64I-NEXT: addi sp, sp, -16 118; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 119; RV64I-NEXT: call fminimumf 120; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 121; RV64I-NEXT: addi sp, sp, 16 122; RV64I-NEXT: ret 123 %1 = call float @llvm.minimum.f32(float %a, float %b) 124 ret float %1 125} 126 127declare float @llvm.maximum.f32(float, float) 128 129define float @fmaximum_f32(float %a, float %b) nounwind { 130; RV32IF-LABEL: fmaximum_f32: 131; RV32IF: # %bb.0: 132; RV32IF-NEXT: feq.s a0, fa0, fa0 133; RV32IF-NEXT: fmv.s fa5, fa1 134; RV32IF-NEXT: beqz a0, .LBB1_3 135; RV32IF-NEXT: # %bb.1: 136; RV32IF-NEXT: feq.s a0, fa1, fa1 137; RV32IF-NEXT: beqz a0, .LBB1_4 138; RV32IF-NEXT: .LBB1_2: 139; RV32IF-NEXT: fmax.s fa0, fa0, fa5 140; RV32IF-NEXT: ret 141; RV32IF-NEXT: .LBB1_3: 142; RV32IF-NEXT: fmv.s fa5, fa0 143; RV32IF-NEXT: feq.s a0, fa1, fa1 144; RV32IF-NEXT: bnez a0, .LBB1_2 145; RV32IF-NEXT: .LBB1_4: 146; RV32IF-NEXT: fmax.s fa0, fa1, fa5 147; RV32IF-NEXT: ret 148; 149; RV32IZFINX-LABEL: fmaximum_f32: 150; RV32IZFINX: # %bb.0: 151; RV32IZFINX-NEXT: feq.s a3, a0, a0 152; RV32IZFINX-NEXT: mv a2, a1 153; RV32IZFINX-NEXT: beqz a3, .LBB1_3 154; RV32IZFINX-NEXT: # %bb.1: 155; RV32IZFINX-NEXT: feq.s a3, a1, a1 156; RV32IZFINX-NEXT: beqz a3, .LBB1_4 157; RV32IZFINX-NEXT: .LBB1_2: 158; RV32IZFINX-NEXT: fmax.s a0, a0, a2 159; RV32IZFINX-NEXT: ret 160; RV32IZFINX-NEXT: .LBB1_3: 161; RV32IZFINX-NEXT: mv a2, a0 162; RV32IZFINX-NEXT: feq.s a3, a1, a1 163; RV32IZFINX-NEXT: bnez a3, .LBB1_2 164; RV32IZFINX-NEXT: .LBB1_4: 165; RV32IZFINX-NEXT: fmax.s a0, a1, a2 166; RV32IZFINX-NEXT: ret 167; 168; RV32I-LABEL: fmaximum_f32: 169; RV32I: # %bb.0: 170; RV32I-NEXT: addi sp, sp, -16 171; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 172; RV32I-NEXT: call fmaximumf 173; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 174; RV32I-NEXT: addi sp, sp, 16 175; RV32I-NEXT: ret 176; 177; RV64IF-LABEL: fmaximum_f32: 178; RV64IF: # %bb.0: 179; RV64IF-NEXT: feq.s a0, fa0, fa0 180; RV64IF-NEXT: fmv.s fa5, fa1 181; RV64IF-NEXT: beqz a0, .LBB1_3 182; RV64IF-NEXT: # %bb.1: 183; RV64IF-NEXT: feq.s a0, fa1, fa1 184; RV64IF-NEXT: beqz a0, .LBB1_4 185; RV64IF-NEXT: .LBB1_2: 186; RV64IF-NEXT: fmax.s fa0, fa0, fa5 187; RV64IF-NEXT: ret 188; RV64IF-NEXT: .LBB1_3: 189; RV64IF-NEXT: fmv.s fa5, fa0 190; RV64IF-NEXT: feq.s a0, fa1, fa1 191; RV64IF-NEXT: bnez a0, .LBB1_2 192; RV64IF-NEXT: .LBB1_4: 193; RV64IF-NEXT: fmax.s fa0, fa1, fa5 194; RV64IF-NEXT: ret 195; 196; RV64IZFINX-LABEL: fmaximum_f32: 197; RV64IZFINX: # %bb.0: 198; RV64IZFINX-NEXT: feq.s a3, a0, a0 199; RV64IZFINX-NEXT: mv a2, a1 200; RV64IZFINX-NEXT: beqz a3, .LBB1_3 201; RV64IZFINX-NEXT: # %bb.1: 202; RV64IZFINX-NEXT: feq.s a3, a1, a1 203; RV64IZFINX-NEXT: beqz a3, .LBB1_4 204; RV64IZFINX-NEXT: .LBB1_2: 205; RV64IZFINX-NEXT: fmax.s a0, a0, a2 206; RV64IZFINX-NEXT: ret 207; RV64IZFINX-NEXT: .LBB1_3: 208; RV64IZFINX-NEXT: mv a2, a0 209; RV64IZFINX-NEXT: feq.s a3, a1, a1 210; RV64IZFINX-NEXT: bnez a3, .LBB1_2 211; RV64IZFINX-NEXT: .LBB1_4: 212; RV64IZFINX-NEXT: fmax.s a0, a1, a2 213; RV64IZFINX-NEXT: ret 214; 215; RV64I-LABEL: fmaximum_f32: 216; RV64I: # %bb.0: 217; RV64I-NEXT: addi sp, sp, -16 218; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 219; RV64I-NEXT: call fmaximumf 220; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 221; RV64I-NEXT: addi sp, sp, 16 222; RV64I-NEXT: ret 223 %1 = call float @llvm.maximum.f32(float %a, float %b) 224 ret float %1 225} 226 227define float @fminimum_nnan_f32(float %a, float %b) nounwind { 228; RV32IF-LABEL: fminimum_nnan_f32: 229; RV32IF: # %bb.0: 230; RV32IF-NEXT: fmin.s fa0, fa0, fa1 231; RV32IF-NEXT: ret 232; 233; RV32IZFINX-LABEL: fminimum_nnan_f32: 234; RV32IZFINX: # %bb.0: 235; RV32IZFINX-NEXT: fmin.s a0, a0, a1 236; RV32IZFINX-NEXT: ret 237; 238; RV32I-LABEL: fminimum_nnan_f32: 239; RV32I: # %bb.0: 240; RV32I-NEXT: addi sp, sp, -16 241; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 242; RV32I-NEXT: call fminimumf 243; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 244; RV32I-NEXT: addi sp, sp, 16 245; RV32I-NEXT: ret 246; 247; RV64IF-LABEL: fminimum_nnan_f32: 248; RV64IF: # %bb.0: 249; RV64IF-NEXT: fmin.s fa0, fa0, fa1 250; RV64IF-NEXT: ret 251; 252; RV64IZFINX-LABEL: fminimum_nnan_f32: 253; RV64IZFINX: # %bb.0: 254; RV64IZFINX-NEXT: fmin.s a0, a0, a1 255; RV64IZFINX-NEXT: ret 256; 257; RV64I-LABEL: fminimum_nnan_f32: 258; RV64I: # %bb.0: 259; RV64I-NEXT: addi sp, sp, -16 260; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 261; RV64I-NEXT: call fminimumf 262; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 263; RV64I-NEXT: addi sp, sp, 16 264; RV64I-NEXT: ret 265 %1 = call nnan float @llvm.minimum.f32(float %a, float %b) 266 ret float %1 267} 268 269define float @fmaximum_nnan_f32(float %a, float %b) nounwind { 270; RV32IF-LABEL: fmaximum_nnan_f32: 271; RV32IF: # %bb.0: 272; RV32IF-NEXT: fmax.s fa0, fa0, fa1 273; RV32IF-NEXT: ret 274; 275; RV32IZFINX-LABEL: fmaximum_nnan_f32: 276; RV32IZFINX: # %bb.0: 277; RV32IZFINX-NEXT: fmax.s a0, a0, a1 278; RV32IZFINX-NEXT: ret 279; 280; RV32I-LABEL: fmaximum_nnan_f32: 281; RV32I: # %bb.0: 282; RV32I-NEXT: addi sp, sp, -16 283; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 284; RV32I-NEXT: call fmaximumf 285; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 286; RV32I-NEXT: addi sp, sp, 16 287; RV32I-NEXT: ret 288; 289; RV64IF-LABEL: fmaximum_nnan_f32: 290; RV64IF: # %bb.0: 291; RV64IF-NEXT: fmax.s fa0, fa0, fa1 292; RV64IF-NEXT: ret 293; 294; RV64IZFINX-LABEL: fmaximum_nnan_f32: 295; RV64IZFINX: # %bb.0: 296; RV64IZFINX-NEXT: fmax.s a0, a0, a1 297; RV64IZFINX-NEXT: ret 298; 299; RV64I-LABEL: fmaximum_nnan_f32: 300; RV64I: # %bb.0: 301; RV64I-NEXT: addi sp, sp, -16 302; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 303; RV64I-NEXT: call fmaximumf 304; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 305; RV64I-NEXT: addi sp, sp, 16 306; RV64I-NEXT: ret 307 %1 = call nnan float @llvm.maximum.f32(float %a, float %b) 308 ret float %1 309} 310 311define float @fminimum_nnan_attr_f32(float %a, float %b) nounwind "no-nans-fp-math"="true" { 312; RV32IF-LABEL: fminimum_nnan_attr_f32: 313; RV32IF: # %bb.0: 314; RV32IF-NEXT: fmin.s fa0, fa0, fa1 315; RV32IF-NEXT: ret 316; 317; RV32IZFINX-LABEL: fminimum_nnan_attr_f32: 318; RV32IZFINX: # %bb.0: 319; RV32IZFINX-NEXT: fmin.s a0, a0, a1 320; RV32IZFINX-NEXT: ret 321; 322; RV32I-LABEL: fminimum_nnan_attr_f32: 323; RV32I: # %bb.0: 324; RV32I-NEXT: addi sp, sp, -16 325; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 326; RV32I-NEXT: call fminimumf 327; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 328; RV32I-NEXT: addi sp, sp, 16 329; RV32I-NEXT: ret 330; 331; RV64IF-LABEL: fminimum_nnan_attr_f32: 332; RV64IF: # %bb.0: 333; RV64IF-NEXT: fmin.s fa0, fa0, fa1 334; RV64IF-NEXT: ret 335; 336; RV64IZFINX-LABEL: fminimum_nnan_attr_f32: 337; RV64IZFINX: # %bb.0: 338; RV64IZFINX-NEXT: fmin.s a0, a0, a1 339; RV64IZFINX-NEXT: ret 340; 341; RV64I-LABEL: fminimum_nnan_attr_f32: 342; RV64I: # %bb.0: 343; RV64I-NEXT: addi sp, sp, -16 344; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 345; RV64I-NEXT: call fminimumf 346; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 347; RV64I-NEXT: addi sp, sp, 16 348; RV64I-NEXT: ret 349 %1 = call float @llvm.minimum.f32(float %a, float %b) 350 ret float %1 351} 352 353define float @fminimum_nnan_op_f32(float %a, float %b) nounwind { 354; RV32IF-LABEL: fminimum_nnan_op_f32: 355; RV32IF: # %bb.0: 356; RV32IF-NEXT: feq.s a0, fa0, fa0 357; RV32IF-NEXT: bnez a0, .LBB5_2 358; RV32IF-NEXT: # %bb.1: 359; RV32IF-NEXT: fmin.s fa0, fa0, fa0 360; RV32IF-NEXT: ret 361; RV32IF-NEXT: .LBB5_2: 362; RV32IF-NEXT: fadd.s fa5, fa0, fa0 363; RV32IF-NEXT: fmin.s fa0, fa0, fa5 364; RV32IF-NEXT: ret 365; 366; RV32IZFINX-LABEL: fminimum_nnan_op_f32: 367; RV32IZFINX: # %bb.0: 368; RV32IZFINX-NEXT: feq.s a1, a0, a0 369; RV32IZFINX-NEXT: bnez a1, .LBB5_2 370; RV32IZFINX-NEXT: # %bb.1: 371; RV32IZFINX-NEXT: fmin.s a0, a0, a0 372; RV32IZFINX-NEXT: ret 373; RV32IZFINX-NEXT: .LBB5_2: 374; RV32IZFINX-NEXT: fadd.s a1, a0, a0 375; RV32IZFINX-NEXT: fmin.s a0, a0, a1 376; RV32IZFINX-NEXT: ret 377; 378; RV32I-LABEL: fminimum_nnan_op_f32: 379; RV32I: # %bb.0: 380; RV32I-NEXT: addi sp, sp, -16 381; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 382; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 383; RV32I-NEXT: mv s0, a0 384; RV32I-NEXT: mv a1, a0 385; RV32I-NEXT: call __addsf3 386; RV32I-NEXT: mv a1, a0 387; RV32I-NEXT: mv a0, s0 388; RV32I-NEXT: call fminimumf 389; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 390; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 391; RV32I-NEXT: addi sp, sp, 16 392; RV32I-NEXT: ret 393; 394; RV64IF-LABEL: fminimum_nnan_op_f32: 395; RV64IF: # %bb.0: 396; RV64IF-NEXT: feq.s a0, fa0, fa0 397; RV64IF-NEXT: bnez a0, .LBB5_2 398; RV64IF-NEXT: # %bb.1: 399; RV64IF-NEXT: fmin.s fa0, fa0, fa0 400; RV64IF-NEXT: ret 401; RV64IF-NEXT: .LBB5_2: 402; RV64IF-NEXT: fadd.s fa5, fa0, fa0 403; RV64IF-NEXT: fmin.s fa0, fa0, fa5 404; RV64IF-NEXT: ret 405; 406; RV64IZFINX-LABEL: fminimum_nnan_op_f32: 407; RV64IZFINX: # %bb.0: 408; RV64IZFINX-NEXT: feq.s a1, a0, a0 409; RV64IZFINX-NEXT: bnez a1, .LBB5_2 410; RV64IZFINX-NEXT: # %bb.1: 411; RV64IZFINX-NEXT: fmin.s a0, a0, a0 412; RV64IZFINX-NEXT: ret 413; RV64IZFINX-NEXT: .LBB5_2: 414; RV64IZFINX-NEXT: fadd.s a1, a0, a0 415; RV64IZFINX-NEXT: fmin.s a0, a0, a1 416; RV64IZFINX-NEXT: ret 417; 418; RV64I-LABEL: fminimum_nnan_op_f32: 419; RV64I: # %bb.0: 420; RV64I-NEXT: addi sp, sp, -16 421; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 422; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 423; RV64I-NEXT: mv s0, a0 424; RV64I-NEXT: mv a1, a0 425; RV64I-NEXT: call __addsf3 426; RV64I-NEXT: mv a1, a0 427; RV64I-NEXT: mv a0, s0 428; RV64I-NEXT: call fminimumf 429; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 430; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 431; RV64I-NEXT: addi sp, sp, 16 432; RV64I-NEXT: ret 433 %c = fadd nnan float %a, %a 434 %1 = call float @llvm.minimum.f32(float %a, float %c) 435 ret float %1 436} 437 438define float @fmaximum_nnan_op_f32(float %a, float %b) nounwind { 439; RV32IF-LABEL: fmaximum_nnan_op_f32: 440; RV32IF: # %bb.0: 441; RV32IF-NEXT: fadd.s fa5, fa0, fa1 442; RV32IF-NEXT: fsub.s fa4, fa0, fa1 443; RV32IF-NEXT: fmax.s fa0, fa5, fa4 444; RV32IF-NEXT: ret 445; 446; RV32IZFINX-LABEL: fmaximum_nnan_op_f32: 447; RV32IZFINX: # %bb.0: 448; RV32IZFINX-NEXT: fadd.s a2, a0, a1 449; RV32IZFINX-NEXT: fsub.s a0, a0, a1 450; RV32IZFINX-NEXT: fmax.s a0, a2, a0 451; RV32IZFINX-NEXT: ret 452; 453; RV32I-LABEL: fmaximum_nnan_op_f32: 454; RV32I: # %bb.0: 455; RV32I-NEXT: addi sp, sp, -16 456; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 457; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 458; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 459; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill 460; RV32I-NEXT: mv s0, a1 461; RV32I-NEXT: mv s1, a0 462; RV32I-NEXT: call __addsf3 463; RV32I-NEXT: mv s2, a0 464; RV32I-NEXT: mv a0, s1 465; RV32I-NEXT: mv a1, s0 466; RV32I-NEXT: call __subsf3 467; RV32I-NEXT: mv a1, a0 468; RV32I-NEXT: mv a0, s2 469; RV32I-NEXT: call fmaximumf 470; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 471; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 472; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 473; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload 474; RV32I-NEXT: addi sp, sp, 16 475; RV32I-NEXT: ret 476; 477; RV64IF-LABEL: fmaximum_nnan_op_f32: 478; RV64IF: # %bb.0: 479; RV64IF-NEXT: fadd.s fa5, fa0, fa1 480; RV64IF-NEXT: fsub.s fa4, fa0, fa1 481; RV64IF-NEXT: fmax.s fa0, fa5, fa4 482; RV64IF-NEXT: ret 483; 484; RV64IZFINX-LABEL: fmaximum_nnan_op_f32: 485; RV64IZFINX: # %bb.0: 486; RV64IZFINX-NEXT: fadd.s a2, a0, a1 487; RV64IZFINX-NEXT: fsub.s a0, a0, a1 488; RV64IZFINX-NEXT: fmax.s a0, a2, a0 489; RV64IZFINX-NEXT: ret 490; 491; RV64I-LABEL: fmaximum_nnan_op_f32: 492; RV64I: # %bb.0: 493; RV64I-NEXT: addi sp, sp, -32 494; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 495; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 496; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 497; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 498; RV64I-NEXT: mv s0, a1 499; RV64I-NEXT: mv s1, a0 500; RV64I-NEXT: call __addsf3 501; RV64I-NEXT: mv s2, a0 502; RV64I-NEXT: mv a0, s1 503; RV64I-NEXT: mv a1, s0 504; RV64I-NEXT: call __subsf3 505; RV64I-NEXT: mv a1, a0 506; RV64I-NEXT: mv a0, s2 507; RV64I-NEXT: call fmaximumf 508; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 509; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 510; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 511; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 512; RV64I-NEXT: addi sp, sp, 32 513; RV64I-NEXT: ret 514 %c = fadd nnan float %a, %b 515 %d = fsub nnan float %a, %b 516 %1 = call float @llvm.maximum.f32(float %c, float %d) 517 ret float %1 518} 519