xref: /llvm-project/llvm/test/CodeGen/RISCV/float-isnan.ll (revision fe558efe71c12a665d4e1b5e7638baaacfe84cf7)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
3; RUN:   < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
5; RUN:   < %s | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -target-abi ilp32 -verify-machineinstrs \
7; RUN:   < %s | FileCheck --check-prefix=CHECKZFINX %s
8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi lp64 -verify-machineinstrs \
9; RUN:   < %s | FileCheck --check-prefix=CHECKZFINX %s
10
11define zeroext i1 @float_is_nan(float %a) nounwind {
12; CHECK-LABEL: float_is_nan:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    feq.s a0, fa0, fa0
15; CHECK-NEXT:    xori a0, a0, 1
16; CHECK-NEXT:    ret
17;
18; CHECKZFINX-LABEL: float_is_nan:
19; CHECKZFINX:       # %bb.0:
20; CHECKZFINX-NEXT:    feq.s a0, a0, a0
21; CHECKZFINX-NEXT:    xori a0, a0, 1
22; CHECKZFINX-NEXT:    ret
23  %1 = fcmp uno float %a, 0.000000e+00
24  ret i1 %1
25}
26
27define zeroext i1 @float_not_nan(float %a) nounwind {
28; CHECK-LABEL: float_not_nan:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    feq.s a0, fa0, fa0
31; CHECK-NEXT:    ret
32;
33; CHECKZFINX-LABEL: float_not_nan:
34; CHECKZFINX:       # %bb.0:
35; CHECKZFINX-NEXT:    feq.s a0, a0, a0
36; CHECKZFINX-NEXT:    ret
37  %1 = fcmp ord float %a, 0.000000e+00
38  ret i1 %1
39}
40