1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ 3; RUN: -verify-machineinstrs -target-abi=ilp32f \ 4; RUN: | FileCheck -check-prefix=RV32IF %s 5; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx \ 6; RUN: -verify-machineinstrs -target-abi=ilp32 \ 7; RUN: | FileCheck -check-prefix=RV32IZFINX %s 8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ 9; RUN: -verify-machineinstrs -target-abi=ilp32f \ 10; RUN: | FileCheck -check-prefix=RV32IF %s 11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ 12; RUN: -verify-machineinstrs -target-abi=lp64f \ 13; RUN: | FileCheck -check-prefix=RV64IF %s 14; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx \ 15; RUN: -verify-machineinstrs -target-abi=lp64 \ 16; RUN: | FileCheck -check-prefix=RV64IZFINX %s 17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ 18; RUN: -verify-machineinstrs -target-abi=lp64d \ 19; RUN: | FileCheck -check-prefix=RV64IF %s 20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ 21; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s 22; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ 23; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s 24 25declare float @llvm.sqrt.f32(float) 26 27define float @sqrt_f32(float %a) nounwind { 28; RV32IF-LABEL: sqrt_f32: 29; RV32IF: # %bb.0: 30; RV32IF-NEXT: fsqrt.s fa0, fa0 31; RV32IF-NEXT: ret 32; 33; RV32IZFINX-LABEL: sqrt_f32: 34; RV32IZFINX: # %bb.0: 35; RV32IZFINX-NEXT: fsqrt.s a0, a0 36; RV32IZFINX-NEXT: ret 37; 38; RV64IF-LABEL: sqrt_f32: 39; RV64IF: # %bb.0: 40; RV64IF-NEXT: fsqrt.s fa0, fa0 41; RV64IF-NEXT: ret 42; 43; RV64IZFINX-LABEL: sqrt_f32: 44; RV64IZFINX: # %bb.0: 45; RV64IZFINX-NEXT: fsqrt.s a0, a0 46; RV64IZFINX-NEXT: ret 47; 48; RV32I-LABEL: sqrt_f32: 49; RV32I: # %bb.0: 50; RV32I-NEXT: addi sp, sp, -16 51; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 52; RV32I-NEXT: call sqrtf 53; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 54; RV32I-NEXT: addi sp, sp, 16 55; RV32I-NEXT: ret 56; 57; RV64I-LABEL: sqrt_f32: 58; RV64I: # %bb.0: 59; RV64I-NEXT: addi sp, sp, -16 60; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 61; RV64I-NEXT: call sqrtf 62; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 63; RV64I-NEXT: addi sp, sp, 16 64; RV64I-NEXT: ret 65 %1 = call float @llvm.sqrt.f32(float %a) 66 ret float %1 67} 68 69declare float @llvm.powi.f32.i32(float, i32) 70 71define float @powi_f32(float %a, i32 %b) nounwind { 72; RV32IF-LABEL: powi_f32: 73; RV32IF: # %bb.0: 74; RV32IF-NEXT: tail __powisf2 75; 76; RV32IZFINX-LABEL: powi_f32: 77; RV32IZFINX: # %bb.0: 78; RV32IZFINX-NEXT: tail __powisf2 79; 80; RV64IF-LABEL: powi_f32: 81; RV64IF: # %bb.0: 82; RV64IF-NEXT: addi sp, sp, -16 83; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 84; RV64IF-NEXT: sext.w a0, a0 85; RV64IF-NEXT: call __powisf2 86; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 87; RV64IF-NEXT: addi sp, sp, 16 88; RV64IF-NEXT: ret 89; 90; RV64IZFINX-LABEL: powi_f32: 91; RV64IZFINX: # %bb.0: 92; RV64IZFINX-NEXT: addi sp, sp, -16 93; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 94; RV64IZFINX-NEXT: sext.w a1, a1 95; RV64IZFINX-NEXT: call __powisf2 96; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 97; RV64IZFINX-NEXT: addi sp, sp, 16 98; RV64IZFINX-NEXT: ret 99; 100; RV32I-LABEL: powi_f32: 101; RV32I: # %bb.0: 102; RV32I-NEXT: addi sp, sp, -16 103; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 104; RV32I-NEXT: call __powisf2 105; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 106; RV32I-NEXT: addi sp, sp, 16 107; RV32I-NEXT: ret 108; 109; RV64I-LABEL: powi_f32: 110; RV64I: # %bb.0: 111; RV64I-NEXT: addi sp, sp, -16 112; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 113; RV64I-NEXT: sext.w a1, a1 114; RV64I-NEXT: call __powisf2 115; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 116; RV64I-NEXT: addi sp, sp, 16 117; RV64I-NEXT: ret 118 %1 = call float @llvm.powi.f32.i32(float %a, i32 %b) 119 ret float %1 120} 121 122declare float @llvm.sin.f32(float) 123 124define float @sin_f32(float %a) nounwind { 125; RV32IF-LABEL: sin_f32: 126; RV32IF: # %bb.0: 127; RV32IF-NEXT: tail sinf 128; 129; RV32IZFINX-LABEL: sin_f32: 130; RV32IZFINX: # %bb.0: 131; RV32IZFINX-NEXT: tail sinf 132; 133; RV64IF-LABEL: sin_f32: 134; RV64IF: # %bb.0: 135; RV64IF-NEXT: tail sinf 136; 137; RV64IZFINX-LABEL: sin_f32: 138; RV64IZFINX: # %bb.0: 139; RV64IZFINX-NEXT: tail sinf 140; 141; RV32I-LABEL: sin_f32: 142; RV32I: # %bb.0: 143; RV32I-NEXT: addi sp, sp, -16 144; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 145; RV32I-NEXT: call sinf 146; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 147; RV32I-NEXT: addi sp, sp, 16 148; RV32I-NEXT: ret 149; 150; RV64I-LABEL: sin_f32: 151; RV64I: # %bb.0: 152; RV64I-NEXT: addi sp, sp, -16 153; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 154; RV64I-NEXT: call sinf 155; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 156; RV64I-NEXT: addi sp, sp, 16 157; RV64I-NEXT: ret 158 %1 = call float @llvm.sin.f32(float %a) 159 ret float %1 160} 161 162declare float @llvm.cos.f32(float) 163 164define float @cos_f32(float %a) nounwind { 165; RV32IF-LABEL: cos_f32: 166; RV32IF: # %bb.0: 167; RV32IF-NEXT: tail cosf 168; 169; RV32IZFINX-LABEL: cos_f32: 170; RV32IZFINX: # %bb.0: 171; RV32IZFINX-NEXT: tail cosf 172; 173; RV64IF-LABEL: cos_f32: 174; RV64IF: # %bb.0: 175; RV64IF-NEXT: tail cosf 176; 177; RV64IZFINX-LABEL: cos_f32: 178; RV64IZFINX: # %bb.0: 179; RV64IZFINX-NEXT: tail cosf 180; 181; RV32I-LABEL: cos_f32: 182; RV32I: # %bb.0: 183; RV32I-NEXT: addi sp, sp, -16 184; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 185; RV32I-NEXT: call cosf 186; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 187; RV32I-NEXT: addi sp, sp, 16 188; RV32I-NEXT: ret 189; 190; RV64I-LABEL: cos_f32: 191; RV64I: # %bb.0: 192; RV64I-NEXT: addi sp, sp, -16 193; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 194; RV64I-NEXT: call cosf 195; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 196; RV64I-NEXT: addi sp, sp, 16 197; RV64I-NEXT: ret 198 %1 = call float @llvm.cos.f32(float %a) 199 ret float %1 200} 201 202; The sin+cos combination results in an FSINCOS SelectionDAG node. 203define float @sincos_f32(float %a) nounwind { 204; RV32IF-LABEL: sincos_f32: 205; RV32IF: # %bb.0: 206; RV32IF-NEXT: addi sp, sp, -16 207; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 208; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill 209; RV32IF-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill 210; RV32IF-NEXT: fmv.s fs0, fa0 211; RV32IF-NEXT: call sinf 212; RV32IF-NEXT: fmv.s fs1, fa0 213; RV32IF-NEXT: fmv.s fa0, fs0 214; RV32IF-NEXT: call cosf 215; RV32IF-NEXT: fadd.s fa0, fs1, fa0 216; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 217; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload 218; RV32IF-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload 219; RV32IF-NEXT: addi sp, sp, 16 220; RV32IF-NEXT: ret 221; 222; RV32IZFINX-LABEL: sincos_f32: 223; RV32IZFINX: # %bb.0: 224; RV32IZFINX-NEXT: addi sp, sp, -16 225; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 226; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 227; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 228; RV32IZFINX-NEXT: mv s0, a0 229; RV32IZFINX-NEXT: call sinf 230; RV32IZFINX-NEXT: mv s1, a0 231; RV32IZFINX-NEXT: mv a0, s0 232; RV32IZFINX-NEXT: call cosf 233; RV32IZFINX-NEXT: fadd.s a0, s1, a0 234; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 235; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 236; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 237; RV32IZFINX-NEXT: addi sp, sp, 16 238; RV32IZFINX-NEXT: ret 239; 240; RV64IZFINX-LABEL: sincos_f32: 241; RV64IZFINX: # %bb.0: 242; RV64IZFINX-NEXT: addi sp, sp, -32 243; RV64IZFINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 244; RV64IZFINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 245; RV64IZFINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 246; RV64IZFINX-NEXT: mv s0, a0 247; RV64IZFINX-NEXT: call sinf 248; RV64IZFINX-NEXT: mv s1, a0 249; RV64IZFINX-NEXT: mv a0, s0 250; RV64IZFINX-NEXT: call cosf 251; RV64IZFINX-NEXT: fadd.s a0, s1, a0 252; RV64IZFINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 253; RV64IZFINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 254; RV64IZFINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 255; RV64IZFINX-NEXT: addi sp, sp, 32 256; RV64IZFINX-NEXT: ret 257; 258; RV32I-LABEL: sincos_f32: 259; RV32I: # %bb.0: 260; RV32I-NEXT: addi sp, sp, -16 261; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 262; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 263; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 264; RV32I-NEXT: mv s0, a0 265; RV32I-NEXT: call sinf 266; RV32I-NEXT: mv s1, a0 267; RV32I-NEXT: mv a0, s0 268; RV32I-NEXT: call cosf 269; RV32I-NEXT: mv a1, a0 270; RV32I-NEXT: mv a0, s1 271; RV32I-NEXT: call __addsf3 272; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 273; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 274; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 275; RV32I-NEXT: addi sp, sp, 16 276; RV32I-NEXT: ret 277; 278; RV64I-LABEL: sincos_f32: 279; RV64I: # %bb.0: 280; RV64I-NEXT: addi sp, sp, -32 281; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 282; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 283; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 284; RV64I-NEXT: mv s0, a0 285; RV64I-NEXT: call sinf 286; RV64I-NEXT: mv s1, a0 287; RV64I-NEXT: mv a0, s0 288; RV64I-NEXT: call cosf 289; RV64I-NEXT: mv a1, a0 290; RV64I-NEXT: mv a0, s1 291; RV64I-NEXT: call __addsf3 292; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 293; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 294; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 295; RV64I-NEXT: addi sp, sp, 32 296; RV64I-NEXT: ret 297 %1 = call float @llvm.sin.f32(float %a) 298 %2 = call float @llvm.cos.f32(float %a) 299 %3 = fadd float %1, %2 300 ret float %3 301} 302 303declare float @llvm.pow.f32(float, float) 304 305define float @pow_f32(float %a, float %b) nounwind { 306; RV32IF-LABEL: pow_f32: 307; RV32IF: # %bb.0: 308; RV32IF-NEXT: tail powf 309; 310; RV32IZFINX-LABEL: pow_f32: 311; RV32IZFINX: # %bb.0: 312; RV32IZFINX-NEXT: tail powf 313; 314; RV64IF-LABEL: pow_f32: 315; RV64IF: # %bb.0: 316; RV64IF-NEXT: tail powf 317; 318; RV64IZFINX-LABEL: pow_f32: 319; RV64IZFINX: # %bb.0: 320; RV64IZFINX-NEXT: tail powf 321; 322; RV32I-LABEL: pow_f32: 323; RV32I: # %bb.0: 324; RV32I-NEXT: addi sp, sp, -16 325; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 326; RV32I-NEXT: call powf 327; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 328; RV32I-NEXT: addi sp, sp, 16 329; RV32I-NEXT: ret 330; 331; RV64I-LABEL: pow_f32: 332; RV64I: # %bb.0: 333; RV64I-NEXT: addi sp, sp, -16 334; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 335; RV64I-NEXT: call powf 336; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 337; RV64I-NEXT: addi sp, sp, 16 338; RV64I-NEXT: ret 339 %1 = call float @llvm.pow.f32(float %a, float %b) 340 ret float %1 341} 342 343declare float @llvm.exp.f32(float) 344 345define float @exp_f32(float %a) nounwind { 346; RV32IF-LABEL: exp_f32: 347; RV32IF: # %bb.0: 348; RV32IF-NEXT: tail expf 349; 350; RV32IZFINX-LABEL: exp_f32: 351; RV32IZFINX: # %bb.0: 352; RV32IZFINX-NEXT: tail expf 353; 354; RV64IF-LABEL: exp_f32: 355; RV64IF: # %bb.0: 356; RV64IF-NEXT: tail expf 357; 358; RV64IZFINX-LABEL: exp_f32: 359; RV64IZFINX: # %bb.0: 360; RV64IZFINX-NEXT: tail expf 361; 362; RV32I-LABEL: exp_f32: 363; RV32I: # %bb.0: 364; RV32I-NEXT: addi sp, sp, -16 365; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 366; RV32I-NEXT: call expf 367; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 368; RV32I-NEXT: addi sp, sp, 16 369; RV32I-NEXT: ret 370; 371; RV64I-LABEL: exp_f32: 372; RV64I: # %bb.0: 373; RV64I-NEXT: addi sp, sp, -16 374; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 375; RV64I-NEXT: call expf 376; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 377; RV64I-NEXT: addi sp, sp, 16 378; RV64I-NEXT: ret 379 %1 = call float @llvm.exp.f32(float %a) 380 ret float %1 381} 382 383declare float @llvm.exp2.f32(float) 384 385define float @exp2_f32(float %a) nounwind { 386; RV32IF-LABEL: exp2_f32: 387; RV32IF: # %bb.0: 388; RV32IF-NEXT: tail exp2f 389; 390; RV32IZFINX-LABEL: exp2_f32: 391; RV32IZFINX: # %bb.0: 392; RV32IZFINX-NEXT: tail exp2f 393; 394; RV64IF-LABEL: exp2_f32: 395; RV64IF: # %bb.0: 396; RV64IF-NEXT: tail exp2f 397; 398; RV64IZFINX-LABEL: exp2_f32: 399; RV64IZFINX: # %bb.0: 400; RV64IZFINX-NEXT: tail exp2f 401; 402; RV32I-LABEL: exp2_f32: 403; RV32I: # %bb.0: 404; RV32I-NEXT: addi sp, sp, -16 405; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 406; RV32I-NEXT: call exp2f 407; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 408; RV32I-NEXT: addi sp, sp, 16 409; RV32I-NEXT: ret 410; 411; RV64I-LABEL: exp2_f32: 412; RV64I: # %bb.0: 413; RV64I-NEXT: addi sp, sp, -16 414; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 415; RV64I-NEXT: call exp2f 416; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 417; RV64I-NEXT: addi sp, sp, 16 418; RV64I-NEXT: ret 419 %1 = call float @llvm.exp2.f32(float %a) 420 ret float %1 421} 422 423define float @exp10_f32(float %a) nounwind { 424; RV32IF-LABEL: exp10_f32: 425; RV32IF: # %bb.0: 426; RV32IF-NEXT: tail exp10f 427; 428; RV32IZFINX-LABEL: exp10_f32: 429; RV32IZFINX: # %bb.0: 430; RV32IZFINX-NEXT: tail exp10f 431; 432; RV64IF-LABEL: exp10_f32: 433; RV64IF: # %bb.0: 434; RV64IF-NEXT: tail exp10f 435; 436; RV64IZFINX-LABEL: exp10_f32: 437; RV64IZFINX: # %bb.0: 438; RV64IZFINX-NEXT: tail exp10f 439; 440; RV32I-LABEL: exp10_f32: 441; RV32I: # %bb.0: 442; RV32I-NEXT: addi sp, sp, -16 443; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 444; RV32I-NEXT: call exp10f 445; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 446; RV32I-NEXT: addi sp, sp, 16 447; RV32I-NEXT: ret 448; 449; RV64I-LABEL: exp10_f32: 450; RV64I: # %bb.0: 451; RV64I-NEXT: addi sp, sp, -16 452; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 453; RV64I-NEXT: call exp10f 454; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 455; RV64I-NEXT: addi sp, sp, 16 456; RV64I-NEXT: ret 457 %1 = call float @llvm.exp10.f32(float %a) 458 ret float %1 459} 460 461declare float @llvm.log.f32(float) 462 463define float @log_f32(float %a) nounwind { 464; RV32IF-LABEL: log_f32: 465; RV32IF: # %bb.0: 466; RV32IF-NEXT: tail logf 467; 468; RV32IZFINX-LABEL: log_f32: 469; RV32IZFINX: # %bb.0: 470; RV32IZFINX-NEXT: tail logf 471; 472; RV64IF-LABEL: log_f32: 473; RV64IF: # %bb.0: 474; RV64IF-NEXT: tail logf 475; 476; RV64IZFINX-LABEL: log_f32: 477; RV64IZFINX: # %bb.0: 478; RV64IZFINX-NEXT: tail logf 479; 480; RV32I-LABEL: log_f32: 481; RV32I: # %bb.0: 482; RV32I-NEXT: addi sp, sp, -16 483; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 484; RV32I-NEXT: call logf 485; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 486; RV32I-NEXT: addi sp, sp, 16 487; RV32I-NEXT: ret 488; 489; RV64I-LABEL: log_f32: 490; RV64I: # %bb.0: 491; RV64I-NEXT: addi sp, sp, -16 492; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 493; RV64I-NEXT: call logf 494; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 495; RV64I-NEXT: addi sp, sp, 16 496; RV64I-NEXT: ret 497 %1 = call float @llvm.log.f32(float %a) 498 ret float %1 499} 500 501declare float @llvm.log10.f32(float) 502 503define float @log10_f32(float %a) nounwind { 504; RV32IF-LABEL: log10_f32: 505; RV32IF: # %bb.0: 506; RV32IF-NEXT: tail log10f 507; 508; RV32IZFINX-LABEL: log10_f32: 509; RV32IZFINX: # %bb.0: 510; RV32IZFINX-NEXT: tail log10f 511; 512; RV64IF-LABEL: log10_f32: 513; RV64IF: # %bb.0: 514; RV64IF-NEXT: tail log10f 515; 516; RV64IZFINX-LABEL: log10_f32: 517; RV64IZFINX: # %bb.0: 518; RV64IZFINX-NEXT: tail log10f 519; 520; RV32I-LABEL: log10_f32: 521; RV32I: # %bb.0: 522; RV32I-NEXT: addi sp, sp, -16 523; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 524; RV32I-NEXT: call log10f 525; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 526; RV32I-NEXT: addi sp, sp, 16 527; RV32I-NEXT: ret 528; 529; RV64I-LABEL: log10_f32: 530; RV64I: # %bb.0: 531; RV64I-NEXT: addi sp, sp, -16 532; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 533; RV64I-NEXT: call log10f 534; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 535; RV64I-NEXT: addi sp, sp, 16 536; RV64I-NEXT: ret 537 %1 = call float @llvm.log10.f32(float %a) 538 ret float %1 539} 540 541declare float @llvm.log2.f32(float) 542 543define float @log2_f32(float %a) nounwind { 544; RV32IF-LABEL: log2_f32: 545; RV32IF: # %bb.0: 546; RV32IF-NEXT: tail log2f 547; 548; RV32IZFINX-LABEL: log2_f32: 549; RV32IZFINX: # %bb.0: 550; RV32IZFINX-NEXT: tail log2f 551; 552; RV64IF-LABEL: log2_f32: 553; RV64IF: # %bb.0: 554; RV64IF-NEXT: tail log2f 555; 556; RV64IZFINX-LABEL: log2_f32: 557; RV64IZFINX: # %bb.0: 558; RV64IZFINX-NEXT: tail log2f 559; 560; RV32I-LABEL: log2_f32: 561; RV32I: # %bb.0: 562; RV32I-NEXT: addi sp, sp, -16 563; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 564; RV32I-NEXT: call log2f 565; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 566; RV32I-NEXT: addi sp, sp, 16 567; RV32I-NEXT: ret 568; 569; RV64I-LABEL: log2_f32: 570; RV64I: # %bb.0: 571; RV64I-NEXT: addi sp, sp, -16 572; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 573; RV64I-NEXT: call log2f 574; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 575; RV64I-NEXT: addi sp, sp, 16 576; RV64I-NEXT: ret 577 %1 = call float @llvm.log2.f32(float %a) 578 ret float %1 579} 580 581declare float @llvm.fma.f32(float, float, float) 582 583define float @fma_f32(float %a, float %b, float %c) nounwind { 584; RV32IF-LABEL: fma_f32: 585; RV32IF: # %bb.0: 586; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 587; RV32IF-NEXT: ret 588; 589; RV32IZFINX-LABEL: fma_f32: 590; RV32IZFINX: # %bb.0: 591; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2 592; RV32IZFINX-NEXT: ret 593; 594; RV64IF-LABEL: fma_f32: 595; RV64IF: # %bb.0: 596; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 597; RV64IF-NEXT: ret 598; 599; RV64IZFINX-LABEL: fma_f32: 600; RV64IZFINX: # %bb.0: 601; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2 602; RV64IZFINX-NEXT: ret 603; 604; RV32I-LABEL: fma_f32: 605; RV32I: # %bb.0: 606; RV32I-NEXT: addi sp, sp, -16 607; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 608; RV32I-NEXT: call fmaf 609; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 610; RV32I-NEXT: addi sp, sp, 16 611; RV32I-NEXT: ret 612; 613; RV64I-LABEL: fma_f32: 614; RV64I: # %bb.0: 615; RV64I-NEXT: addi sp, sp, -16 616; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 617; RV64I-NEXT: call fmaf 618; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 619; RV64I-NEXT: addi sp, sp, 16 620; RV64I-NEXT: ret 621 %1 = call float @llvm.fma.f32(float %a, float %b, float %c) 622 ret float %1 623} 624 625declare float @llvm.fmuladd.f32(float, float, float) 626 627define float @fmuladd_f32(float %a, float %b, float %c) nounwind { 628; RV32IF-LABEL: fmuladd_f32: 629; RV32IF: # %bb.0: 630; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 631; RV32IF-NEXT: ret 632; 633; RV32IZFINX-LABEL: fmuladd_f32: 634; RV32IZFINX: # %bb.0: 635; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2 636; RV32IZFINX-NEXT: ret 637; 638; RV64IF-LABEL: fmuladd_f32: 639; RV64IF: # %bb.0: 640; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2 641; RV64IF-NEXT: ret 642; 643; RV64IZFINX-LABEL: fmuladd_f32: 644; RV64IZFINX: # %bb.0: 645; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2 646; RV64IZFINX-NEXT: ret 647; 648; RV32I-LABEL: fmuladd_f32: 649; RV32I: # %bb.0: 650; RV32I-NEXT: addi sp, sp, -16 651; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 652; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 653; RV32I-NEXT: mv s0, a2 654; RV32I-NEXT: call __mulsf3 655; RV32I-NEXT: mv a1, s0 656; RV32I-NEXT: call __addsf3 657; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 658; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 659; RV32I-NEXT: addi sp, sp, 16 660; RV32I-NEXT: ret 661; 662; RV64I-LABEL: fmuladd_f32: 663; RV64I: # %bb.0: 664; RV64I-NEXT: addi sp, sp, -16 665; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 666; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 667; RV64I-NEXT: mv s0, a2 668; RV64I-NEXT: call __mulsf3 669; RV64I-NEXT: mv a1, s0 670; RV64I-NEXT: call __addsf3 671; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 672; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 673; RV64I-NEXT: addi sp, sp, 16 674; RV64I-NEXT: ret 675 %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) 676 ret float %1 677} 678 679declare float @llvm.fabs.f32(float) 680 681define float @fabs_f32(float %a) nounwind { 682; RV32IF-LABEL: fabs_f32: 683; RV32IF: # %bb.0: 684; RV32IF-NEXT: fabs.s fa0, fa0 685; RV32IF-NEXT: ret 686; 687; RV32IZFINX-LABEL: fabs_f32: 688; RV32IZFINX: # %bb.0: 689; RV32IZFINX-NEXT: fabs.s a0, a0 690; RV32IZFINX-NEXT: ret 691; 692; RV64IF-LABEL: fabs_f32: 693; RV64IF: # %bb.0: 694; RV64IF-NEXT: fabs.s fa0, fa0 695; RV64IF-NEXT: ret 696; 697; RV64IZFINX-LABEL: fabs_f32: 698; RV64IZFINX: # %bb.0: 699; RV64IZFINX-NEXT: fabs.s a0, a0 700; RV64IZFINX-NEXT: ret 701; 702; RV32I-LABEL: fabs_f32: 703; RV32I: # %bb.0: 704; RV32I-NEXT: slli a0, a0, 1 705; RV32I-NEXT: srli a0, a0, 1 706; RV32I-NEXT: ret 707; 708; RV64I-LABEL: fabs_f32: 709; RV64I: # %bb.0: 710; RV64I-NEXT: slli a0, a0, 33 711; RV64I-NEXT: srli a0, a0, 33 712; RV64I-NEXT: ret 713 %1 = call float @llvm.fabs.f32(float %a) 714 ret float %1 715} 716 717declare float @llvm.minnum.f32(float, float) 718 719define float @minnum_f32(float %a, float %b) nounwind { 720; RV32IF-LABEL: minnum_f32: 721; RV32IF: # %bb.0: 722; RV32IF-NEXT: fmin.s fa0, fa0, fa1 723; RV32IF-NEXT: ret 724; 725; RV32IZFINX-LABEL: minnum_f32: 726; RV32IZFINX: # %bb.0: 727; RV32IZFINX-NEXT: fmin.s a0, a0, a1 728; RV32IZFINX-NEXT: ret 729; 730; RV64IF-LABEL: minnum_f32: 731; RV64IF: # %bb.0: 732; RV64IF-NEXT: fmin.s fa0, fa0, fa1 733; RV64IF-NEXT: ret 734; 735; RV64IZFINX-LABEL: minnum_f32: 736; RV64IZFINX: # %bb.0: 737; RV64IZFINX-NEXT: fmin.s a0, a0, a1 738; RV64IZFINX-NEXT: ret 739; 740; RV32I-LABEL: minnum_f32: 741; RV32I: # %bb.0: 742; RV32I-NEXT: addi sp, sp, -16 743; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 744; RV32I-NEXT: call fminf 745; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 746; RV32I-NEXT: addi sp, sp, 16 747; RV32I-NEXT: ret 748; 749; RV64I-LABEL: minnum_f32: 750; RV64I: # %bb.0: 751; RV64I-NEXT: addi sp, sp, -16 752; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 753; RV64I-NEXT: call fminf 754; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 755; RV64I-NEXT: addi sp, sp, 16 756; RV64I-NEXT: ret 757 %1 = call float @llvm.minnum.f32(float %a, float %b) 758 ret float %1 759} 760 761declare float @llvm.maxnum.f32(float, float) 762 763define float @maxnum_f32(float %a, float %b) nounwind { 764; RV32IF-LABEL: maxnum_f32: 765; RV32IF: # %bb.0: 766; RV32IF-NEXT: fmax.s fa0, fa0, fa1 767; RV32IF-NEXT: ret 768; 769; RV32IZFINX-LABEL: maxnum_f32: 770; RV32IZFINX: # %bb.0: 771; RV32IZFINX-NEXT: fmax.s a0, a0, a1 772; RV32IZFINX-NEXT: ret 773; 774; RV64IF-LABEL: maxnum_f32: 775; RV64IF: # %bb.0: 776; RV64IF-NEXT: fmax.s fa0, fa0, fa1 777; RV64IF-NEXT: ret 778; 779; RV64IZFINX-LABEL: maxnum_f32: 780; RV64IZFINX: # %bb.0: 781; RV64IZFINX-NEXT: fmax.s a0, a0, a1 782; RV64IZFINX-NEXT: ret 783; 784; RV32I-LABEL: maxnum_f32: 785; RV32I: # %bb.0: 786; RV32I-NEXT: addi sp, sp, -16 787; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 788; RV32I-NEXT: call fmaxf 789; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 790; RV32I-NEXT: addi sp, sp, 16 791; RV32I-NEXT: ret 792; 793; RV64I-LABEL: maxnum_f32: 794; RV64I: # %bb.0: 795; RV64I-NEXT: addi sp, sp, -16 796; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 797; RV64I-NEXT: call fmaxf 798; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 799; RV64I-NEXT: addi sp, sp, 16 800; RV64I-NEXT: ret 801 %1 = call float @llvm.maxnum.f32(float %a, float %b) 802 ret float %1 803} 804 805; TODO: FMINNAN and FMAXNAN aren't handled in 806; SelectionDAGLegalize::ExpandNode. 807 808; declare float @llvm.minimum.f32(float, float) 809 810; define float @fminimum_f32(float %a, float %b) nounwind { 811; %1 = call float @llvm.minimum.f32(float %a, float %b) 812; ret float %1 813; } 814 815; declare float @llvm.maximum.f32(float, float) 816 817; define float @fmaximum_f32(float %a, float %b) nounwind { 818; %1 = call float @llvm.maximum.f32(float %a, float %b) 819; ret float %1 820; } 821 822declare float @llvm.copysign.f32(float, float) 823 824define float @copysign_f32(float %a, float %b) nounwind { 825; RV32IF-LABEL: copysign_f32: 826; RV32IF: # %bb.0: 827; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1 828; RV32IF-NEXT: ret 829; 830; RV32IZFINX-LABEL: copysign_f32: 831; RV32IZFINX: # %bb.0: 832; RV32IZFINX-NEXT: fsgnj.s a0, a0, a1 833; RV32IZFINX-NEXT: ret 834; 835; RV64IF-LABEL: copysign_f32: 836; RV64IF: # %bb.0: 837; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1 838; RV64IF-NEXT: ret 839; 840; RV64IZFINX-LABEL: copysign_f32: 841; RV64IZFINX: # %bb.0: 842; RV64IZFINX-NEXT: fsgnj.s a0, a0, a1 843; RV64IZFINX-NEXT: ret 844; 845; RV32I-LABEL: copysign_f32: 846; RV32I: # %bb.0: 847; RV32I-NEXT: lui a2, 524288 848; RV32I-NEXT: slli a0, a0, 1 849; RV32I-NEXT: and a1, a1, a2 850; RV32I-NEXT: srli a0, a0, 1 851; RV32I-NEXT: or a0, a0, a1 852; RV32I-NEXT: ret 853; 854; RV64I-LABEL: copysign_f32: 855; RV64I: # %bb.0: 856; RV64I-NEXT: lui a2, 524288 857; RV64I-NEXT: slli a0, a0, 33 858; RV64I-NEXT: and a1, a1, a2 859; RV64I-NEXT: srli a0, a0, 33 860; RV64I-NEXT: or a0, a0, a1 861; RV64I-NEXT: ret 862 %1 = call float @llvm.copysign.f32(float %a, float %b) 863 ret float %1 864} 865 866declare float @llvm.floor.f32(float) 867 868define float @floor_f32(float %a) nounwind { 869; RV32IF-LABEL: floor_f32: 870; RV32IF: # %bb.0: 871; RV32IF-NEXT: lui a0, 307200 872; RV32IF-NEXT: fmv.w.x fa5, a0 873; RV32IF-NEXT: fabs.s fa4, fa0 874; RV32IF-NEXT: flt.s a0, fa4, fa5 875; RV32IF-NEXT: beqz a0, .LBB18_2 876; RV32IF-NEXT: # %bb.1: 877; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn 878; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn 879; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0 880; RV32IF-NEXT: .LBB18_2: 881; RV32IF-NEXT: ret 882; 883; RV32IZFINX-LABEL: floor_f32: 884; RV32IZFINX: # %bb.0: 885; RV32IZFINX-NEXT: lui a1, 307200 886; RV32IZFINX-NEXT: fabs.s a2, a0 887; RV32IZFINX-NEXT: flt.s a1, a2, a1 888; RV32IZFINX-NEXT: beqz a1, .LBB18_2 889; RV32IZFINX-NEXT: # %bb.1: 890; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rdn 891; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rdn 892; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0 893; RV32IZFINX-NEXT: .LBB18_2: 894; RV32IZFINX-NEXT: ret 895; 896; RV64IF-LABEL: floor_f32: 897; RV64IF: # %bb.0: 898; RV64IF-NEXT: lui a0, 307200 899; RV64IF-NEXT: fmv.w.x fa5, a0 900; RV64IF-NEXT: fabs.s fa4, fa0 901; RV64IF-NEXT: flt.s a0, fa4, fa5 902; RV64IF-NEXT: beqz a0, .LBB18_2 903; RV64IF-NEXT: # %bb.1: 904; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn 905; RV64IF-NEXT: fcvt.s.w fa5, a0, rdn 906; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0 907; RV64IF-NEXT: .LBB18_2: 908; RV64IF-NEXT: ret 909; 910; RV64IZFINX-LABEL: floor_f32: 911; RV64IZFINX: # %bb.0: 912; RV64IZFINX-NEXT: lui a1, 307200 913; RV64IZFINX-NEXT: fabs.s a2, a0 914; RV64IZFINX-NEXT: flt.s a1, a2, a1 915; RV64IZFINX-NEXT: beqz a1, .LBB18_2 916; RV64IZFINX-NEXT: # %bb.1: 917; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rdn 918; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rdn 919; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0 920; RV64IZFINX-NEXT: .LBB18_2: 921; RV64IZFINX-NEXT: ret 922; 923; RV32I-LABEL: floor_f32: 924; RV32I: # %bb.0: 925; RV32I-NEXT: addi sp, sp, -16 926; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 927; RV32I-NEXT: call floorf 928; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 929; RV32I-NEXT: addi sp, sp, 16 930; RV32I-NEXT: ret 931; 932; RV64I-LABEL: floor_f32: 933; RV64I: # %bb.0: 934; RV64I-NEXT: addi sp, sp, -16 935; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 936; RV64I-NEXT: call floorf 937; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 938; RV64I-NEXT: addi sp, sp, 16 939; RV64I-NEXT: ret 940 %1 = call float @llvm.floor.f32(float %a) 941 ret float %1 942} 943 944declare float @llvm.ceil.f32(float) 945 946define float @ceil_f32(float %a) nounwind { 947; RV32IF-LABEL: ceil_f32: 948; RV32IF: # %bb.0: 949; RV32IF-NEXT: lui a0, 307200 950; RV32IF-NEXT: fmv.w.x fa5, a0 951; RV32IF-NEXT: fabs.s fa4, fa0 952; RV32IF-NEXT: flt.s a0, fa4, fa5 953; RV32IF-NEXT: beqz a0, .LBB19_2 954; RV32IF-NEXT: # %bb.1: 955; RV32IF-NEXT: fcvt.w.s a0, fa0, rup 956; RV32IF-NEXT: fcvt.s.w fa5, a0, rup 957; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0 958; RV32IF-NEXT: .LBB19_2: 959; RV32IF-NEXT: ret 960; 961; RV32IZFINX-LABEL: ceil_f32: 962; RV32IZFINX: # %bb.0: 963; RV32IZFINX-NEXT: lui a1, 307200 964; RV32IZFINX-NEXT: fabs.s a2, a0 965; RV32IZFINX-NEXT: flt.s a1, a2, a1 966; RV32IZFINX-NEXT: beqz a1, .LBB19_2 967; RV32IZFINX-NEXT: # %bb.1: 968; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rup 969; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rup 970; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0 971; RV32IZFINX-NEXT: .LBB19_2: 972; RV32IZFINX-NEXT: ret 973; 974; RV64IF-LABEL: ceil_f32: 975; RV64IF: # %bb.0: 976; RV64IF-NEXT: lui a0, 307200 977; RV64IF-NEXT: fmv.w.x fa5, a0 978; RV64IF-NEXT: fabs.s fa4, fa0 979; RV64IF-NEXT: flt.s a0, fa4, fa5 980; RV64IF-NEXT: beqz a0, .LBB19_2 981; RV64IF-NEXT: # %bb.1: 982; RV64IF-NEXT: fcvt.w.s a0, fa0, rup 983; RV64IF-NEXT: fcvt.s.w fa5, a0, rup 984; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0 985; RV64IF-NEXT: .LBB19_2: 986; RV64IF-NEXT: ret 987; 988; RV64IZFINX-LABEL: ceil_f32: 989; RV64IZFINX: # %bb.0: 990; RV64IZFINX-NEXT: lui a1, 307200 991; RV64IZFINX-NEXT: fabs.s a2, a0 992; RV64IZFINX-NEXT: flt.s a1, a2, a1 993; RV64IZFINX-NEXT: beqz a1, .LBB19_2 994; RV64IZFINX-NEXT: # %bb.1: 995; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rup 996; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rup 997; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0 998; RV64IZFINX-NEXT: .LBB19_2: 999; RV64IZFINX-NEXT: ret 1000; 1001; RV32I-LABEL: ceil_f32: 1002; RV32I: # %bb.0: 1003; RV32I-NEXT: addi sp, sp, -16 1004; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1005; RV32I-NEXT: call ceilf 1006; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1007; RV32I-NEXT: addi sp, sp, 16 1008; RV32I-NEXT: ret 1009; 1010; RV64I-LABEL: ceil_f32: 1011; RV64I: # %bb.0: 1012; RV64I-NEXT: addi sp, sp, -16 1013; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1014; RV64I-NEXT: call ceilf 1015; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1016; RV64I-NEXT: addi sp, sp, 16 1017; RV64I-NEXT: ret 1018 %1 = call float @llvm.ceil.f32(float %a) 1019 ret float %1 1020} 1021 1022declare float @llvm.trunc.f32(float) 1023 1024define float @trunc_f32(float %a) nounwind { 1025; RV32IF-LABEL: trunc_f32: 1026; RV32IF: # %bb.0: 1027; RV32IF-NEXT: lui a0, 307200 1028; RV32IF-NEXT: fmv.w.x fa5, a0 1029; RV32IF-NEXT: fabs.s fa4, fa0 1030; RV32IF-NEXT: flt.s a0, fa4, fa5 1031; RV32IF-NEXT: beqz a0, .LBB20_2 1032; RV32IF-NEXT: # %bb.1: 1033; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz 1034; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz 1035; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0 1036; RV32IF-NEXT: .LBB20_2: 1037; RV32IF-NEXT: ret 1038; 1039; RV32IZFINX-LABEL: trunc_f32: 1040; RV32IZFINX: # %bb.0: 1041; RV32IZFINX-NEXT: lui a1, 307200 1042; RV32IZFINX-NEXT: fabs.s a2, a0 1043; RV32IZFINX-NEXT: flt.s a1, a2, a1 1044; RV32IZFINX-NEXT: beqz a1, .LBB20_2 1045; RV32IZFINX-NEXT: # %bb.1: 1046; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rtz 1047; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rtz 1048; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0 1049; RV32IZFINX-NEXT: .LBB20_2: 1050; RV32IZFINX-NEXT: ret 1051; 1052; RV64IF-LABEL: trunc_f32: 1053; RV64IF: # %bb.0: 1054; RV64IF-NEXT: lui a0, 307200 1055; RV64IF-NEXT: fmv.w.x fa5, a0 1056; RV64IF-NEXT: fabs.s fa4, fa0 1057; RV64IF-NEXT: flt.s a0, fa4, fa5 1058; RV64IF-NEXT: beqz a0, .LBB20_2 1059; RV64IF-NEXT: # %bb.1: 1060; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz 1061; RV64IF-NEXT: fcvt.s.w fa5, a0, rtz 1062; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0 1063; RV64IF-NEXT: .LBB20_2: 1064; RV64IF-NEXT: ret 1065; 1066; RV64IZFINX-LABEL: trunc_f32: 1067; RV64IZFINX: # %bb.0: 1068; RV64IZFINX-NEXT: lui a1, 307200 1069; RV64IZFINX-NEXT: fabs.s a2, a0 1070; RV64IZFINX-NEXT: flt.s a1, a2, a1 1071; RV64IZFINX-NEXT: beqz a1, .LBB20_2 1072; RV64IZFINX-NEXT: # %bb.1: 1073; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rtz 1074; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rtz 1075; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0 1076; RV64IZFINX-NEXT: .LBB20_2: 1077; RV64IZFINX-NEXT: ret 1078; 1079; RV32I-LABEL: trunc_f32: 1080; RV32I: # %bb.0: 1081; RV32I-NEXT: addi sp, sp, -16 1082; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1083; RV32I-NEXT: call truncf 1084; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1085; RV32I-NEXT: addi sp, sp, 16 1086; RV32I-NEXT: ret 1087; 1088; RV64I-LABEL: trunc_f32: 1089; RV64I: # %bb.0: 1090; RV64I-NEXT: addi sp, sp, -16 1091; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1092; RV64I-NEXT: call truncf 1093; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1094; RV64I-NEXT: addi sp, sp, 16 1095; RV64I-NEXT: ret 1096 %1 = call float @llvm.trunc.f32(float %a) 1097 ret float %1 1098} 1099 1100declare float @llvm.rint.f32(float) 1101 1102define float @rint_f32(float %a) nounwind { 1103; RV32IF-LABEL: rint_f32: 1104; RV32IF: # %bb.0: 1105; RV32IF-NEXT: lui a0, 307200 1106; RV32IF-NEXT: fmv.w.x fa5, a0 1107; RV32IF-NEXT: fabs.s fa4, fa0 1108; RV32IF-NEXT: flt.s a0, fa4, fa5 1109; RV32IF-NEXT: beqz a0, .LBB21_2 1110; RV32IF-NEXT: # %bb.1: 1111; RV32IF-NEXT: fcvt.w.s a0, fa0 1112; RV32IF-NEXT: fcvt.s.w fa5, a0 1113; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0 1114; RV32IF-NEXT: .LBB21_2: 1115; RV32IF-NEXT: ret 1116; 1117; RV32IZFINX-LABEL: rint_f32: 1118; RV32IZFINX: # %bb.0: 1119; RV32IZFINX-NEXT: lui a1, 307200 1120; RV32IZFINX-NEXT: fabs.s a2, a0 1121; RV32IZFINX-NEXT: flt.s a1, a2, a1 1122; RV32IZFINX-NEXT: beqz a1, .LBB21_2 1123; RV32IZFINX-NEXT: # %bb.1: 1124; RV32IZFINX-NEXT: fcvt.w.s a1, a0 1125; RV32IZFINX-NEXT: fcvt.s.w a1, a1 1126; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0 1127; RV32IZFINX-NEXT: .LBB21_2: 1128; RV32IZFINX-NEXT: ret 1129; 1130; RV64IF-LABEL: rint_f32: 1131; RV64IF: # %bb.0: 1132; RV64IF-NEXT: lui a0, 307200 1133; RV64IF-NEXT: fmv.w.x fa5, a0 1134; RV64IF-NEXT: fabs.s fa4, fa0 1135; RV64IF-NEXT: flt.s a0, fa4, fa5 1136; RV64IF-NEXT: beqz a0, .LBB21_2 1137; RV64IF-NEXT: # %bb.1: 1138; RV64IF-NEXT: fcvt.w.s a0, fa0 1139; RV64IF-NEXT: fcvt.s.w fa5, a0 1140; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0 1141; RV64IF-NEXT: .LBB21_2: 1142; RV64IF-NEXT: ret 1143; 1144; RV64IZFINX-LABEL: rint_f32: 1145; RV64IZFINX: # %bb.0: 1146; RV64IZFINX-NEXT: lui a1, 307200 1147; RV64IZFINX-NEXT: fabs.s a2, a0 1148; RV64IZFINX-NEXT: flt.s a1, a2, a1 1149; RV64IZFINX-NEXT: beqz a1, .LBB21_2 1150; RV64IZFINX-NEXT: # %bb.1: 1151; RV64IZFINX-NEXT: fcvt.w.s a1, a0 1152; RV64IZFINX-NEXT: fcvt.s.w a1, a1 1153; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0 1154; RV64IZFINX-NEXT: .LBB21_2: 1155; RV64IZFINX-NEXT: ret 1156; 1157; RV32I-LABEL: rint_f32: 1158; RV32I: # %bb.0: 1159; RV32I-NEXT: addi sp, sp, -16 1160; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1161; RV32I-NEXT: call rintf 1162; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1163; RV32I-NEXT: addi sp, sp, 16 1164; RV32I-NEXT: ret 1165; 1166; RV64I-LABEL: rint_f32: 1167; RV64I: # %bb.0: 1168; RV64I-NEXT: addi sp, sp, -16 1169; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1170; RV64I-NEXT: call rintf 1171; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1172; RV64I-NEXT: addi sp, sp, 16 1173; RV64I-NEXT: ret 1174 %1 = call float @llvm.rint.f32(float %a) 1175 ret float %1 1176} 1177 1178declare float @llvm.nearbyint.f32(float) 1179 1180define float @nearbyint_f32(float %a) nounwind { 1181; RV32IF-LABEL: nearbyint_f32: 1182; RV32IF: # %bb.0: 1183; RV32IF-NEXT: tail nearbyintf 1184; 1185; RV32IZFINX-LABEL: nearbyint_f32: 1186; RV32IZFINX: # %bb.0: 1187; RV32IZFINX-NEXT: tail nearbyintf 1188; 1189; RV64IF-LABEL: nearbyint_f32: 1190; RV64IF: # %bb.0: 1191; RV64IF-NEXT: tail nearbyintf 1192; 1193; RV64IZFINX-LABEL: nearbyint_f32: 1194; RV64IZFINX: # %bb.0: 1195; RV64IZFINX-NEXT: tail nearbyintf 1196; 1197; RV32I-LABEL: nearbyint_f32: 1198; RV32I: # %bb.0: 1199; RV32I-NEXT: addi sp, sp, -16 1200; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1201; RV32I-NEXT: call nearbyintf 1202; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1203; RV32I-NEXT: addi sp, sp, 16 1204; RV32I-NEXT: ret 1205; 1206; RV64I-LABEL: nearbyint_f32: 1207; RV64I: # %bb.0: 1208; RV64I-NEXT: addi sp, sp, -16 1209; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1210; RV64I-NEXT: call nearbyintf 1211; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1212; RV64I-NEXT: addi sp, sp, 16 1213; RV64I-NEXT: ret 1214 %1 = call float @llvm.nearbyint.f32(float %a) 1215 ret float %1 1216} 1217 1218declare float @llvm.round.f32(float) 1219 1220define float @round_f32(float %a) nounwind { 1221; RV32IF-LABEL: round_f32: 1222; RV32IF: # %bb.0: 1223; RV32IF-NEXT: lui a0, 307200 1224; RV32IF-NEXT: fmv.w.x fa5, a0 1225; RV32IF-NEXT: fabs.s fa4, fa0 1226; RV32IF-NEXT: flt.s a0, fa4, fa5 1227; RV32IF-NEXT: beqz a0, .LBB23_2 1228; RV32IF-NEXT: # %bb.1: 1229; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm 1230; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm 1231; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0 1232; RV32IF-NEXT: .LBB23_2: 1233; RV32IF-NEXT: ret 1234; 1235; RV32IZFINX-LABEL: round_f32: 1236; RV32IZFINX: # %bb.0: 1237; RV32IZFINX-NEXT: lui a1, 307200 1238; RV32IZFINX-NEXT: fabs.s a2, a0 1239; RV32IZFINX-NEXT: flt.s a1, a2, a1 1240; RV32IZFINX-NEXT: beqz a1, .LBB23_2 1241; RV32IZFINX-NEXT: # %bb.1: 1242; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rmm 1243; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rmm 1244; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0 1245; RV32IZFINX-NEXT: .LBB23_2: 1246; RV32IZFINX-NEXT: ret 1247; 1248; RV64IF-LABEL: round_f32: 1249; RV64IF: # %bb.0: 1250; RV64IF-NEXT: lui a0, 307200 1251; RV64IF-NEXT: fmv.w.x fa5, a0 1252; RV64IF-NEXT: fabs.s fa4, fa0 1253; RV64IF-NEXT: flt.s a0, fa4, fa5 1254; RV64IF-NEXT: beqz a0, .LBB23_2 1255; RV64IF-NEXT: # %bb.1: 1256; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm 1257; RV64IF-NEXT: fcvt.s.w fa5, a0, rmm 1258; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0 1259; RV64IF-NEXT: .LBB23_2: 1260; RV64IF-NEXT: ret 1261; 1262; RV64IZFINX-LABEL: round_f32: 1263; RV64IZFINX: # %bb.0: 1264; RV64IZFINX-NEXT: lui a1, 307200 1265; RV64IZFINX-NEXT: fabs.s a2, a0 1266; RV64IZFINX-NEXT: flt.s a1, a2, a1 1267; RV64IZFINX-NEXT: beqz a1, .LBB23_2 1268; RV64IZFINX-NEXT: # %bb.1: 1269; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rmm 1270; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rmm 1271; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0 1272; RV64IZFINX-NEXT: .LBB23_2: 1273; RV64IZFINX-NEXT: ret 1274; 1275; RV32I-LABEL: round_f32: 1276; RV32I: # %bb.0: 1277; RV32I-NEXT: addi sp, sp, -16 1278; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1279; RV32I-NEXT: call roundf 1280; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1281; RV32I-NEXT: addi sp, sp, 16 1282; RV32I-NEXT: ret 1283; 1284; RV64I-LABEL: round_f32: 1285; RV64I: # %bb.0: 1286; RV64I-NEXT: addi sp, sp, -16 1287; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1288; RV64I-NEXT: call roundf 1289; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1290; RV64I-NEXT: addi sp, sp, 16 1291; RV64I-NEXT: ret 1292 %1 = call float @llvm.round.f32(float %a) 1293 ret float %1 1294} 1295 1296declare float @llvm.roundeven.f32(float) 1297 1298define float @roundeven_f32(float %a) nounwind { 1299; RV32IF-LABEL: roundeven_f32: 1300; RV32IF: # %bb.0: 1301; RV32IF-NEXT: lui a0, 307200 1302; RV32IF-NEXT: fmv.w.x fa5, a0 1303; RV32IF-NEXT: fabs.s fa4, fa0 1304; RV32IF-NEXT: flt.s a0, fa4, fa5 1305; RV32IF-NEXT: beqz a0, .LBB24_2 1306; RV32IF-NEXT: # %bb.1: 1307; RV32IF-NEXT: fcvt.w.s a0, fa0, rne 1308; RV32IF-NEXT: fcvt.s.w fa5, a0, rne 1309; RV32IF-NEXT: fsgnj.s fa0, fa5, fa0 1310; RV32IF-NEXT: .LBB24_2: 1311; RV32IF-NEXT: ret 1312; 1313; RV32IZFINX-LABEL: roundeven_f32: 1314; RV32IZFINX: # %bb.0: 1315; RV32IZFINX-NEXT: lui a1, 307200 1316; RV32IZFINX-NEXT: fabs.s a2, a0 1317; RV32IZFINX-NEXT: flt.s a1, a2, a1 1318; RV32IZFINX-NEXT: beqz a1, .LBB24_2 1319; RV32IZFINX-NEXT: # %bb.1: 1320; RV32IZFINX-NEXT: fcvt.w.s a1, a0, rne 1321; RV32IZFINX-NEXT: fcvt.s.w a1, a1, rne 1322; RV32IZFINX-NEXT: fsgnj.s a0, a1, a0 1323; RV32IZFINX-NEXT: .LBB24_2: 1324; RV32IZFINX-NEXT: ret 1325; 1326; RV64IF-LABEL: roundeven_f32: 1327; RV64IF: # %bb.0: 1328; RV64IF-NEXT: lui a0, 307200 1329; RV64IF-NEXT: fmv.w.x fa5, a0 1330; RV64IF-NEXT: fabs.s fa4, fa0 1331; RV64IF-NEXT: flt.s a0, fa4, fa5 1332; RV64IF-NEXT: beqz a0, .LBB24_2 1333; RV64IF-NEXT: # %bb.1: 1334; RV64IF-NEXT: fcvt.w.s a0, fa0, rne 1335; RV64IF-NEXT: fcvt.s.w fa5, a0, rne 1336; RV64IF-NEXT: fsgnj.s fa0, fa5, fa0 1337; RV64IF-NEXT: .LBB24_2: 1338; RV64IF-NEXT: ret 1339; 1340; RV64IZFINX-LABEL: roundeven_f32: 1341; RV64IZFINX: # %bb.0: 1342; RV64IZFINX-NEXT: lui a1, 307200 1343; RV64IZFINX-NEXT: fabs.s a2, a0 1344; RV64IZFINX-NEXT: flt.s a1, a2, a1 1345; RV64IZFINX-NEXT: beqz a1, .LBB24_2 1346; RV64IZFINX-NEXT: # %bb.1: 1347; RV64IZFINX-NEXT: fcvt.w.s a1, a0, rne 1348; RV64IZFINX-NEXT: fcvt.s.w a1, a1, rne 1349; RV64IZFINX-NEXT: fsgnj.s a0, a1, a0 1350; RV64IZFINX-NEXT: .LBB24_2: 1351; RV64IZFINX-NEXT: ret 1352; 1353; RV32I-LABEL: roundeven_f32: 1354; RV32I: # %bb.0: 1355; RV32I-NEXT: addi sp, sp, -16 1356; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1357; RV32I-NEXT: call roundevenf 1358; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1359; RV32I-NEXT: addi sp, sp, 16 1360; RV32I-NEXT: ret 1361; 1362; RV64I-LABEL: roundeven_f32: 1363; RV64I: # %bb.0: 1364; RV64I-NEXT: addi sp, sp, -16 1365; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1366; RV64I-NEXT: call roundevenf 1367; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1368; RV64I-NEXT: addi sp, sp, 16 1369; RV64I-NEXT: ret 1370 %1 = call float @llvm.roundeven.f32(float %a) 1371 ret float %1 1372} 1373 1374declare iXLen @llvm.lrint.iXLen.f32(float) 1375 1376define iXLen @lrint_f32(float %a) nounwind { 1377; RV32IF-LABEL: lrint_f32: 1378; RV32IF: # %bb.0: 1379; RV32IF-NEXT: fcvt.w.s a0, fa0 1380; RV32IF-NEXT: ret 1381; 1382; RV32IZFINX-LABEL: lrint_f32: 1383; RV32IZFINX: # %bb.0: 1384; RV32IZFINX-NEXT: fcvt.w.s a0, a0 1385; RV32IZFINX-NEXT: ret 1386; 1387; RV64IF-LABEL: lrint_f32: 1388; RV64IF: # %bb.0: 1389; RV64IF-NEXT: fcvt.l.s a0, fa0 1390; RV64IF-NEXT: ret 1391; 1392; RV64IZFINX-LABEL: lrint_f32: 1393; RV64IZFINX: # %bb.0: 1394; RV64IZFINX-NEXT: fcvt.l.s a0, a0 1395; RV64IZFINX-NEXT: ret 1396; 1397; RV32I-LABEL: lrint_f32: 1398; RV32I: # %bb.0: 1399; RV32I-NEXT: addi sp, sp, -16 1400; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1401; RV32I-NEXT: call lrintf 1402; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1403; RV32I-NEXT: addi sp, sp, 16 1404; RV32I-NEXT: ret 1405; 1406; RV64I-LABEL: lrint_f32: 1407; RV64I: # %bb.0: 1408; RV64I-NEXT: addi sp, sp, -16 1409; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1410; RV64I-NEXT: call lrintf 1411; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1412; RV64I-NEXT: addi sp, sp, 16 1413; RV64I-NEXT: ret 1414 %1 = call iXLen @llvm.lrint.iXLen.f32(float %a) 1415 ret iXLen %1 1416} 1417 1418declare i32 @llvm.lround.i32.f32(float) 1419declare i64 @llvm.lround.i64.f32(float) 1420 1421define iXLen @lround_f32(float %a) nounwind { 1422; RV32IF-LABEL: lround_f32: 1423; RV32IF: # %bb.0: 1424; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm 1425; RV32IF-NEXT: ret 1426; 1427; RV32IZFINX-LABEL: lround_f32: 1428; RV32IZFINX: # %bb.0: 1429; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm 1430; RV32IZFINX-NEXT: ret 1431; 1432; RV64IF-LABEL: lround_f32: 1433; RV64IF: # %bb.0: 1434; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm 1435; RV64IF-NEXT: ret 1436; 1437; RV64IZFINX-LABEL: lround_f32: 1438; RV64IZFINX: # %bb.0: 1439; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm 1440; RV64IZFINX-NEXT: ret 1441; 1442; RV32I-LABEL: lround_f32: 1443; RV32I: # %bb.0: 1444; RV32I-NEXT: addi sp, sp, -16 1445; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1446; RV32I-NEXT: call lroundf 1447; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1448; RV32I-NEXT: addi sp, sp, 16 1449; RV32I-NEXT: ret 1450; 1451; RV64I-LABEL: lround_f32: 1452; RV64I: # %bb.0: 1453; RV64I-NEXT: addi sp, sp, -16 1454; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1455; RV64I-NEXT: call lroundf 1456; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1457; RV64I-NEXT: addi sp, sp, 16 1458; RV64I-NEXT: ret 1459 %1 = call iXLen @llvm.lround.iXLen.f32(float %a) 1460 ret iXLen %1 1461} 1462 1463; We support i32 lround on RV64 even though long isn't 32 bits. This is needed 1464; by flang. 1465define i32 @lround_i32_f32(float %a) nounwind { 1466; RV32IF-LABEL: lround_i32_f32: 1467; RV32IF: # %bb.0: 1468; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm 1469; RV32IF-NEXT: ret 1470; 1471; RV32IZFINX-LABEL: lround_i32_f32: 1472; RV32IZFINX: # %bb.0: 1473; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rmm 1474; RV32IZFINX-NEXT: ret 1475; 1476; RV64IF-LABEL: lround_i32_f32: 1477; RV64IF: # %bb.0: 1478; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm 1479; RV64IF-NEXT: ret 1480; 1481; RV64IZFINX-LABEL: lround_i32_f32: 1482; RV64IZFINX: # %bb.0: 1483; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rmm 1484; RV64IZFINX-NEXT: ret 1485; 1486; RV32I-LABEL: lround_i32_f32: 1487; RV32I: # %bb.0: 1488; RV32I-NEXT: addi sp, sp, -16 1489; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1490; RV32I-NEXT: call lroundf 1491; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1492; RV32I-NEXT: addi sp, sp, 16 1493; RV32I-NEXT: ret 1494; 1495; RV64I-LABEL: lround_i32_f32: 1496; RV64I: # %bb.0: 1497; RV64I-NEXT: addi sp, sp, -16 1498; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1499; RV64I-NEXT: call lroundf 1500; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1501; RV64I-NEXT: addi sp, sp, 16 1502; RV64I-NEXT: ret 1503 %1 = call i32 @llvm.lround.i32.f32(float %a) 1504 ret i32 %1 1505} 1506 1507declare i64 @llvm.llrint.i64.f32(float) 1508 1509define i64 @llrint_f32(float %a) nounwind { 1510; RV32IF-LABEL: llrint_f32: 1511; RV32IF: # %bb.0: 1512; RV32IF-NEXT: addi sp, sp, -16 1513; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1514; RV32IF-NEXT: call llrintf 1515; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1516; RV32IF-NEXT: addi sp, sp, 16 1517; RV32IF-NEXT: ret 1518; 1519; RV32IZFINX-LABEL: llrint_f32: 1520; RV32IZFINX: # %bb.0: 1521; RV32IZFINX-NEXT: addi sp, sp, -16 1522; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1523; RV32IZFINX-NEXT: call llrintf 1524; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1525; RV32IZFINX-NEXT: addi sp, sp, 16 1526; RV32IZFINX-NEXT: ret 1527; 1528; RV64IF-LABEL: llrint_f32: 1529; RV64IF: # %bb.0: 1530; RV64IF-NEXT: fcvt.l.s a0, fa0 1531; RV64IF-NEXT: ret 1532; 1533; RV64IZFINX-LABEL: llrint_f32: 1534; RV64IZFINX: # %bb.0: 1535; RV64IZFINX-NEXT: fcvt.l.s a0, a0 1536; RV64IZFINX-NEXT: ret 1537; 1538; RV32I-LABEL: llrint_f32: 1539; RV32I: # %bb.0: 1540; RV32I-NEXT: addi sp, sp, -16 1541; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1542; RV32I-NEXT: call llrintf 1543; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1544; RV32I-NEXT: addi sp, sp, 16 1545; RV32I-NEXT: ret 1546; 1547; RV64I-LABEL: llrint_f32: 1548; RV64I: # %bb.0: 1549; RV64I-NEXT: addi sp, sp, -16 1550; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1551; RV64I-NEXT: call llrintf 1552; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1553; RV64I-NEXT: addi sp, sp, 16 1554; RV64I-NEXT: ret 1555 %1 = call i64 @llvm.llrint.i64.f32(float %a) 1556 ret i64 %1 1557} 1558 1559declare i64 @llvm.llround.i64.f32(float) 1560 1561define i64 @llround_f32(float %a) nounwind { 1562; RV32IF-LABEL: llround_f32: 1563; RV32IF: # %bb.0: 1564; RV32IF-NEXT: addi sp, sp, -16 1565; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1566; RV32IF-NEXT: call llroundf 1567; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1568; RV32IF-NEXT: addi sp, sp, 16 1569; RV32IF-NEXT: ret 1570; 1571; RV32IZFINX-LABEL: llround_f32: 1572; RV32IZFINX: # %bb.0: 1573; RV32IZFINX-NEXT: addi sp, sp, -16 1574; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1575; RV32IZFINX-NEXT: call llroundf 1576; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1577; RV32IZFINX-NEXT: addi sp, sp, 16 1578; RV32IZFINX-NEXT: ret 1579; 1580; RV64IF-LABEL: llround_f32: 1581; RV64IF: # %bb.0: 1582; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm 1583; RV64IF-NEXT: ret 1584; 1585; RV64IZFINX-LABEL: llround_f32: 1586; RV64IZFINX: # %bb.0: 1587; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm 1588; RV64IZFINX-NEXT: ret 1589; 1590; RV32I-LABEL: llround_f32: 1591; RV32I: # %bb.0: 1592; RV32I-NEXT: addi sp, sp, -16 1593; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1594; RV32I-NEXT: call llroundf 1595; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1596; RV32I-NEXT: addi sp, sp, 16 1597; RV32I-NEXT: ret 1598; 1599; RV64I-LABEL: llround_f32: 1600; RV64I: # %bb.0: 1601; RV64I-NEXT: addi sp, sp, -16 1602; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1603; RV64I-NEXT: call llroundf 1604; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1605; RV64I-NEXT: addi sp, sp, 16 1606; RV64I-NEXT: ret 1607 %1 = call i64 @llvm.llround.i64.f32(float %a) 1608 ret i64 %1 1609} 1610 1611declare i1 @llvm.is.fpclass.f32(float, i32) 1612define i1 @fpclass(float %x) { 1613; RV32IF-LABEL: fpclass: 1614; RV32IF: # %bb.0: 1615; RV32IF-NEXT: fclass.s a0, fa0 1616; RV32IF-NEXT: andi a0, a0, 927 1617; RV32IF-NEXT: snez a0, a0 1618; RV32IF-NEXT: ret 1619; 1620; RV32IZFINX-LABEL: fpclass: 1621; RV32IZFINX: # %bb.0: 1622; RV32IZFINX-NEXT: fclass.s a0, a0 1623; RV32IZFINX-NEXT: andi a0, a0, 927 1624; RV32IZFINX-NEXT: snez a0, a0 1625; RV32IZFINX-NEXT: ret 1626; 1627; RV64IF-LABEL: fpclass: 1628; RV64IF: # %bb.0: 1629; RV64IF-NEXT: fclass.s a0, fa0 1630; RV64IF-NEXT: andi a0, a0, 927 1631; RV64IF-NEXT: snez a0, a0 1632; RV64IF-NEXT: ret 1633; 1634; RV64IZFINX-LABEL: fpclass: 1635; RV64IZFINX: # %bb.0: 1636; RV64IZFINX-NEXT: fclass.s a0, a0 1637; RV64IZFINX-NEXT: andi a0, a0, 927 1638; RV64IZFINX-NEXT: snez a0, a0 1639; RV64IZFINX-NEXT: ret 1640; 1641; RV32I-LABEL: fpclass: 1642; RV32I: # %bb.0: 1643; RV32I-NEXT: slli a1, a0, 1 1644; RV32I-NEXT: lui a2, 2048 1645; RV32I-NEXT: slti a0, a0, 0 1646; RV32I-NEXT: lui a3, 522240 1647; RV32I-NEXT: lui a4, 1046528 1648; RV32I-NEXT: srli a1, a1, 1 1649; RV32I-NEXT: addi a2, a2, -1 1650; RV32I-NEXT: addi a5, a1, -1 1651; RV32I-NEXT: sltu a2, a5, a2 1652; RV32I-NEXT: xor a5, a1, a3 1653; RV32I-NEXT: slt a3, a3, a1 1654; RV32I-NEXT: add a4, a1, a4 1655; RV32I-NEXT: seqz a1, a1 1656; RV32I-NEXT: seqz a5, a5 1657; RV32I-NEXT: srli a4, a4, 24 1658; RV32I-NEXT: and a2, a2, a0 1659; RV32I-NEXT: or a1, a1, a5 1660; RV32I-NEXT: sltiu a4, a4, 127 1661; RV32I-NEXT: or a1, a1, a2 1662; RV32I-NEXT: or a1, a1, a3 1663; RV32I-NEXT: and a0, a4, a0 1664; RV32I-NEXT: or a0, a1, a0 1665; RV32I-NEXT: ret 1666; 1667; RV64I-LABEL: fpclass: 1668; RV64I: # %bb.0: 1669; RV64I-NEXT: sext.w a1, a0 1670; RV64I-NEXT: slli a0, a0, 33 1671; RV64I-NEXT: lui a2, 2048 1672; RV64I-NEXT: lui a3, 522240 1673; RV64I-NEXT: lui a4, 1046528 1674; RV64I-NEXT: srli a0, a0, 33 1675; RV64I-NEXT: addiw a2, a2, -1 1676; RV64I-NEXT: slti a1, a1, 0 1677; RV64I-NEXT: addi a5, a0, -1 1678; RV64I-NEXT: sltu a2, a5, a2 1679; RV64I-NEXT: xor a5, a0, a3 1680; RV64I-NEXT: slt a3, a3, a0 1681; RV64I-NEXT: add a4, a0, a4 1682; RV64I-NEXT: seqz a0, a0 1683; RV64I-NEXT: seqz a5, a5 1684; RV64I-NEXT: srliw a4, a4, 24 1685; RV64I-NEXT: and a2, a2, a1 1686; RV64I-NEXT: or a0, a0, a5 1687; RV64I-NEXT: sltiu a4, a4, 127 1688; RV64I-NEXT: or a0, a0, a2 1689; RV64I-NEXT: or a0, a0, a3 1690; RV64I-NEXT: and a1, a4, a1 1691; RV64I-NEXT: or a0, a0, a1 1692; RV64I-NEXT: ret 1693 %cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639) 1694 ret i1 %cmp 1695} 1696 1697define i1 @isnan_fpclass(float %x) { 1698; RV32IF-LABEL: isnan_fpclass: 1699; RV32IF: # %bb.0: 1700; RV32IF-NEXT: fclass.s a0, fa0 1701; RV32IF-NEXT: andi a0, a0, 768 1702; RV32IF-NEXT: snez a0, a0 1703; RV32IF-NEXT: ret 1704; 1705; RV32IZFINX-LABEL: isnan_fpclass: 1706; RV32IZFINX: # %bb.0: 1707; RV32IZFINX-NEXT: fclass.s a0, a0 1708; RV32IZFINX-NEXT: andi a0, a0, 768 1709; RV32IZFINX-NEXT: snez a0, a0 1710; RV32IZFINX-NEXT: ret 1711; 1712; RV64IF-LABEL: isnan_fpclass: 1713; RV64IF: # %bb.0: 1714; RV64IF-NEXT: fclass.s a0, fa0 1715; RV64IF-NEXT: andi a0, a0, 768 1716; RV64IF-NEXT: snez a0, a0 1717; RV64IF-NEXT: ret 1718; 1719; RV64IZFINX-LABEL: isnan_fpclass: 1720; RV64IZFINX: # %bb.0: 1721; RV64IZFINX-NEXT: fclass.s a0, a0 1722; RV64IZFINX-NEXT: andi a0, a0, 768 1723; RV64IZFINX-NEXT: snez a0, a0 1724; RV64IZFINX-NEXT: ret 1725; 1726; RV32I-LABEL: isnan_fpclass: 1727; RV32I: # %bb.0: 1728; RV32I-NEXT: slli a0, a0, 1 1729; RV32I-NEXT: srli a0, a0, 1 1730; RV32I-NEXT: lui a1, 522240 1731; RV32I-NEXT: slt a0, a1, a0 1732; RV32I-NEXT: ret 1733; 1734; RV64I-LABEL: isnan_fpclass: 1735; RV64I: # %bb.0: 1736; RV64I-NEXT: slli a0, a0, 33 1737; RV64I-NEXT: srli a0, a0, 33 1738; RV64I-NEXT: lui a1, 522240 1739; RV64I-NEXT: slt a0, a1, a0 1740; RV64I-NEXT: ret 1741 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan 1742 ret i1 %1 1743} 1744 1745define i1 @isqnan_fpclass(float %x) { 1746; RV32IF-LABEL: isqnan_fpclass: 1747; RV32IF: # %bb.0: 1748; RV32IF-NEXT: fclass.s a0, fa0 1749; RV32IF-NEXT: srli a0, a0, 9 1750; RV32IF-NEXT: ret 1751; 1752; RV32IZFINX-LABEL: isqnan_fpclass: 1753; RV32IZFINX: # %bb.0: 1754; RV32IZFINX-NEXT: fclass.s a0, a0 1755; RV32IZFINX-NEXT: srli a0, a0, 9 1756; RV32IZFINX-NEXT: ret 1757; 1758; RV64IF-LABEL: isqnan_fpclass: 1759; RV64IF: # %bb.0: 1760; RV64IF-NEXT: fclass.s a0, fa0 1761; RV64IF-NEXT: srli a0, a0, 9 1762; RV64IF-NEXT: ret 1763; 1764; RV64IZFINX-LABEL: isqnan_fpclass: 1765; RV64IZFINX: # %bb.0: 1766; RV64IZFINX-NEXT: fclass.s a0, a0 1767; RV64IZFINX-NEXT: srli a0, a0, 9 1768; RV64IZFINX-NEXT: ret 1769; 1770; RV32I-LABEL: isqnan_fpclass: 1771; RV32I: # %bb.0: 1772; RV32I-NEXT: slli a0, a0, 1 1773; RV32I-NEXT: lui a1, 523264 1774; RV32I-NEXT: srli a0, a0, 1 1775; RV32I-NEXT: addi a1, a1, -1 1776; RV32I-NEXT: slt a0, a1, a0 1777; RV32I-NEXT: ret 1778; 1779; RV64I-LABEL: isqnan_fpclass: 1780; RV64I: # %bb.0: 1781; RV64I-NEXT: slli a0, a0, 33 1782; RV64I-NEXT: lui a1, 523264 1783; RV64I-NEXT: srli a0, a0, 33 1784; RV64I-NEXT: addiw a1, a1, -1 1785; RV64I-NEXT: slt a0, a1, a0 1786; RV64I-NEXT: ret 1787 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; qnan 1788 ret i1 %1 1789} 1790 1791define i1 @issnan_fpclass(float %x) { 1792; RV32IF-LABEL: issnan_fpclass: 1793; RV32IF: # %bb.0: 1794; RV32IF-NEXT: fclass.s a0, fa0 1795; RV32IF-NEXT: slli a0, a0, 23 1796; RV32IF-NEXT: srli a0, a0, 31 1797; RV32IF-NEXT: ret 1798; 1799; RV32IZFINX-LABEL: issnan_fpclass: 1800; RV32IZFINX: # %bb.0: 1801; RV32IZFINX-NEXT: fclass.s a0, a0 1802; RV32IZFINX-NEXT: slli a0, a0, 23 1803; RV32IZFINX-NEXT: srli a0, a0, 31 1804; RV32IZFINX-NEXT: ret 1805; 1806; RV64IF-LABEL: issnan_fpclass: 1807; RV64IF: # %bb.0: 1808; RV64IF-NEXT: fclass.s a0, fa0 1809; RV64IF-NEXT: slli a0, a0, 55 1810; RV64IF-NEXT: srli a0, a0, 63 1811; RV64IF-NEXT: ret 1812; 1813; RV64IZFINX-LABEL: issnan_fpclass: 1814; RV64IZFINX: # %bb.0: 1815; RV64IZFINX-NEXT: fclass.s a0, a0 1816; RV64IZFINX-NEXT: slli a0, a0, 55 1817; RV64IZFINX-NEXT: srli a0, a0, 63 1818; RV64IZFINX-NEXT: ret 1819; 1820; RV32I-LABEL: issnan_fpclass: 1821; RV32I: # %bb.0: 1822; RV32I-NEXT: slli a0, a0, 1 1823; RV32I-NEXT: lui a1, 523264 1824; RV32I-NEXT: lui a2, 522240 1825; RV32I-NEXT: srli a0, a0, 1 1826; RV32I-NEXT: slt a1, a0, a1 1827; RV32I-NEXT: slt a0, a2, a0 1828; RV32I-NEXT: and a0, a0, a1 1829; RV32I-NEXT: ret 1830; 1831; RV64I-LABEL: issnan_fpclass: 1832; RV64I: # %bb.0: 1833; RV64I-NEXT: slli a0, a0, 33 1834; RV64I-NEXT: lui a1, 523264 1835; RV64I-NEXT: lui a2, 522240 1836; RV64I-NEXT: srli a0, a0, 33 1837; RV64I-NEXT: slt a1, a0, a1 1838; RV64I-NEXT: slt a0, a2, a0 1839; RV64I-NEXT: and a0, a0, a1 1840; RV64I-NEXT: ret 1841 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; snan 1842 ret i1 %1 1843} 1844 1845define i1 @isinf_fpclass(float %x) { 1846; RV32IF-LABEL: isinf_fpclass: 1847; RV32IF: # %bb.0: 1848; RV32IF-NEXT: fclass.s a0, fa0 1849; RV32IF-NEXT: andi a0, a0, 129 1850; RV32IF-NEXT: snez a0, a0 1851; RV32IF-NEXT: ret 1852; 1853; RV32IZFINX-LABEL: isinf_fpclass: 1854; RV32IZFINX: # %bb.0: 1855; RV32IZFINX-NEXT: fclass.s a0, a0 1856; RV32IZFINX-NEXT: andi a0, a0, 129 1857; RV32IZFINX-NEXT: snez a0, a0 1858; RV32IZFINX-NEXT: ret 1859; 1860; RV64IF-LABEL: isinf_fpclass: 1861; RV64IF: # %bb.0: 1862; RV64IF-NEXT: fclass.s a0, fa0 1863; RV64IF-NEXT: andi a0, a0, 129 1864; RV64IF-NEXT: snez a0, a0 1865; RV64IF-NEXT: ret 1866; 1867; RV64IZFINX-LABEL: isinf_fpclass: 1868; RV64IZFINX: # %bb.0: 1869; RV64IZFINX-NEXT: fclass.s a0, a0 1870; RV64IZFINX-NEXT: andi a0, a0, 129 1871; RV64IZFINX-NEXT: snez a0, a0 1872; RV64IZFINX-NEXT: ret 1873; 1874; RV32I-LABEL: isinf_fpclass: 1875; RV32I: # %bb.0: 1876; RV32I-NEXT: slli a0, a0, 1 1877; RV32I-NEXT: srli a0, a0, 1 1878; RV32I-NEXT: lui a1, 522240 1879; RV32I-NEXT: xor a0, a0, a1 1880; RV32I-NEXT: seqz a0, a0 1881; RV32I-NEXT: ret 1882; 1883; RV64I-LABEL: isinf_fpclass: 1884; RV64I: # %bb.0: 1885; RV64I-NEXT: slli a0, a0, 33 1886; RV64I-NEXT: srli a0, a0, 33 1887; RV64I-NEXT: lui a1, 522240 1888; RV64I-NEXT: xor a0, a0, a1 1889; RV64I-NEXT: seqz a0, a0 1890; RV64I-NEXT: ret 1891 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf" 1892 ret i1 %1 1893} 1894 1895define i1 @isposinf_fpclass(float %x) { 1896; RV32IF-LABEL: isposinf_fpclass: 1897; RV32IF: # %bb.0: 1898; RV32IF-NEXT: fclass.s a0, fa0 1899; RV32IF-NEXT: slli a0, a0, 24 1900; RV32IF-NEXT: srli a0, a0, 31 1901; RV32IF-NEXT: ret 1902; 1903; RV32IZFINX-LABEL: isposinf_fpclass: 1904; RV32IZFINX: # %bb.0: 1905; RV32IZFINX-NEXT: fclass.s a0, a0 1906; RV32IZFINX-NEXT: slli a0, a0, 24 1907; RV32IZFINX-NEXT: srli a0, a0, 31 1908; RV32IZFINX-NEXT: ret 1909; 1910; RV64IF-LABEL: isposinf_fpclass: 1911; RV64IF: # %bb.0: 1912; RV64IF-NEXT: fclass.s a0, fa0 1913; RV64IF-NEXT: slli a0, a0, 56 1914; RV64IF-NEXT: srli a0, a0, 63 1915; RV64IF-NEXT: ret 1916; 1917; RV64IZFINX-LABEL: isposinf_fpclass: 1918; RV64IZFINX: # %bb.0: 1919; RV64IZFINX-NEXT: fclass.s a0, a0 1920; RV64IZFINX-NEXT: slli a0, a0, 56 1921; RV64IZFINX-NEXT: srli a0, a0, 63 1922; RV64IZFINX-NEXT: ret 1923; 1924; RV32I-LABEL: isposinf_fpclass: 1925; RV32I: # %bb.0: 1926; RV32I-NEXT: lui a1, 522240 1927; RV32I-NEXT: xor a0, a0, a1 1928; RV32I-NEXT: seqz a0, a0 1929; RV32I-NEXT: ret 1930; 1931; RV64I-LABEL: isposinf_fpclass: 1932; RV64I: # %bb.0: 1933; RV64I-NEXT: sext.w a0, a0 1934; RV64I-NEXT: lui a1, 522240 1935; RV64I-NEXT: xor a0, a0, a1 1936; RV64I-NEXT: seqz a0, a0 1937; RV64I-NEXT: ret 1938 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf" 1939 ret i1 %1 1940} 1941 1942define i1 @isneginf_fpclass(float %x) { 1943; RV32IF-LABEL: isneginf_fpclass: 1944; RV32IF: # %bb.0: 1945; RV32IF-NEXT: fclass.s a0, fa0 1946; RV32IF-NEXT: andi a0, a0, 1 1947; RV32IF-NEXT: ret 1948; 1949; RV32IZFINX-LABEL: isneginf_fpclass: 1950; RV32IZFINX: # %bb.0: 1951; RV32IZFINX-NEXT: fclass.s a0, a0 1952; RV32IZFINX-NEXT: andi a0, a0, 1 1953; RV32IZFINX-NEXT: ret 1954; 1955; RV64IF-LABEL: isneginf_fpclass: 1956; RV64IF: # %bb.0: 1957; RV64IF-NEXT: fclass.s a0, fa0 1958; RV64IF-NEXT: andi a0, a0, 1 1959; RV64IF-NEXT: ret 1960; 1961; RV64IZFINX-LABEL: isneginf_fpclass: 1962; RV64IZFINX: # %bb.0: 1963; RV64IZFINX-NEXT: fclass.s a0, a0 1964; RV64IZFINX-NEXT: andi a0, a0, 1 1965; RV64IZFINX-NEXT: ret 1966; 1967; RV32I-LABEL: isneginf_fpclass: 1968; RV32I: # %bb.0: 1969; RV32I-NEXT: lui a1, 1046528 1970; RV32I-NEXT: xor a0, a0, a1 1971; RV32I-NEXT: seqz a0, a0 1972; RV32I-NEXT: ret 1973; 1974; RV64I-LABEL: isneginf_fpclass: 1975; RV64I: # %bb.0: 1976; RV64I-NEXT: sext.w a0, a0 1977; RV64I-NEXT: lui a1, 1046528 1978; RV64I-NEXT: xor a0, a0, a1 1979; RV64I-NEXT: seqz a0, a0 1980; RV64I-NEXT: ret 1981 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf" 1982 ret i1 %1 1983} 1984 1985define i1 @isfinite_fpclass(float %x) { 1986; RV32IF-LABEL: isfinite_fpclass: 1987; RV32IF: # %bb.0: 1988; RV32IF-NEXT: fclass.s a0, fa0 1989; RV32IF-NEXT: andi a0, a0, 126 1990; RV32IF-NEXT: snez a0, a0 1991; RV32IF-NEXT: ret 1992; 1993; RV32IZFINX-LABEL: isfinite_fpclass: 1994; RV32IZFINX: # %bb.0: 1995; RV32IZFINX-NEXT: fclass.s a0, a0 1996; RV32IZFINX-NEXT: andi a0, a0, 126 1997; RV32IZFINX-NEXT: snez a0, a0 1998; RV32IZFINX-NEXT: ret 1999; 2000; RV64IF-LABEL: isfinite_fpclass: 2001; RV64IF: # %bb.0: 2002; RV64IF-NEXT: fclass.s a0, fa0 2003; RV64IF-NEXT: andi a0, a0, 126 2004; RV64IF-NEXT: snez a0, a0 2005; RV64IF-NEXT: ret 2006; 2007; RV64IZFINX-LABEL: isfinite_fpclass: 2008; RV64IZFINX: # %bb.0: 2009; RV64IZFINX-NEXT: fclass.s a0, a0 2010; RV64IZFINX-NEXT: andi a0, a0, 126 2011; RV64IZFINX-NEXT: snez a0, a0 2012; RV64IZFINX-NEXT: ret 2013; 2014; RV32I-LABEL: isfinite_fpclass: 2015; RV32I: # %bb.0: 2016; RV32I-NEXT: slli a0, a0, 1 2017; RV32I-NEXT: srli a0, a0, 1 2018; RV32I-NEXT: lui a1, 522240 2019; RV32I-NEXT: slt a0, a0, a1 2020; RV32I-NEXT: ret 2021; 2022; RV64I-LABEL: isfinite_fpclass: 2023; RV64I: # %bb.0: 2024; RV64I-NEXT: slli a0, a0, 33 2025; RV64I-NEXT: srli a0, a0, 33 2026; RV64I-NEXT: lui a1, 522240 2027; RV64I-NEXT: slt a0, a0, a1 2028; RV64I-NEXT: ret 2029 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite" 2030 ret i1 %1 2031} 2032 2033define i1 @isposfinite_fpclass(float %x) { 2034; RV32IF-LABEL: isposfinite_fpclass: 2035; RV32IF: # %bb.0: 2036; RV32IF-NEXT: fclass.s a0, fa0 2037; RV32IF-NEXT: andi a0, a0, 112 2038; RV32IF-NEXT: snez a0, a0 2039; RV32IF-NEXT: ret 2040; 2041; RV32IZFINX-LABEL: isposfinite_fpclass: 2042; RV32IZFINX: # %bb.0: 2043; RV32IZFINX-NEXT: fclass.s a0, a0 2044; RV32IZFINX-NEXT: andi a0, a0, 112 2045; RV32IZFINX-NEXT: snez a0, a0 2046; RV32IZFINX-NEXT: ret 2047; 2048; RV64IF-LABEL: isposfinite_fpclass: 2049; RV64IF: # %bb.0: 2050; RV64IF-NEXT: fclass.s a0, fa0 2051; RV64IF-NEXT: andi a0, a0, 112 2052; RV64IF-NEXT: snez a0, a0 2053; RV64IF-NEXT: ret 2054; 2055; RV64IZFINX-LABEL: isposfinite_fpclass: 2056; RV64IZFINX: # %bb.0: 2057; RV64IZFINX-NEXT: fclass.s a0, a0 2058; RV64IZFINX-NEXT: andi a0, a0, 112 2059; RV64IZFINX-NEXT: snez a0, a0 2060; RV64IZFINX-NEXT: ret 2061; 2062; RV32I-LABEL: isposfinite_fpclass: 2063; RV32I: # %bb.0: 2064; RV32I-NEXT: srli a0, a0, 23 2065; RV32I-NEXT: sltiu a0, a0, 255 2066; RV32I-NEXT: ret 2067; 2068; RV64I-LABEL: isposfinite_fpclass: 2069; RV64I: # %bb.0: 2070; RV64I-NEXT: srliw a0, a0, 23 2071; RV64I-NEXT: sltiu a0, a0, 255 2072; RV64I-NEXT: ret 2073 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite" 2074 ret i1 %1 2075} 2076 2077define i1 @isnegfinite_fpclass(float %x) { 2078; RV32IF-LABEL: isnegfinite_fpclass: 2079; RV32IF: # %bb.0: 2080; RV32IF-NEXT: fclass.s a0, fa0 2081; RV32IF-NEXT: andi a0, a0, 14 2082; RV32IF-NEXT: snez a0, a0 2083; RV32IF-NEXT: ret 2084; 2085; RV32IZFINX-LABEL: isnegfinite_fpclass: 2086; RV32IZFINX: # %bb.0: 2087; RV32IZFINX-NEXT: fclass.s a0, a0 2088; RV32IZFINX-NEXT: andi a0, a0, 14 2089; RV32IZFINX-NEXT: snez a0, a0 2090; RV32IZFINX-NEXT: ret 2091; 2092; RV64IF-LABEL: isnegfinite_fpclass: 2093; RV64IF: # %bb.0: 2094; RV64IF-NEXT: fclass.s a0, fa0 2095; RV64IF-NEXT: andi a0, a0, 14 2096; RV64IF-NEXT: snez a0, a0 2097; RV64IF-NEXT: ret 2098; 2099; RV64IZFINX-LABEL: isnegfinite_fpclass: 2100; RV64IZFINX: # %bb.0: 2101; RV64IZFINX-NEXT: fclass.s a0, a0 2102; RV64IZFINX-NEXT: andi a0, a0, 14 2103; RV64IZFINX-NEXT: snez a0, a0 2104; RV64IZFINX-NEXT: ret 2105; 2106; RV32I-LABEL: isnegfinite_fpclass: 2107; RV32I: # %bb.0: 2108; RV32I-NEXT: slli a1, a0, 1 2109; RV32I-NEXT: lui a2, 522240 2110; RV32I-NEXT: srli a1, a1, 1 2111; RV32I-NEXT: slt a1, a1, a2 2112; RV32I-NEXT: slti a0, a0, 0 2113; RV32I-NEXT: and a0, a1, a0 2114; RV32I-NEXT: ret 2115; 2116; RV64I-LABEL: isnegfinite_fpclass: 2117; RV64I: # %bb.0: 2118; RV64I-NEXT: sext.w a1, a0 2119; RV64I-NEXT: slli a0, a0, 33 2120; RV64I-NEXT: lui a2, 522240 2121; RV64I-NEXT: srli a0, a0, 33 2122; RV64I-NEXT: slt a0, a0, a2 2123; RV64I-NEXT: slti a1, a1, 0 2124; RV64I-NEXT: and a0, a0, a1 2125; RV64I-NEXT: ret 2126 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite" 2127 ret i1 %1 2128} 2129 2130define i1 @isnotfinite_fpclass(float %x) { 2131; RV32IF-LABEL: isnotfinite_fpclass: 2132; RV32IF: # %bb.0: 2133; RV32IF-NEXT: fclass.s a0, fa0 2134; RV32IF-NEXT: andi a0, a0, 897 2135; RV32IF-NEXT: snez a0, a0 2136; RV32IF-NEXT: ret 2137; 2138; RV32IZFINX-LABEL: isnotfinite_fpclass: 2139; RV32IZFINX: # %bb.0: 2140; RV32IZFINX-NEXT: fclass.s a0, a0 2141; RV32IZFINX-NEXT: andi a0, a0, 897 2142; RV32IZFINX-NEXT: snez a0, a0 2143; RV32IZFINX-NEXT: ret 2144; 2145; RV64IF-LABEL: isnotfinite_fpclass: 2146; RV64IF: # %bb.0: 2147; RV64IF-NEXT: fclass.s a0, fa0 2148; RV64IF-NEXT: andi a0, a0, 897 2149; RV64IF-NEXT: snez a0, a0 2150; RV64IF-NEXT: ret 2151; 2152; RV64IZFINX-LABEL: isnotfinite_fpclass: 2153; RV64IZFINX: # %bb.0: 2154; RV64IZFINX-NEXT: fclass.s a0, a0 2155; RV64IZFINX-NEXT: andi a0, a0, 897 2156; RV64IZFINX-NEXT: snez a0, a0 2157; RV64IZFINX-NEXT: ret 2158; 2159; RV32I-LABEL: isnotfinite_fpclass: 2160; RV32I: # %bb.0: 2161; RV32I-NEXT: slli a0, a0, 1 2162; RV32I-NEXT: lui a1, 522240 2163; RV32I-NEXT: srli a0, a0, 1 2164; RV32I-NEXT: addi a1, a1, -1 2165; RV32I-NEXT: slt a0, a1, a0 2166; RV32I-NEXT: ret 2167; 2168; RV64I-LABEL: isnotfinite_fpclass: 2169; RV64I: # %bb.0: 2170; RV64I-NEXT: slli a0, a0, 33 2171; RV64I-NEXT: lui a1, 522240 2172; RV64I-NEXT: srli a0, a0, 33 2173; RV64I-NEXT: addiw a1, a1, -1 2174; RV64I-NEXT: slt a0, a1, a0 2175; RV64I-NEXT: ret 2176 %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan" 2177 ret i1 %1 2178} 2179 2180define float @tan_f32(float %a) nounwind { 2181; RV32IF-LABEL: tan_f32: 2182; RV32IF: # %bb.0: 2183; RV32IF-NEXT: tail tanf 2184; 2185; RV32IZFINX-LABEL: tan_f32: 2186; RV32IZFINX: # %bb.0: 2187; RV32IZFINX-NEXT: tail tanf 2188; 2189; RV64IF-LABEL: tan_f32: 2190; RV64IF: # %bb.0: 2191; RV64IF-NEXT: tail tanf 2192; 2193; RV64IZFINX-LABEL: tan_f32: 2194; RV64IZFINX: # %bb.0: 2195; RV64IZFINX-NEXT: tail tanf 2196; 2197; RV32I-LABEL: tan_f32: 2198; RV32I: # %bb.0: 2199; RV32I-NEXT: addi sp, sp, -16 2200; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2201; RV32I-NEXT: call tanf 2202; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2203; RV32I-NEXT: addi sp, sp, 16 2204; RV32I-NEXT: ret 2205; 2206; RV64I-LABEL: tan_f32: 2207; RV64I: # %bb.0: 2208; RV64I-NEXT: addi sp, sp, -16 2209; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2210; RV64I-NEXT: call tanf 2211; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2212; RV64I-NEXT: addi sp, sp, 16 2213; RV64I-NEXT: ret 2214 %1 = call float @llvm.tan.f32(float %a) 2215 ret float %1 2216} 2217 2218declare float @llvm.maximumnum.f32(float, float) 2219 2220define float @maximumnum_float(float %x, float %y) { 2221; RV32IF-LABEL: maximumnum_float: 2222; RV32IF: # %bb.0: 2223; RV32IF-NEXT: fmax.s fa0, fa0, fa1 2224; RV32IF-NEXT: ret 2225; 2226; RV32IZFINX-LABEL: maximumnum_float: 2227; RV32IZFINX: # %bb.0: 2228; RV32IZFINX-NEXT: fmax.s a0, a0, a1 2229; RV32IZFINX-NEXT: ret 2230; 2231; RV64IF-LABEL: maximumnum_float: 2232; RV64IF: # %bb.0: 2233; RV64IF-NEXT: fmax.s fa0, fa0, fa1 2234; RV64IF-NEXT: ret 2235; 2236; RV64IZFINX-LABEL: maximumnum_float: 2237; RV64IZFINX: # %bb.0: 2238; RV64IZFINX-NEXT: fmax.s a0, a0, a1 2239; RV64IZFINX-NEXT: ret 2240; 2241; RV32I-LABEL: maximumnum_float: 2242; RV32I: # %bb.0: 2243; RV32I-NEXT: addi sp, sp, -16 2244; RV32I-NEXT: .cfi_def_cfa_offset 16 2245; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2246; RV32I-NEXT: .cfi_offset ra, -4 2247; RV32I-NEXT: call fmaximum_numf 2248; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2249; RV32I-NEXT: .cfi_restore ra 2250; RV32I-NEXT: addi sp, sp, 16 2251; RV32I-NEXT: .cfi_def_cfa_offset 0 2252; RV32I-NEXT: ret 2253; 2254; RV64I-LABEL: maximumnum_float: 2255; RV64I: # %bb.0: 2256; RV64I-NEXT: addi sp, sp, -16 2257; RV64I-NEXT: .cfi_def_cfa_offset 16 2258; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2259; RV64I-NEXT: .cfi_offset ra, -8 2260; RV64I-NEXT: call fmaximum_numf 2261; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2262; RV64I-NEXT: .cfi_restore ra 2263; RV64I-NEXT: addi sp, sp, 16 2264; RV64I-NEXT: .cfi_def_cfa_offset 0 2265; RV64I-NEXT: ret 2266 %z = call float @llvm.maximumnum.f32(float %x, float %y) 2267 ret float %z 2268} 2269 2270declare float @llvm.minimumnum.f32(float, float) 2271 2272define float @minimumnum_float(float %x, float %y) { 2273; RV32IF-LABEL: minimumnum_float: 2274; RV32IF: # %bb.0: 2275; RV32IF-NEXT: fmin.s fa0, fa0, fa1 2276; RV32IF-NEXT: ret 2277; 2278; RV32IZFINX-LABEL: minimumnum_float: 2279; RV32IZFINX: # %bb.0: 2280; RV32IZFINX-NEXT: fmin.s a0, a0, a1 2281; RV32IZFINX-NEXT: ret 2282; 2283; RV64IF-LABEL: minimumnum_float: 2284; RV64IF: # %bb.0: 2285; RV64IF-NEXT: fmin.s fa0, fa0, fa1 2286; RV64IF-NEXT: ret 2287; 2288; RV64IZFINX-LABEL: minimumnum_float: 2289; RV64IZFINX: # %bb.0: 2290; RV64IZFINX-NEXT: fmin.s a0, a0, a1 2291; RV64IZFINX-NEXT: ret 2292; 2293; RV32I-LABEL: minimumnum_float: 2294; RV32I: # %bb.0: 2295; RV32I-NEXT: addi sp, sp, -16 2296; RV32I-NEXT: .cfi_def_cfa_offset 16 2297; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2298; RV32I-NEXT: .cfi_offset ra, -4 2299; RV32I-NEXT: call fminimum_numf 2300; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2301; RV32I-NEXT: .cfi_restore ra 2302; RV32I-NEXT: addi sp, sp, 16 2303; RV32I-NEXT: .cfi_def_cfa_offset 0 2304; RV32I-NEXT: ret 2305; 2306; RV64I-LABEL: minimumnum_float: 2307; RV64I: # %bb.0: 2308; RV64I-NEXT: addi sp, sp, -16 2309; RV64I-NEXT: .cfi_def_cfa_offset 16 2310; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2311; RV64I-NEXT: .cfi_offset ra, -8 2312; RV64I-NEXT: call fminimum_numf 2313; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2314; RV64I-NEXT: .cfi_restore ra 2315; RV64I-NEXT: addi sp, sp, 16 2316; RV64I-NEXT: .cfi_def_cfa_offset 0 2317; RV64I-NEXT: ret 2318 %z = call float @llvm.minimumnum.f32(float %x, float %y) 2319 ret float %z 2320} 2321 2322define float @ldexp_float(float %x, i32 signext %y) nounwind { 2323; RV32IF-LABEL: ldexp_float: 2324; RV32IF: # %bb.0: 2325; RV32IF-NEXT: tail ldexpf 2326; 2327; RV32IZFINX-LABEL: ldexp_float: 2328; RV32IZFINX: # %bb.0: 2329; RV32IZFINX-NEXT: tail ldexpf 2330; 2331; RV64IF-LABEL: ldexp_float: 2332; RV64IF: # %bb.0: 2333; RV64IF-NEXT: addi sp, sp, -16 2334; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2335; RV64IF-NEXT: call ldexpf 2336; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2337; RV64IF-NEXT: addi sp, sp, 16 2338; RV64IF-NEXT: ret 2339; 2340; RV64IZFINX-LABEL: ldexp_float: 2341; RV64IZFINX: # %bb.0: 2342; RV64IZFINX-NEXT: addi sp, sp, -16 2343; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2344; RV64IZFINX-NEXT: call ldexpf 2345; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2346; RV64IZFINX-NEXT: addi sp, sp, 16 2347; RV64IZFINX-NEXT: ret 2348; 2349; RV32I-LABEL: ldexp_float: 2350; RV32I: # %bb.0: 2351; RV32I-NEXT: addi sp, sp, -16 2352; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2353; RV32I-NEXT: call ldexpf 2354; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2355; RV32I-NEXT: addi sp, sp, 16 2356; RV32I-NEXT: ret 2357; 2358; RV64I-LABEL: ldexp_float: 2359; RV64I: # %bb.0: 2360; RV64I-NEXT: addi sp, sp, -16 2361; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2362; RV64I-NEXT: call ldexpf 2363; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2364; RV64I-NEXT: addi sp, sp, 16 2365; RV64I-NEXT: ret 2366 %z = call float @llvm.ldexp.f32.i32(float %x, i32 %y) 2367 ret float %z 2368} 2369 2370define {float, i32} @frexp_float(float %x) nounwind { 2371; RV32IF-LABEL: frexp_float: 2372; RV32IF: # %bb.0: 2373; RV32IF-NEXT: addi sp, sp, -16 2374; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2375; RV32IF-NEXT: addi a0, sp, 8 2376; RV32IF-NEXT: call frexpf 2377; RV32IF-NEXT: lw a0, 8(sp) 2378; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2379; RV32IF-NEXT: addi sp, sp, 16 2380; RV32IF-NEXT: ret 2381; 2382; RV32IZFINX-LABEL: frexp_float: 2383; RV32IZFINX: # %bb.0: 2384; RV32IZFINX-NEXT: addi sp, sp, -16 2385; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2386; RV32IZFINX-NEXT: addi a1, sp, 8 2387; RV32IZFINX-NEXT: call frexpf 2388; RV32IZFINX-NEXT: lw a1, 8(sp) 2389; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2390; RV32IZFINX-NEXT: addi sp, sp, 16 2391; RV32IZFINX-NEXT: ret 2392; 2393; RV64IF-LABEL: frexp_float: 2394; RV64IF: # %bb.0: 2395; RV64IF-NEXT: addi sp, sp, -16 2396; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2397; RV64IF-NEXT: mv a0, sp 2398; RV64IF-NEXT: call frexpf 2399; RV64IF-NEXT: ld a0, 0(sp) 2400; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2401; RV64IF-NEXT: addi sp, sp, 16 2402; RV64IF-NEXT: ret 2403; 2404; RV64IZFINX-LABEL: frexp_float: 2405; RV64IZFINX: # %bb.0: 2406; RV64IZFINX-NEXT: addi sp, sp, -16 2407; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2408; RV64IZFINX-NEXT: mv a1, sp 2409; RV64IZFINX-NEXT: call frexpf 2410; RV64IZFINX-NEXT: ld a1, 0(sp) 2411; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2412; RV64IZFINX-NEXT: addi sp, sp, 16 2413; RV64IZFINX-NEXT: ret 2414; 2415; RV32I-LABEL: frexp_float: 2416; RV32I: # %bb.0: 2417; RV32I-NEXT: addi sp, sp, -16 2418; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2419; RV32I-NEXT: addi a1, sp, 8 2420; RV32I-NEXT: call frexpf 2421; RV32I-NEXT: lw a1, 8(sp) 2422; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2423; RV32I-NEXT: addi sp, sp, 16 2424; RV32I-NEXT: ret 2425; 2426; RV64I-LABEL: frexp_float: 2427; RV64I: # %bb.0: 2428; RV64I-NEXT: addi sp, sp, -16 2429; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2430; RV64I-NEXT: addi a1, sp, 4 2431; RV64I-NEXT: call frexpf 2432; RV64I-NEXT: lw a1, 4(sp) 2433; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2434; RV64I-NEXT: addi sp, sp, 16 2435; RV64I-NEXT: ret 2436 %a = call {float, i32} @llvm.frexp.f32.i32(float %x) 2437 ret {float, i32} %a 2438} 2439 2440define float @asin_f32(float %a) nounwind { 2441; RV32IF-LABEL: asin_f32: 2442; RV32IF: # %bb.0: 2443; RV32IF-NEXT: tail asinf 2444; 2445; RV32IZFINX-LABEL: asin_f32: 2446; RV32IZFINX: # %bb.0: 2447; RV32IZFINX-NEXT: tail asinf 2448; 2449; RV64IF-LABEL: asin_f32: 2450; RV64IF: # %bb.0: 2451; RV64IF-NEXT: tail asinf 2452; 2453; RV64IZFINX-LABEL: asin_f32: 2454; RV64IZFINX: # %bb.0: 2455; RV64IZFINX-NEXT: tail asinf 2456; 2457; RV32I-LABEL: asin_f32: 2458; RV32I: # %bb.0: 2459; RV32I-NEXT: addi sp, sp, -16 2460; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2461; RV32I-NEXT: call asinf 2462; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2463; RV32I-NEXT: addi sp, sp, 16 2464; RV32I-NEXT: ret 2465; 2466; RV64I-LABEL: asin_f32: 2467; RV64I: # %bb.0: 2468; RV64I-NEXT: addi sp, sp, -16 2469; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2470; RV64I-NEXT: call asinf 2471; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2472; RV64I-NEXT: addi sp, sp, 16 2473; RV64I-NEXT: ret 2474 %1 = call float @llvm.asin.f32(float %a) 2475 ret float %1 2476} 2477 2478define float @acos_f32(float %a) nounwind { 2479; RV32IF-LABEL: acos_f32: 2480; RV32IF: # %bb.0: 2481; RV32IF-NEXT: tail acosf 2482; 2483; RV32IZFINX-LABEL: acos_f32: 2484; RV32IZFINX: # %bb.0: 2485; RV32IZFINX-NEXT: tail acosf 2486; 2487; RV64IF-LABEL: acos_f32: 2488; RV64IF: # %bb.0: 2489; RV64IF-NEXT: tail acosf 2490; 2491; RV64IZFINX-LABEL: acos_f32: 2492; RV64IZFINX: # %bb.0: 2493; RV64IZFINX-NEXT: tail acosf 2494; 2495; RV32I-LABEL: acos_f32: 2496; RV32I: # %bb.0: 2497; RV32I-NEXT: addi sp, sp, -16 2498; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2499; RV32I-NEXT: call acosf 2500; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2501; RV32I-NEXT: addi sp, sp, 16 2502; RV32I-NEXT: ret 2503; 2504; RV64I-LABEL: acos_f32: 2505; RV64I: # %bb.0: 2506; RV64I-NEXT: addi sp, sp, -16 2507; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2508; RV64I-NEXT: call acosf 2509; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2510; RV64I-NEXT: addi sp, sp, 16 2511; RV64I-NEXT: ret 2512 %1 = call float @llvm.acos.f32(float %a) 2513 ret float %1 2514} 2515 2516define float @atan_f32(float %a) nounwind { 2517; RV32IF-LABEL: atan_f32: 2518; RV32IF: # %bb.0: 2519; RV32IF-NEXT: tail atanf 2520; 2521; RV32IZFINX-LABEL: atan_f32: 2522; RV32IZFINX: # %bb.0: 2523; RV32IZFINX-NEXT: tail atanf 2524; 2525; RV64IF-LABEL: atan_f32: 2526; RV64IF: # %bb.0: 2527; RV64IF-NEXT: tail atanf 2528; 2529; RV64IZFINX-LABEL: atan_f32: 2530; RV64IZFINX: # %bb.0: 2531; RV64IZFINX-NEXT: tail atanf 2532; 2533; RV32I-LABEL: atan_f32: 2534; RV32I: # %bb.0: 2535; RV32I-NEXT: addi sp, sp, -16 2536; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2537; RV32I-NEXT: call atanf 2538; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2539; RV32I-NEXT: addi sp, sp, 16 2540; RV32I-NEXT: ret 2541; 2542; RV64I-LABEL: atan_f32: 2543; RV64I: # %bb.0: 2544; RV64I-NEXT: addi sp, sp, -16 2545; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2546; RV64I-NEXT: call atanf 2547; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2548; RV64I-NEXT: addi sp, sp, 16 2549; RV64I-NEXT: ret 2550 %1 = call float @llvm.atan.f32(float %a) 2551 ret float %1 2552} 2553 2554define float @atan2_f32(float %a, float %b) nounwind { 2555; RV32IF-LABEL: atan2_f32: 2556; RV32IF: # %bb.0: 2557; RV32IF-NEXT: tail atan2f 2558; 2559; RV32IZFINX-LABEL: atan2_f32: 2560; RV32IZFINX: # %bb.0: 2561; RV32IZFINX-NEXT: tail atan2f 2562; 2563; RV64IF-LABEL: atan2_f32: 2564; RV64IF: # %bb.0: 2565; RV64IF-NEXT: tail atan2f 2566; 2567; RV64IZFINX-LABEL: atan2_f32: 2568; RV64IZFINX: # %bb.0: 2569; RV64IZFINX-NEXT: tail atan2f 2570; 2571; RV32I-LABEL: atan2_f32: 2572; RV32I: # %bb.0: 2573; RV32I-NEXT: addi sp, sp, -16 2574; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2575; RV32I-NEXT: call atan2f 2576; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2577; RV32I-NEXT: addi sp, sp, 16 2578; RV32I-NEXT: ret 2579; 2580; RV64I-LABEL: atan2_f32: 2581; RV64I: # %bb.0: 2582; RV64I-NEXT: addi sp, sp, -16 2583; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2584; RV64I-NEXT: call atan2f 2585; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2586; RV64I-NEXT: addi sp, sp, 16 2587; RV64I-NEXT: ret 2588 %1 = call float @llvm.atan2.f32(float %a, float %b) 2589 ret float %1 2590} 2591 2592define float @sinh_f32(float %a) nounwind { 2593; RV32IF-LABEL: sinh_f32: 2594; RV32IF: # %bb.0: 2595; RV32IF-NEXT: tail sinhf 2596; 2597; RV32IZFINX-LABEL: sinh_f32: 2598; RV32IZFINX: # %bb.0: 2599; RV32IZFINX-NEXT: tail sinhf 2600; 2601; RV64IF-LABEL: sinh_f32: 2602; RV64IF: # %bb.0: 2603; RV64IF-NEXT: tail sinhf 2604; 2605; RV64IZFINX-LABEL: sinh_f32: 2606; RV64IZFINX: # %bb.0: 2607; RV64IZFINX-NEXT: tail sinhf 2608; 2609; RV32I-LABEL: sinh_f32: 2610; RV32I: # %bb.0: 2611; RV32I-NEXT: addi sp, sp, -16 2612; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2613; RV32I-NEXT: call sinhf 2614; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2615; RV32I-NEXT: addi sp, sp, 16 2616; RV32I-NEXT: ret 2617; 2618; RV64I-LABEL: sinh_f32: 2619; RV64I: # %bb.0: 2620; RV64I-NEXT: addi sp, sp, -16 2621; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2622; RV64I-NEXT: call sinhf 2623; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2624; RV64I-NEXT: addi sp, sp, 16 2625; RV64I-NEXT: ret 2626 %1 = call float @llvm.sinh.f32(float %a) 2627 ret float %1 2628} 2629 2630define float @cosh_f32(float %a) nounwind { 2631; RV32IF-LABEL: cosh_f32: 2632; RV32IF: # %bb.0: 2633; RV32IF-NEXT: tail coshf 2634; 2635; RV32IZFINX-LABEL: cosh_f32: 2636; RV32IZFINX: # %bb.0: 2637; RV32IZFINX-NEXT: tail coshf 2638; 2639; RV64IF-LABEL: cosh_f32: 2640; RV64IF: # %bb.0: 2641; RV64IF-NEXT: tail coshf 2642; 2643; RV64IZFINX-LABEL: cosh_f32: 2644; RV64IZFINX: # %bb.0: 2645; RV64IZFINX-NEXT: tail coshf 2646; 2647; RV32I-LABEL: cosh_f32: 2648; RV32I: # %bb.0: 2649; RV32I-NEXT: addi sp, sp, -16 2650; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2651; RV32I-NEXT: call coshf 2652; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2653; RV32I-NEXT: addi sp, sp, 16 2654; RV32I-NEXT: ret 2655; 2656; RV64I-LABEL: cosh_f32: 2657; RV64I: # %bb.0: 2658; RV64I-NEXT: addi sp, sp, -16 2659; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2660; RV64I-NEXT: call coshf 2661; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2662; RV64I-NEXT: addi sp, sp, 16 2663; RV64I-NEXT: ret 2664 %1 = call float @llvm.cosh.f32(float %a) 2665 ret float %1 2666} 2667 2668define float @tanh_f32(float %a) nounwind { 2669; RV32IF-LABEL: tanh_f32: 2670; RV32IF: # %bb.0: 2671; RV32IF-NEXT: tail tanhf 2672; 2673; RV32IZFINX-LABEL: tanh_f32: 2674; RV32IZFINX: # %bb.0: 2675; RV32IZFINX-NEXT: tail tanhf 2676; 2677; RV64IF-LABEL: tanh_f32: 2678; RV64IF: # %bb.0: 2679; RV64IF-NEXT: tail tanhf 2680; 2681; RV64IZFINX-LABEL: tanh_f32: 2682; RV64IZFINX: # %bb.0: 2683; RV64IZFINX-NEXT: tail tanhf 2684; 2685; RV32I-LABEL: tanh_f32: 2686; RV32I: # %bb.0: 2687; RV32I-NEXT: addi sp, sp, -16 2688; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2689; RV32I-NEXT: call tanhf 2690; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2691; RV32I-NEXT: addi sp, sp, 16 2692; RV32I-NEXT: ret 2693; 2694; RV64I-LABEL: tanh_f32: 2695; RV64I: # %bb.0: 2696; RV64I-NEXT: addi sp, sp, -16 2697; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2698; RV64I-NEXT: call tanhf 2699; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2700; RV64I-NEXT: addi sp, sp, 16 2701; RV64I-NEXT: ret 2702 %1 = call float @llvm.tanh.f32(float %a) 2703 ret float %1 2704} 2705