1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32IF %s 4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64IF %s 6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ 7; RUN: | FileCheck -check-prefix=RV32IZFINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ 9; RUN: | FileCheck -check-prefix=RV64IZFINX %s 10; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 11; RUN: | FileCheck -check-prefix=RV32I %s 12; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 13; RUN: | FileCheck -check-prefix=RV64I %s 14 15define float @frem_f32(float %a, float %b) nounwind { 16; RV32IF-LABEL: frem_f32: 17; RV32IF: # %bb.0: 18; RV32IF-NEXT: tail fmodf 19; 20; RV64IF-LABEL: frem_f32: 21; RV64IF: # %bb.0: 22; RV64IF-NEXT: tail fmodf 23; 24; RV32IZFINX-LABEL: frem_f32: 25; RV32IZFINX: # %bb.0: 26; RV32IZFINX-NEXT: tail fmodf 27; 28; RV64IZFINX-LABEL: frem_f32: 29; RV64IZFINX: # %bb.0: 30; RV64IZFINX-NEXT: tail fmodf 31; 32; RV32I-LABEL: frem_f32: 33; RV32I: # %bb.0: 34; RV32I-NEXT: addi sp, sp, -16 35; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 36; RV32I-NEXT: call fmodf 37; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 38; RV32I-NEXT: addi sp, sp, 16 39; RV32I-NEXT: ret 40; 41; RV64I-LABEL: frem_f32: 42; RV64I: # %bb.0: 43; RV64I-NEXT: addi sp, sp, -16 44; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 45; RV64I-NEXT: call fmodf 46; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 47; RV64I-NEXT: addi sp, sp, 16 48; RV64I-NEXT: ret 49 %1 = frem float %a, %b 50 ret float %1 51} 52