1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ 3; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s 4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ 5; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s 6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ 7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ 9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s 10; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 11; RUN: | FileCheck -check-prefix=RV32I %s 12; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 13; RUN: | FileCheck -check-prefix=RV64I %s 14 15define i32 @fcvt_w_s(float %a) nounwind { 16; CHECKIF-LABEL: fcvt_w_s: 17; CHECKIF: # %bb.0: 18; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz 19; CHECKIF-NEXT: ret 20; 21; CHECKIZFINX-LABEL: fcvt_w_s: 22; CHECKIZFINX: # %bb.0: 23; CHECKIZFINX-NEXT: fcvt.w.s a0, a0, rtz 24; CHECKIZFINX-NEXT: ret 25; 26; RV32I-LABEL: fcvt_w_s: 27; RV32I: # %bb.0: 28; RV32I-NEXT: addi sp, sp, -16 29; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 30; RV32I-NEXT: call __fixsfsi 31; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 32; RV32I-NEXT: addi sp, sp, 16 33; RV32I-NEXT: ret 34; 35; RV64I-LABEL: fcvt_w_s: 36; RV64I: # %bb.0: 37; RV64I-NEXT: addi sp, sp, -16 38; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 39; RV64I-NEXT: call __fixsfsi 40; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 41; RV64I-NEXT: addi sp, sp, 16 42; RV64I-NEXT: ret 43 %1 = fptosi float %a to i32 44 ret i32 %1 45} 46 47define i32 @fcvt_w_s_sat(float %a) nounwind { 48; CHECKIF-LABEL: fcvt_w_s_sat: 49; CHECKIF: # %bb.0: # %start 50; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz 51; CHECKIF-NEXT: feq.s a1, fa0, fa0 52; CHECKIF-NEXT: seqz a1, a1 53; CHECKIF-NEXT: addi a1, a1, -1 54; CHECKIF-NEXT: and a0, a1, a0 55; CHECKIF-NEXT: ret 56; 57; CHECKIZFINX-LABEL: fcvt_w_s_sat: 58; CHECKIZFINX: # %bb.0: # %start 59; CHECKIZFINX-NEXT: fcvt.w.s a1, a0, rtz 60; CHECKIZFINX-NEXT: feq.s a0, a0, a0 61; CHECKIZFINX-NEXT: seqz a0, a0 62; CHECKIZFINX-NEXT: addi a0, a0, -1 63; CHECKIZFINX-NEXT: and a0, a0, a1 64; CHECKIZFINX-NEXT: ret 65; 66; RV32I-LABEL: fcvt_w_s_sat: 67; RV32I: # %bb.0: # %start 68; RV32I-NEXT: addi sp, sp, -32 69; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 70; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 71; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 72; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 73; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 74; RV32I-NEXT: mv s0, a0 75; RV32I-NEXT: lui a1, 847872 76; RV32I-NEXT: call __gesf2 77; RV32I-NEXT: mv s2, a0 78; RV32I-NEXT: mv a0, s0 79; RV32I-NEXT: call __fixsfsi 80; RV32I-NEXT: mv s1, a0 81; RV32I-NEXT: lui s3, 524288 82; RV32I-NEXT: bgez s2, .LBB1_2 83; RV32I-NEXT: # %bb.1: # %start 84; RV32I-NEXT: lui s1, 524288 85; RV32I-NEXT: .LBB1_2: # %start 86; RV32I-NEXT: lui a1, 323584 87; RV32I-NEXT: addi a1, a1, -1 88; RV32I-NEXT: mv a0, s0 89; RV32I-NEXT: call __gtsf2 90; RV32I-NEXT: blez a0, .LBB1_4 91; RV32I-NEXT: # %bb.3: # %start 92; RV32I-NEXT: addi s1, s3, -1 93; RV32I-NEXT: .LBB1_4: # %start 94; RV32I-NEXT: mv a0, s0 95; RV32I-NEXT: mv a1, s0 96; RV32I-NEXT: call __unordsf2 97; RV32I-NEXT: snez a0, a0 98; RV32I-NEXT: addi a0, a0, -1 99; RV32I-NEXT: and a0, a0, s1 100; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 101; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 102; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 103; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 104; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 105; RV32I-NEXT: addi sp, sp, 32 106; RV32I-NEXT: ret 107; 108; RV64I-LABEL: fcvt_w_s_sat: 109; RV64I: # %bb.0: # %start 110; RV64I-NEXT: addi sp, sp, -48 111; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill 112; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill 113; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill 114; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill 115; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill 116; RV64I-NEXT: mv s0, a0 117; RV64I-NEXT: lui a1, 847872 118; RV64I-NEXT: call __gesf2 119; RV64I-NEXT: mv s2, a0 120; RV64I-NEXT: mv a0, s0 121; RV64I-NEXT: call __fixsfdi 122; RV64I-NEXT: mv s1, a0 123; RV64I-NEXT: lui s3, 524288 124; RV64I-NEXT: bgez s2, .LBB1_2 125; RV64I-NEXT: # %bb.1: # %start 126; RV64I-NEXT: lui s1, 524288 127; RV64I-NEXT: .LBB1_2: # %start 128; RV64I-NEXT: lui a1, 323584 129; RV64I-NEXT: addiw a1, a1, -1 130; RV64I-NEXT: mv a0, s0 131; RV64I-NEXT: call __gtsf2 132; RV64I-NEXT: blez a0, .LBB1_4 133; RV64I-NEXT: # %bb.3: # %start 134; RV64I-NEXT: addiw s1, s3, -1 135; RV64I-NEXT: .LBB1_4: # %start 136; RV64I-NEXT: mv a0, s0 137; RV64I-NEXT: mv a1, s0 138; RV64I-NEXT: call __unordsf2 139; RV64I-NEXT: snez a0, a0 140; RV64I-NEXT: addi a0, a0, -1 141; RV64I-NEXT: and a0, a0, s1 142; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload 143; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload 144; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload 145; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload 146; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload 147; RV64I-NEXT: addi sp, sp, 48 148; RV64I-NEXT: ret 149start: 150 %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a) 151 ret i32 %0 152} 153declare i32 @llvm.fptosi.sat.i32.f32(float) 154 155define i32 @fcvt_wu_s(float %a) nounwind { 156; CHECKIF-LABEL: fcvt_wu_s: 157; CHECKIF: # %bb.0: 158; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz 159; CHECKIF-NEXT: ret 160; 161; CHECKIZFINX-LABEL: fcvt_wu_s: 162; CHECKIZFINX: # %bb.0: 163; CHECKIZFINX-NEXT: fcvt.wu.s a0, a0, rtz 164; CHECKIZFINX-NEXT: ret 165; 166; RV32I-LABEL: fcvt_wu_s: 167; RV32I: # %bb.0: 168; RV32I-NEXT: addi sp, sp, -16 169; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 170; RV32I-NEXT: call __fixunssfsi 171; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 172; RV32I-NEXT: addi sp, sp, 16 173; RV32I-NEXT: ret 174; 175; RV64I-LABEL: fcvt_wu_s: 176; RV64I: # %bb.0: 177; RV64I-NEXT: addi sp, sp, -16 178; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 179; RV64I-NEXT: call __fixunssfsi 180; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 181; RV64I-NEXT: addi sp, sp, 16 182; RV64I-NEXT: ret 183 %1 = fptoui float %a to i32 184 ret i32 %1 185} 186 187; Test where the fptoui has multiple uses, one of which causes a sext to be 188; inserted on RV64. 189define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind { 190; CHECKIF-LABEL: fcvt_wu_s_multiple_use: 191; CHECKIF: # %bb.0: 192; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz 193; CHECKIF-NEXT: seqz a1, a0 194; CHECKIF-NEXT: add a0, a0, a1 195; CHECKIF-NEXT: ret 196; 197; CHECKIZFINX-LABEL: fcvt_wu_s_multiple_use: 198; CHECKIZFINX: # %bb.0: 199; CHECKIZFINX-NEXT: fcvt.wu.s a0, a0, rtz 200; CHECKIZFINX-NEXT: seqz a1, a0 201; CHECKIZFINX-NEXT: add a0, a0, a1 202; CHECKIZFINX-NEXT: ret 203; 204; RV32I-LABEL: fcvt_wu_s_multiple_use: 205; RV32I: # %bb.0: 206; RV32I-NEXT: addi sp, sp, -16 207; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 208; RV32I-NEXT: call __fixunssfsi 209; RV32I-NEXT: seqz a1, a0 210; RV32I-NEXT: add a0, a0, a1 211; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 212; RV32I-NEXT: addi sp, sp, 16 213; RV32I-NEXT: ret 214; 215; RV64I-LABEL: fcvt_wu_s_multiple_use: 216; RV64I: # %bb.0: 217; RV64I-NEXT: addi sp, sp, -16 218; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 219; RV64I-NEXT: call __fixunssfsi 220; RV64I-NEXT: seqz a1, a0 221; RV64I-NEXT: add a0, a0, a1 222; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 223; RV64I-NEXT: addi sp, sp, 16 224; RV64I-NEXT: ret 225 %a = fptoui float %x to i32 226 %b = icmp eq i32 %a, 0 227 %c = select i1 %b, i32 1, i32 %a 228 ret i32 %c 229} 230 231define i32 @fcvt_wu_s_sat(float %a) nounwind { 232; RV32IF-LABEL: fcvt_wu_s_sat: 233; RV32IF: # %bb.0: # %start 234; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz 235; RV32IF-NEXT: feq.s a1, fa0, fa0 236; RV32IF-NEXT: seqz a1, a1 237; RV32IF-NEXT: addi a1, a1, -1 238; RV32IF-NEXT: and a0, a1, a0 239; RV32IF-NEXT: ret 240; 241; RV64IF-LABEL: fcvt_wu_s_sat: 242; RV64IF: # %bb.0: # %start 243; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz 244; RV64IF-NEXT: feq.s a1, fa0, fa0 245; RV64IF-NEXT: seqz a1, a1 246; RV64IF-NEXT: addi a1, a1, -1 247; RV64IF-NEXT: and a0, a0, a1 248; RV64IF-NEXT: slli a0, a0, 32 249; RV64IF-NEXT: srli a0, a0, 32 250; RV64IF-NEXT: ret 251; 252; RV32IZFINX-LABEL: fcvt_wu_s_sat: 253; RV32IZFINX: # %bb.0: # %start 254; RV32IZFINX-NEXT: fcvt.wu.s a1, a0, rtz 255; RV32IZFINX-NEXT: feq.s a0, a0, a0 256; RV32IZFINX-NEXT: seqz a0, a0 257; RV32IZFINX-NEXT: addi a0, a0, -1 258; RV32IZFINX-NEXT: and a0, a0, a1 259; RV32IZFINX-NEXT: ret 260; 261; RV64IZFINX-LABEL: fcvt_wu_s_sat: 262; RV64IZFINX: # %bb.0: # %start 263; RV64IZFINX-NEXT: fcvt.wu.s a1, a0, rtz 264; RV64IZFINX-NEXT: feq.s a0, a0, a0 265; RV64IZFINX-NEXT: seqz a0, a0 266; RV64IZFINX-NEXT: addi a0, a0, -1 267; RV64IZFINX-NEXT: and a0, a1, a0 268; RV64IZFINX-NEXT: slli a0, a0, 32 269; RV64IZFINX-NEXT: srli a0, a0, 32 270; RV64IZFINX-NEXT: ret 271; 272; RV32I-LABEL: fcvt_wu_s_sat: 273; RV32I: # %bb.0: # %start 274; RV32I-NEXT: addi sp, sp, -16 275; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 276; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 277; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 278; RV32I-NEXT: mv s0, a0 279; RV32I-NEXT: li a1, 0 280; RV32I-NEXT: call __gesf2 281; RV32I-NEXT: slti a0, a0, 0 282; RV32I-NEXT: addi s1, a0, -1 283; RV32I-NEXT: mv a0, s0 284; RV32I-NEXT: call __fixunssfsi 285; RV32I-NEXT: and s1, s1, a0 286; RV32I-NEXT: lui a1, 325632 287; RV32I-NEXT: addi a1, a1, -1 288; RV32I-NEXT: mv a0, s0 289; RV32I-NEXT: call __gtsf2 290; RV32I-NEXT: sgtz a0, a0 291; RV32I-NEXT: neg a0, a0 292; RV32I-NEXT: or a0, a0, s1 293; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 294; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 295; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 296; RV32I-NEXT: addi sp, sp, 16 297; RV32I-NEXT: ret 298; 299; RV64I-LABEL: fcvt_wu_s_sat: 300; RV64I: # %bb.0: # %start 301; RV64I-NEXT: addi sp, sp, -32 302; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 303; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 304; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 305; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 306; RV64I-NEXT: mv s2, a0 307; RV64I-NEXT: li a1, 0 308; RV64I-NEXT: call __gesf2 309; RV64I-NEXT: mv s0, a0 310; RV64I-NEXT: mv a0, s2 311; RV64I-NEXT: call __fixunssfdi 312; RV64I-NEXT: mv s1, a0 313; RV64I-NEXT: lui a1, 325632 314; RV64I-NEXT: addiw a1, a1, -1 315; RV64I-NEXT: mv a0, s2 316; RV64I-NEXT: call __gtsf2 317; RV64I-NEXT: blez a0, .LBB4_2 318; RV64I-NEXT: # %bb.1: # %start 319; RV64I-NEXT: li a0, -1 320; RV64I-NEXT: srli a0, a0, 32 321; RV64I-NEXT: j .LBB4_3 322; RV64I-NEXT: .LBB4_2: 323; RV64I-NEXT: slti a0, s0, 0 324; RV64I-NEXT: addi a0, a0, -1 325; RV64I-NEXT: and a0, a0, s1 326; RV64I-NEXT: .LBB4_3: # %start 327; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 328; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 329; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 330; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 331; RV64I-NEXT: addi sp, sp, 32 332; RV64I-NEXT: ret 333start: 334 %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a) 335 ret i32 %0 336} 337declare i32 @llvm.fptoui.sat.i32.f32(float) 338 339define signext i32 @fmv_x_w(float %a, float %b) nounwind { 340; CHECKIF-LABEL: fmv_x_w: 341; CHECKIF: # %bb.0: 342; CHECKIF-NEXT: fadd.s fa5, fa0, fa1 343; CHECKIF-NEXT: fmv.x.w a0, fa5 344; CHECKIF-NEXT: ret 345; 346; RV32IZFINX-LABEL: fmv_x_w: 347; RV32IZFINX: # %bb.0: 348; RV32IZFINX-NEXT: fadd.s a0, a0, a1 349; RV32IZFINX-NEXT: ret 350; 351; RV64IZFINX-LABEL: fmv_x_w: 352; RV64IZFINX: # %bb.0: 353; RV64IZFINX-NEXT: fadd.s a0, a0, a1 354; RV64IZFINX-NEXT: sext.w a0, a0 355; RV64IZFINX-NEXT: ret 356; 357; RV32I-LABEL: fmv_x_w: 358; RV32I: # %bb.0: 359; RV32I-NEXT: addi sp, sp, -16 360; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 361; RV32I-NEXT: call __addsf3 362; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 363; RV32I-NEXT: addi sp, sp, 16 364; RV32I-NEXT: ret 365; 366; RV64I-LABEL: fmv_x_w: 367; RV64I: # %bb.0: 368; RV64I-NEXT: addi sp, sp, -16 369; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 370; RV64I-NEXT: call __addsf3 371; RV64I-NEXT: sext.w a0, a0 372; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 373; RV64I-NEXT: addi sp, sp, 16 374; RV64I-NEXT: ret 375; Ensure fmv.x.w is generated even for a soft float calling convention 376 %1 = fadd float %a, %b 377 %2 = bitcast float %1 to i32 378 ret i32 %2 379} 380 381define float @fcvt_s_w(i32 %a) nounwind { 382; CHECKIF-LABEL: fcvt_s_w: 383; CHECKIF: # %bb.0: 384; CHECKIF-NEXT: fcvt.s.w fa0, a0 385; CHECKIF-NEXT: ret 386; 387; CHECKIZFINX-LABEL: fcvt_s_w: 388; CHECKIZFINX: # %bb.0: 389; CHECKIZFINX-NEXT: fcvt.s.w a0, a0 390; CHECKIZFINX-NEXT: ret 391; 392; RV32I-LABEL: fcvt_s_w: 393; RV32I: # %bb.0: 394; RV32I-NEXT: addi sp, sp, -16 395; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 396; RV32I-NEXT: call __floatsisf 397; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 398; RV32I-NEXT: addi sp, sp, 16 399; RV32I-NEXT: ret 400; 401; RV64I-LABEL: fcvt_s_w: 402; RV64I: # %bb.0: 403; RV64I-NEXT: addi sp, sp, -16 404; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 405; RV64I-NEXT: sext.w a0, a0 406; RV64I-NEXT: call __floatsisf 407; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 408; RV64I-NEXT: addi sp, sp, 16 409; RV64I-NEXT: ret 410 %1 = sitofp i32 %a to float 411 ret float %1 412} 413 414define float @fcvt_s_w_load(ptr %p) nounwind { 415; CHECKIF-LABEL: fcvt_s_w_load: 416; CHECKIF: # %bb.0: 417; CHECKIF-NEXT: lw a0, 0(a0) 418; CHECKIF-NEXT: fcvt.s.w fa0, a0 419; CHECKIF-NEXT: ret 420; 421; CHECKIZFINX-LABEL: fcvt_s_w_load: 422; CHECKIZFINX: # %bb.0: 423; CHECKIZFINX-NEXT: lw a0, 0(a0) 424; CHECKIZFINX-NEXT: fcvt.s.w a0, a0 425; CHECKIZFINX-NEXT: ret 426; 427; RV32I-LABEL: fcvt_s_w_load: 428; RV32I: # %bb.0: 429; RV32I-NEXT: addi sp, sp, -16 430; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 431; RV32I-NEXT: lw a0, 0(a0) 432; RV32I-NEXT: call __floatsisf 433; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 434; RV32I-NEXT: addi sp, sp, 16 435; RV32I-NEXT: ret 436; 437; RV64I-LABEL: fcvt_s_w_load: 438; RV64I: # %bb.0: 439; RV64I-NEXT: addi sp, sp, -16 440; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 441; RV64I-NEXT: lw a0, 0(a0) 442; RV64I-NEXT: call __floatsisf 443; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 444; RV64I-NEXT: addi sp, sp, 16 445; RV64I-NEXT: ret 446 %a = load i32, ptr %p 447 %1 = sitofp i32 %a to float 448 ret float %1 449} 450 451define float @fcvt_s_wu(i32 %a) nounwind { 452; CHECKIF-LABEL: fcvt_s_wu: 453; CHECKIF: # %bb.0: 454; CHECKIF-NEXT: fcvt.s.wu fa0, a0 455; CHECKIF-NEXT: ret 456; 457; CHECKIZFINX-LABEL: fcvt_s_wu: 458; CHECKIZFINX: # %bb.0: 459; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0 460; CHECKIZFINX-NEXT: ret 461; 462; RV32I-LABEL: fcvt_s_wu: 463; RV32I: # %bb.0: 464; RV32I-NEXT: addi sp, sp, -16 465; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 466; RV32I-NEXT: call __floatunsisf 467; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 468; RV32I-NEXT: addi sp, sp, 16 469; RV32I-NEXT: ret 470; 471; RV64I-LABEL: fcvt_s_wu: 472; RV64I: # %bb.0: 473; RV64I-NEXT: addi sp, sp, -16 474; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 475; RV64I-NEXT: sext.w a0, a0 476; RV64I-NEXT: call __floatunsisf 477; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 478; RV64I-NEXT: addi sp, sp, 16 479; RV64I-NEXT: ret 480 %1 = uitofp i32 %a to float 481 ret float %1 482} 483 484define float @fcvt_s_wu_load(ptr %p) nounwind { 485; RV32IF-LABEL: fcvt_s_wu_load: 486; RV32IF: # %bb.0: 487; RV32IF-NEXT: lw a0, 0(a0) 488; RV32IF-NEXT: fcvt.s.wu fa0, a0 489; RV32IF-NEXT: ret 490; 491; RV64IF-LABEL: fcvt_s_wu_load: 492; RV64IF: # %bb.0: 493; RV64IF-NEXT: lwu a0, 0(a0) 494; RV64IF-NEXT: fcvt.s.wu fa0, a0 495; RV64IF-NEXT: ret 496; 497; RV32IZFINX-LABEL: fcvt_s_wu_load: 498; RV32IZFINX: # %bb.0: 499; RV32IZFINX-NEXT: lw a0, 0(a0) 500; RV32IZFINX-NEXT: fcvt.s.wu a0, a0 501; RV32IZFINX-NEXT: ret 502; 503; RV64IZFINX-LABEL: fcvt_s_wu_load: 504; RV64IZFINX: # %bb.0: 505; RV64IZFINX-NEXT: lwu a0, 0(a0) 506; RV64IZFINX-NEXT: fcvt.s.wu a0, a0 507; RV64IZFINX-NEXT: ret 508; 509; RV32I-LABEL: fcvt_s_wu_load: 510; RV32I: # %bb.0: 511; RV32I-NEXT: addi sp, sp, -16 512; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 513; RV32I-NEXT: lw a0, 0(a0) 514; RV32I-NEXT: call __floatunsisf 515; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 516; RV32I-NEXT: addi sp, sp, 16 517; RV32I-NEXT: ret 518; 519; RV64I-LABEL: fcvt_s_wu_load: 520; RV64I: # %bb.0: 521; RV64I-NEXT: addi sp, sp, -16 522; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 523; RV64I-NEXT: lw a0, 0(a0) 524; RV64I-NEXT: call __floatunsisf 525; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 526; RV64I-NEXT: addi sp, sp, 16 527; RV64I-NEXT: ret 528 %a = load i32, ptr %p 529 %1 = uitofp i32 %a to float 530 ret float %1 531} 532 533define float @fmv_w_x(i32 %a, i32 %b) nounwind { 534; CHECKIF-LABEL: fmv_w_x: 535; CHECKIF: # %bb.0: 536; CHECKIF-NEXT: fmv.w.x fa5, a0 537; CHECKIF-NEXT: fmv.w.x fa4, a1 538; CHECKIF-NEXT: fadd.s fa0, fa5, fa4 539; CHECKIF-NEXT: ret 540; 541; CHECKIZFINX-LABEL: fmv_w_x: 542; CHECKIZFINX: # %bb.0: 543; CHECKIZFINX-NEXT: fadd.s a0, a0, a1 544; CHECKIZFINX-NEXT: ret 545; 546; RV32I-LABEL: fmv_w_x: 547; RV32I: # %bb.0: 548; RV32I-NEXT: addi sp, sp, -16 549; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 550; RV32I-NEXT: call __addsf3 551; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 552; RV32I-NEXT: addi sp, sp, 16 553; RV32I-NEXT: ret 554; 555; RV64I-LABEL: fmv_w_x: 556; RV64I: # %bb.0: 557; RV64I-NEXT: addi sp, sp, -16 558; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 559; RV64I-NEXT: call __addsf3 560; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 561; RV64I-NEXT: addi sp, sp, 16 562; RV64I-NEXT: ret 563; Ensure fmv.w.x is generated even for a soft float calling convention 564 %1 = bitcast i32 %a to float 565 %2 = bitcast i32 %b to float 566 %3 = fadd float %1, %2 567 ret float %3 568} 569 570define i64 @fcvt_l_s(float %a) nounwind { 571; RV32IF-LABEL: fcvt_l_s: 572; RV32IF: # %bb.0: 573; RV32IF-NEXT: addi sp, sp, -16 574; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 575; RV32IF-NEXT: call __fixsfdi 576; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 577; RV32IF-NEXT: addi sp, sp, 16 578; RV32IF-NEXT: ret 579; 580; RV64IF-LABEL: fcvt_l_s: 581; RV64IF: # %bb.0: 582; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz 583; RV64IF-NEXT: ret 584; 585; RV32IZFINX-LABEL: fcvt_l_s: 586; RV32IZFINX: # %bb.0: 587; RV32IZFINX-NEXT: addi sp, sp, -16 588; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 589; RV32IZFINX-NEXT: call __fixsfdi 590; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 591; RV32IZFINX-NEXT: addi sp, sp, 16 592; RV32IZFINX-NEXT: ret 593; 594; RV64IZFINX-LABEL: fcvt_l_s: 595; RV64IZFINX: # %bb.0: 596; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz 597; RV64IZFINX-NEXT: ret 598; 599; RV32I-LABEL: fcvt_l_s: 600; RV32I: # %bb.0: 601; RV32I-NEXT: addi sp, sp, -16 602; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 603; RV32I-NEXT: call __fixsfdi 604; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 605; RV32I-NEXT: addi sp, sp, 16 606; RV32I-NEXT: ret 607; 608; RV64I-LABEL: fcvt_l_s: 609; RV64I: # %bb.0: 610; RV64I-NEXT: addi sp, sp, -16 611; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 612; RV64I-NEXT: call __fixsfdi 613; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 614; RV64I-NEXT: addi sp, sp, 16 615; RV64I-NEXT: ret 616 %1 = fptosi float %a to i64 617 ret i64 %1 618} 619 620define i64 @fcvt_l_s_sat(float %a) nounwind { 621; RV32IF-LABEL: fcvt_l_s_sat: 622; RV32IF: # %bb.0: # %start 623; RV32IF-NEXT: addi sp, sp, -16 624; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 625; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 626; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 627; RV32IF-NEXT: fmv.s fs0, fa0 628; RV32IF-NEXT: lui a0, 913408 629; RV32IF-NEXT: fmv.w.x fa5, a0 630; RV32IF-NEXT: fle.s s0, fa5, fa0 631; RV32IF-NEXT: call __fixsfdi 632; RV32IF-NEXT: lui a3, 524288 633; RV32IF-NEXT: lui a2, 524288 634; RV32IF-NEXT: beqz s0, .LBB12_2 635; RV32IF-NEXT: # %bb.1: # %start 636; RV32IF-NEXT: mv a2, a1 637; RV32IF-NEXT: .LBB12_2: # %start 638; RV32IF-NEXT: lui a1, %hi(.LCPI12_0) 639; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a1) 640; RV32IF-NEXT: flt.s a1, fa5, fs0 641; RV32IF-NEXT: beqz a1, .LBB12_4 642; RV32IF-NEXT: # %bb.3: 643; RV32IF-NEXT: addi a2, a3, -1 644; RV32IF-NEXT: .LBB12_4: # %start 645; RV32IF-NEXT: feq.s a3, fs0, fs0 646; RV32IF-NEXT: neg a4, s0 647; RV32IF-NEXT: neg a5, a1 648; RV32IF-NEXT: neg a3, a3 649; RV32IF-NEXT: and a0, a4, a0 650; RV32IF-NEXT: and a1, a3, a2 651; RV32IF-NEXT: or a0, a5, a0 652; RV32IF-NEXT: and a0, a3, a0 653; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 654; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 655; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 656; RV32IF-NEXT: addi sp, sp, 16 657; RV32IF-NEXT: ret 658; 659; RV64IF-LABEL: fcvt_l_s_sat: 660; RV64IF: # %bb.0: # %start 661; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz 662; RV64IF-NEXT: feq.s a1, fa0, fa0 663; RV64IF-NEXT: seqz a1, a1 664; RV64IF-NEXT: addi a1, a1, -1 665; RV64IF-NEXT: and a0, a1, a0 666; RV64IF-NEXT: ret 667; 668; RV32IZFINX-LABEL: fcvt_l_s_sat: 669; RV32IZFINX: # %bb.0: # %start 670; RV32IZFINX-NEXT: addi sp, sp, -16 671; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 672; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 673; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 674; RV32IZFINX-NEXT: mv s0, a0 675; RV32IZFINX-NEXT: lui a0, 913408 676; RV32IZFINX-NEXT: fle.s s1, a0, s0 677; RV32IZFINX-NEXT: mv a0, s0 678; RV32IZFINX-NEXT: call __fixsfdi 679; RV32IZFINX-NEXT: lui a3, 524288 680; RV32IZFINX-NEXT: lui a2, 524288 681; RV32IZFINX-NEXT: beqz s1, .LBB12_2 682; RV32IZFINX-NEXT: # %bb.1: # %start 683; RV32IZFINX-NEXT: mv a2, a1 684; RV32IZFINX-NEXT: .LBB12_2: # %start 685; RV32IZFINX-NEXT: lui a1, 389120 686; RV32IZFINX-NEXT: addi a1, a1, -1 687; RV32IZFINX-NEXT: flt.s a1, a1, s0 688; RV32IZFINX-NEXT: beqz a1, .LBB12_4 689; RV32IZFINX-NEXT: # %bb.3: 690; RV32IZFINX-NEXT: addi a2, a3, -1 691; RV32IZFINX-NEXT: .LBB12_4: # %start 692; RV32IZFINX-NEXT: feq.s a3, s0, s0 693; RV32IZFINX-NEXT: neg a4, s1 694; RV32IZFINX-NEXT: neg a5, a1 695; RV32IZFINX-NEXT: neg a3, a3 696; RV32IZFINX-NEXT: and a0, a4, a0 697; RV32IZFINX-NEXT: and a1, a3, a2 698; RV32IZFINX-NEXT: or a0, a5, a0 699; RV32IZFINX-NEXT: and a0, a3, a0 700; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 701; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 702; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 703; RV32IZFINX-NEXT: addi sp, sp, 16 704; RV32IZFINX-NEXT: ret 705; 706; RV64IZFINX-LABEL: fcvt_l_s_sat: 707; RV64IZFINX: # %bb.0: # %start 708; RV64IZFINX-NEXT: fcvt.l.s a1, a0, rtz 709; RV64IZFINX-NEXT: feq.s a0, a0, a0 710; RV64IZFINX-NEXT: seqz a0, a0 711; RV64IZFINX-NEXT: addi a0, a0, -1 712; RV64IZFINX-NEXT: and a0, a0, a1 713; RV64IZFINX-NEXT: ret 714; 715; RV32I-LABEL: fcvt_l_s_sat: 716; RV32I: # %bb.0: # %start 717; RV32I-NEXT: addi sp, sp, -32 718; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 719; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 720; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 721; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 722; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 723; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill 724; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill 725; RV32I-NEXT: mv s1, a0 726; RV32I-NEXT: lui a1, 913408 727; RV32I-NEXT: call __gesf2 728; RV32I-NEXT: mv s2, a0 729; RV32I-NEXT: mv a0, s1 730; RV32I-NEXT: call __fixsfdi 731; RV32I-NEXT: mv s0, a0 732; RV32I-NEXT: mv s3, a1 733; RV32I-NEXT: lui s5, 524288 734; RV32I-NEXT: bgez s2, .LBB12_2 735; RV32I-NEXT: # %bb.1: # %start 736; RV32I-NEXT: lui s3, 524288 737; RV32I-NEXT: .LBB12_2: # %start 738; RV32I-NEXT: lui a1, 389120 739; RV32I-NEXT: addi a1, a1, -1 740; RV32I-NEXT: mv a0, s1 741; RV32I-NEXT: call __gtsf2 742; RV32I-NEXT: mv s4, a0 743; RV32I-NEXT: blez a0, .LBB12_4 744; RV32I-NEXT: # %bb.3: # %start 745; RV32I-NEXT: addi s3, s5, -1 746; RV32I-NEXT: .LBB12_4: # %start 747; RV32I-NEXT: mv a0, s1 748; RV32I-NEXT: mv a1, s1 749; RV32I-NEXT: call __unordsf2 750; RV32I-NEXT: snez a0, a0 751; RV32I-NEXT: slti a1, s2, 0 752; RV32I-NEXT: sgtz a2, s4 753; RV32I-NEXT: addi a0, a0, -1 754; RV32I-NEXT: addi a3, a1, -1 755; RV32I-NEXT: and a1, a0, s3 756; RV32I-NEXT: and a3, a3, s0 757; RV32I-NEXT: neg a2, a2 758; RV32I-NEXT: or a2, a2, a3 759; RV32I-NEXT: and a0, a0, a2 760; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 761; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 762; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 763; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 764; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 765; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload 766; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload 767; RV32I-NEXT: addi sp, sp, 32 768; RV32I-NEXT: ret 769; 770; RV64I-LABEL: fcvt_l_s_sat: 771; RV64I: # %bb.0: # %start 772; RV64I-NEXT: addi sp, sp, -48 773; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill 774; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill 775; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill 776; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill 777; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill 778; RV64I-NEXT: mv s0, a0 779; RV64I-NEXT: lui a1, 913408 780; RV64I-NEXT: call __gesf2 781; RV64I-NEXT: mv s2, a0 782; RV64I-NEXT: mv a0, s0 783; RV64I-NEXT: call __fixsfdi 784; RV64I-NEXT: mv s1, a0 785; RV64I-NEXT: li s3, -1 786; RV64I-NEXT: bgez s2, .LBB12_2 787; RV64I-NEXT: # %bb.1: # %start 788; RV64I-NEXT: slli s1, s3, 63 789; RV64I-NEXT: .LBB12_2: # %start 790; RV64I-NEXT: lui a1, 389120 791; RV64I-NEXT: addiw a1, a1, -1 792; RV64I-NEXT: mv a0, s0 793; RV64I-NEXT: call __gtsf2 794; RV64I-NEXT: blez a0, .LBB12_4 795; RV64I-NEXT: # %bb.3: # %start 796; RV64I-NEXT: srli s1, s3, 1 797; RV64I-NEXT: .LBB12_4: # %start 798; RV64I-NEXT: mv a0, s0 799; RV64I-NEXT: mv a1, s0 800; RV64I-NEXT: call __unordsf2 801; RV64I-NEXT: snez a0, a0 802; RV64I-NEXT: addi a0, a0, -1 803; RV64I-NEXT: and a0, a0, s1 804; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload 805; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload 806; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload 807; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload 808; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload 809; RV64I-NEXT: addi sp, sp, 48 810; RV64I-NEXT: ret 811start: 812 %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a) 813 ret i64 %0 814} 815declare i64 @llvm.fptosi.sat.i64.f32(float) 816 817define i64 @fcvt_lu_s(float %a) nounwind { 818; RV32IF-LABEL: fcvt_lu_s: 819; RV32IF: # %bb.0: 820; RV32IF-NEXT: addi sp, sp, -16 821; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 822; RV32IF-NEXT: call __fixunssfdi 823; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 824; RV32IF-NEXT: addi sp, sp, 16 825; RV32IF-NEXT: ret 826; 827; RV64IF-LABEL: fcvt_lu_s: 828; RV64IF: # %bb.0: 829; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz 830; RV64IF-NEXT: ret 831; 832; RV32IZFINX-LABEL: fcvt_lu_s: 833; RV32IZFINX: # %bb.0: 834; RV32IZFINX-NEXT: addi sp, sp, -16 835; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 836; RV32IZFINX-NEXT: call __fixunssfdi 837; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 838; RV32IZFINX-NEXT: addi sp, sp, 16 839; RV32IZFINX-NEXT: ret 840; 841; RV64IZFINX-LABEL: fcvt_lu_s: 842; RV64IZFINX: # %bb.0: 843; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz 844; RV64IZFINX-NEXT: ret 845; 846; RV32I-LABEL: fcvt_lu_s: 847; RV32I: # %bb.0: 848; RV32I-NEXT: addi sp, sp, -16 849; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 850; RV32I-NEXT: call __fixunssfdi 851; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 852; RV32I-NEXT: addi sp, sp, 16 853; RV32I-NEXT: ret 854; 855; RV64I-LABEL: fcvt_lu_s: 856; RV64I: # %bb.0: 857; RV64I-NEXT: addi sp, sp, -16 858; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 859; RV64I-NEXT: call __fixunssfdi 860; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 861; RV64I-NEXT: addi sp, sp, 16 862; RV64I-NEXT: ret 863 %1 = fptoui float %a to i64 864 ret i64 %1 865} 866 867define i64 @fcvt_lu_s_sat(float %a) nounwind { 868; RV32IF-LABEL: fcvt_lu_s_sat: 869; RV32IF: # %bb.0: # %start 870; RV32IF-NEXT: addi sp, sp, -16 871; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 872; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 873; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill 874; RV32IF-NEXT: fmv.s fs0, fa0 875; RV32IF-NEXT: fmv.w.x fa5, zero 876; RV32IF-NEXT: fle.s a0, fa5, fa0 877; RV32IF-NEXT: neg s0, a0 878; RV32IF-NEXT: call __fixunssfdi 879; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) 880; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) 881; RV32IF-NEXT: and a0, s0, a0 882; RV32IF-NEXT: and a1, s0, a1 883; RV32IF-NEXT: flt.s a2, fa5, fs0 884; RV32IF-NEXT: neg a2, a2 885; RV32IF-NEXT: or a0, a2, a0 886; RV32IF-NEXT: or a1, a2, a1 887; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 888; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 889; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload 890; RV32IF-NEXT: addi sp, sp, 16 891; RV32IF-NEXT: ret 892; 893; RV64IF-LABEL: fcvt_lu_s_sat: 894; RV64IF: # %bb.0: # %start 895; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz 896; RV64IF-NEXT: feq.s a1, fa0, fa0 897; RV64IF-NEXT: seqz a1, a1 898; RV64IF-NEXT: addi a1, a1, -1 899; RV64IF-NEXT: and a0, a1, a0 900; RV64IF-NEXT: ret 901; 902; RV32IZFINX-LABEL: fcvt_lu_s_sat: 903; RV32IZFINX: # %bb.0: # %start 904; RV32IZFINX-NEXT: addi sp, sp, -16 905; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 906; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 907; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 908; RV32IZFINX-NEXT: mv s0, a0 909; RV32IZFINX-NEXT: fle.s a0, zero, a0 910; RV32IZFINX-NEXT: neg s1, a0 911; RV32IZFINX-NEXT: mv a0, s0 912; RV32IZFINX-NEXT: call __fixunssfdi 913; RV32IZFINX-NEXT: and a0, s1, a0 914; RV32IZFINX-NEXT: lui a2, 391168 915; RV32IZFINX-NEXT: and a1, s1, a1 916; RV32IZFINX-NEXT: addi a2, a2, -1 917; RV32IZFINX-NEXT: flt.s a2, a2, s0 918; RV32IZFINX-NEXT: neg a2, a2 919; RV32IZFINX-NEXT: or a0, a2, a0 920; RV32IZFINX-NEXT: or a1, a2, a1 921; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 922; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 923; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 924; RV32IZFINX-NEXT: addi sp, sp, 16 925; RV32IZFINX-NEXT: ret 926; 927; RV64IZFINX-LABEL: fcvt_lu_s_sat: 928; RV64IZFINX: # %bb.0: # %start 929; RV64IZFINX-NEXT: fcvt.lu.s a1, a0, rtz 930; RV64IZFINX-NEXT: feq.s a0, a0, a0 931; RV64IZFINX-NEXT: seqz a0, a0 932; RV64IZFINX-NEXT: addi a0, a0, -1 933; RV64IZFINX-NEXT: and a0, a0, a1 934; RV64IZFINX-NEXT: ret 935; 936; RV32I-LABEL: fcvt_lu_s_sat: 937; RV32I: # %bb.0: # %start 938; RV32I-NEXT: addi sp, sp, -32 939; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 940; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 941; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 942; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 943; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 944; RV32I-NEXT: mv s0, a0 945; RV32I-NEXT: li a1, 0 946; RV32I-NEXT: call __gesf2 947; RV32I-NEXT: slti a0, a0, 0 948; RV32I-NEXT: addi s2, a0, -1 949; RV32I-NEXT: mv a0, s0 950; RV32I-NEXT: call __fixunssfdi 951; RV32I-NEXT: mv s1, a1 952; RV32I-NEXT: and s3, s2, a0 953; RV32I-NEXT: lui a1, 391168 954; RV32I-NEXT: addi a1, a1, -1 955; RV32I-NEXT: mv a0, s0 956; RV32I-NEXT: call __gtsf2 957; RV32I-NEXT: sgtz a0, a0 958; RV32I-NEXT: and a1, s2, s1 959; RV32I-NEXT: neg a2, a0 960; RV32I-NEXT: or a0, a2, s3 961; RV32I-NEXT: or a1, a2, a1 962; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 963; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 964; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 965; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 966; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 967; RV32I-NEXT: addi sp, sp, 32 968; RV32I-NEXT: ret 969; 970; RV64I-LABEL: fcvt_lu_s_sat: 971; RV64I: # %bb.0: # %start 972; RV64I-NEXT: addi sp, sp, -32 973; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 974; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 975; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 976; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 977; RV64I-NEXT: mv s0, a0 978; RV64I-NEXT: lui a1, 391168 979; RV64I-NEXT: addiw a1, a1, -1 980; RV64I-NEXT: call __gtsf2 981; RV64I-NEXT: sgtz a0, a0 982; RV64I-NEXT: neg s1, a0 983; RV64I-NEXT: mv a0, s0 984; RV64I-NEXT: li a1, 0 985; RV64I-NEXT: call __gesf2 986; RV64I-NEXT: slti a0, a0, 0 987; RV64I-NEXT: addi s2, a0, -1 988; RV64I-NEXT: mv a0, s0 989; RV64I-NEXT: call __fixunssfdi 990; RV64I-NEXT: and a0, s2, a0 991; RV64I-NEXT: or a0, s1, a0 992; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 993; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 994; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 995; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 996; RV64I-NEXT: addi sp, sp, 32 997; RV64I-NEXT: ret 998start: 999 %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a) 1000 ret i64 %0 1001} 1002declare i64 @llvm.fptoui.sat.i64.f32(float) 1003 1004define float @fcvt_s_l(i64 %a) nounwind { 1005; RV32IF-LABEL: fcvt_s_l: 1006; RV32IF: # %bb.0: 1007; RV32IF-NEXT: addi sp, sp, -16 1008; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1009; RV32IF-NEXT: call __floatdisf 1010; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1011; RV32IF-NEXT: addi sp, sp, 16 1012; RV32IF-NEXT: ret 1013; 1014; RV64IF-LABEL: fcvt_s_l: 1015; RV64IF: # %bb.0: 1016; RV64IF-NEXT: fcvt.s.l fa0, a0 1017; RV64IF-NEXT: ret 1018; 1019; RV32IZFINX-LABEL: fcvt_s_l: 1020; RV32IZFINX: # %bb.0: 1021; RV32IZFINX-NEXT: addi sp, sp, -16 1022; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1023; RV32IZFINX-NEXT: call __floatdisf 1024; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1025; RV32IZFINX-NEXT: addi sp, sp, 16 1026; RV32IZFINX-NEXT: ret 1027; 1028; RV64IZFINX-LABEL: fcvt_s_l: 1029; RV64IZFINX: # %bb.0: 1030; RV64IZFINX-NEXT: fcvt.s.l a0, a0 1031; RV64IZFINX-NEXT: ret 1032; 1033; RV32I-LABEL: fcvt_s_l: 1034; RV32I: # %bb.0: 1035; RV32I-NEXT: addi sp, sp, -16 1036; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1037; RV32I-NEXT: call __floatdisf 1038; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1039; RV32I-NEXT: addi sp, sp, 16 1040; RV32I-NEXT: ret 1041; 1042; RV64I-LABEL: fcvt_s_l: 1043; RV64I: # %bb.0: 1044; RV64I-NEXT: addi sp, sp, -16 1045; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1046; RV64I-NEXT: call __floatdisf 1047; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1048; RV64I-NEXT: addi sp, sp, 16 1049; RV64I-NEXT: ret 1050 %1 = sitofp i64 %a to float 1051 ret float %1 1052} 1053 1054define float @fcvt_s_lu(i64 %a) nounwind { 1055; RV32IF-LABEL: fcvt_s_lu: 1056; RV32IF: # %bb.0: 1057; RV32IF-NEXT: addi sp, sp, -16 1058; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1059; RV32IF-NEXT: call __floatundisf 1060; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1061; RV32IF-NEXT: addi sp, sp, 16 1062; RV32IF-NEXT: ret 1063; 1064; RV64IF-LABEL: fcvt_s_lu: 1065; RV64IF: # %bb.0: 1066; RV64IF-NEXT: fcvt.s.lu fa0, a0 1067; RV64IF-NEXT: ret 1068; 1069; RV32IZFINX-LABEL: fcvt_s_lu: 1070; RV32IZFINX: # %bb.0: 1071; RV32IZFINX-NEXT: addi sp, sp, -16 1072; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1073; RV32IZFINX-NEXT: call __floatundisf 1074; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1075; RV32IZFINX-NEXT: addi sp, sp, 16 1076; RV32IZFINX-NEXT: ret 1077; 1078; RV64IZFINX-LABEL: fcvt_s_lu: 1079; RV64IZFINX: # %bb.0: 1080; RV64IZFINX-NEXT: fcvt.s.lu a0, a0 1081; RV64IZFINX-NEXT: ret 1082; 1083; RV32I-LABEL: fcvt_s_lu: 1084; RV32I: # %bb.0: 1085; RV32I-NEXT: addi sp, sp, -16 1086; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1087; RV32I-NEXT: call __floatundisf 1088; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1089; RV32I-NEXT: addi sp, sp, 16 1090; RV32I-NEXT: ret 1091; 1092; RV64I-LABEL: fcvt_s_lu: 1093; RV64I: # %bb.0: 1094; RV64I-NEXT: addi sp, sp, -16 1095; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1096; RV64I-NEXT: call __floatundisf 1097; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1098; RV64I-NEXT: addi sp, sp, 16 1099; RV64I-NEXT: ret 1100 %1 = uitofp i64 %a to float 1101 ret float %1 1102} 1103 1104define float @fcvt_s_w_i8(i8 signext %a) nounwind { 1105; CHECKIF-LABEL: fcvt_s_w_i8: 1106; CHECKIF: # %bb.0: 1107; CHECKIF-NEXT: fcvt.s.w fa0, a0 1108; CHECKIF-NEXT: ret 1109; 1110; CHECKIZFINX-LABEL: fcvt_s_w_i8: 1111; CHECKIZFINX: # %bb.0: 1112; CHECKIZFINX-NEXT: fcvt.s.w a0, a0 1113; CHECKIZFINX-NEXT: ret 1114; 1115; RV32I-LABEL: fcvt_s_w_i8: 1116; RV32I: # %bb.0: 1117; RV32I-NEXT: addi sp, sp, -16 1118; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1119; RV32I-NEXT: call __floatsisf 1120; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1121; RV32I-NEXT: addi sp, sp, 16 1122; RV32I-NEXT: ret 1123; 1124; RV64I-LABEL: fcvt_s_w_i8: 1125; RV64I: # %bb.0: 1126; RV64I-NEXT: addi sp, sp, -16 1127; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1128; RV64I-NEXT: call __floatsisf 1129; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1130; RV64I-NEXT: addi sp, sp, 16 1131; RV64I-NEXT: ret 1132 %1 = sitofp i8 %a to float 1133 ret float %1 1134} 1135 1136define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind { 1137; CHECKIF-LABEL: fcvt_s_wu_i8: 1138; CHECKIF: # %bb.0: 1139; CHECKIF-NEXT: fcvt.s.wu fa0, a0 1140; CHECKIF-NEXT: ret 1141; 1142; CHECKIZFINX-LABEL: fcvt_s_wu_i8: 1143; CHECKIZFINX: # %bb.0: 1144; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0 1145; CHECKIZFINX-NEXT: ret 1146; 1147; RV32I-LABEL: fcvt_s_wu_i8: 1148; RV32I: # %bb.0: 1149; RV32I-NEXT: addi sp, sp, -16 1150; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1151; RV32I-NEXT: call __floatunsisf 1152; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1153; RV32I-NEXT: addi sp, sp, 16 1154; RV32I-NEXT: ret 1155; 1156; RV64I-LABEL: fcvt_s_wu_i8: 1157; RV64I: # %bb.0: 1158; RV64I-NEXT: addi sp, sp, -16 1159; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1160; RV64I-NEXT: call __floatunsisf 1161; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1162; RV64I-NEXT: addi sp, sp, 16 1163; RV64I-NEXT: ret 1164 %1 = uitofp i8 %a to float 1165 ret float %1 1166} 1167 1168define float @fcvt_s_w_i16(i16 signext %a) nounwind { 1169; CHECKIF-LABEL: fcvt_s_w_i16: 1170; CHECKIF: # %bb.0: 1171; CHECKIF-NEXT: fcvt.s.w fa0, a0 1172; CHECKIF-NEXT: ret 1173; 1174; CHECKIZFINX-LABEL: fcvt_s_w_i16: 1175; CHECKIZFINX: # %bb.0: 1176; CHECKIZFINX-NEXT: fcvt.s.w a0, a0 1177; CHECKIZFINX-NEXT: ret 1178; 1179; RV32I-LABEL: fcvt_s_w_i16: 1180; RV32I: # %bb.0: 1181; RV32I-NEXT: addi sp, sp, -16 1182; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1183; RV32I-NEXT: call __floatsisf 1184; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1185; RV32I-NEXT: addi sp, sp, 16 1186; RV32I-NEXT: ret 1187; 1188; RV64I-LABEL: fcvt_s_w_i16: 1189; RV64I: # %bb.0: 1190; RV64I-NEXT: addi sp, sp, -16 1191; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1192; RV64I-NEXT: call __floatsisf 1193; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1194; RV64I-NEXT: addi sp, sp, 16 1195; RV64I-NEXT: ret 1196 %1 = sitofp i16 %a to float 1197 ret float %1 1198} 1199 1200define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind { 1201; CHECKIF-LABEL: fcvt_s_wu_i16: 1202; CHECKIF: # %bb.0: 1203; CHECKIF-NEXT: fcvt.s.wu fa0, a0 1204; CHECKIF-NEXT: ret 1205; 1206; CHECKIZFINX-LABEL: fcvt_s_wu_i16: 1207; CHECKIZFINX: # %bb.0: 1208; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0 1209; CHECKIZFINX-NEXT: ret 1210; 1211; RV32I-LABEL: fcvt_s_wu_i16: 1212; RV32I: # %bb.0: 1213; RV32I-NEXT: addi sp, sp, -16 1214; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1215; RV32I-NEXT: call __floatunsisf 1216; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1217; RV32I-NEXT: addi sp, sp, 16 1218; RV32I-NEXT: ret 1219; 1220; RV64I-LABEL: fcvt_s_wu_i16: 1221; RV64I: # %bb.0: 1222; RV64I-NEXT: addi sp, sp, -16 1223; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1224; RV64I-NEXT: call __floatunsisf 1225; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1226; RV64I-NEXT: addi sp, sp, 16 1227; RV64I-NEXT: ret 1228 %1 = uitofp i16 %a to float 1229 ret float %1 1230} 1231 1232; Make sure we select W version of addi on RV64. 1233define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind { 1234; RV32IF-LABEL: fcvt_s_w_demanded_bits: 1235; RV32IF: # %bb.0: 1236; RV32IF-NEXT: addi a0, a0, 1 1237; RV32IF-NEXT: fcvt.s.w fa5, a0 1238; RV32IF-NEXT: fsw fa5, 0(a1) 1239; RV32IF-NEXT: ret 1240; 1241; RV64IF-LABEL: fcvt_s_w_demanded_bits: 1242; RV64IF: # %bb.0: 1243; RV64IF-NEXT: addiw a0, a0, 1 1244; RV64IF-NEXT: fcvt.s.w fa5, a0 1245; RV64IF-NEXT: fsw fa5, 0(a1) 1246; RV64IF-NEXT: ret 1247; 1248; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits: 1249; RV32IZFINX: # %bb.0: 1250; RV32IZFINX-NEXT: addi a0, a0, 1 1251; RV32IZFINX-NEXT: fcvt.s.w a2, a0 1252; RV32IZFINX-NEXT: sw a2, 0(a1) 1253; RV32IZFINX-NEXT: ret 1254; 1255; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits: 1256; RV64IZFINX: # %bb.0: 1257; RV64IZFINX-NEXT: addiw a0, a0, 1 1258; RV64IZFINX-NEXT: fcvt.s.w a2, a0 1259; RV64IZFINX-NEXT: sw a2, 0(a1) 1260; RV64IZFINX-NEXT: ret 1261; 1262; RV32I-LABEL: fcvt_s_w_demanded_bits: 1263; RV32I: # %bb.0: 1264; RV32I-NEXT: addi sp, sp, -16 1265; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1266; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1267; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1268; RV32I-NEXT: mv s0, a1 1269; RV32I-NEXT: addi s1, a0, 1 1270; RV32I-NEXT: mv a0, s1 1271; RV32I-NEXT: call __floatsisf 1272; RV32I-NEXT: sw a0, 0(s0) 1273; RV32I-NEXT: mv a0, s1 1274; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1275; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1276; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1277; RV32I-NEXT: addi sp, sp, 16 1278; RV32I-NEXT: ret 1279; 1280; RV64I-LABEL: fcvt_s_w_demanded_bits: 1281; RV64I: # %bb.0: 1282; RV64I-NEXT: addi sp, sp, -32 1283; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 1284; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 1285; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 1286; RV64I-NEXT: mv s0, a1 1287; RV64I-NEXT: addiw s1, a0, 1 1288; RV64I-NEXT: mv a0, s1 1289; RV64I-NEXT: call __floatsisf 1290; RV64I-NEXT: sw a0, 0(s0) 1291; RV64I-NEXT: mv a0, s1 1292; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 1293; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 1294; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 1295; RV64I-NEXT: addi sp, sp, 32 1296; RV64I-NEXT: ret 1297 %3 = add i32 %0, 1 1298 %4 = sitofp i32 %3 to float 1299 store float %4, ptr %1, align 4 1300 ret i32 %3 1301} 1302 1303; Make sure we select W version of addi on RV64. 1304define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind { 1305; RV32IF-LABEL: fcvt_s_wu_demanded_bits: 1306; RV32IF: # %bb.0: 1307; RV32IF-NEXT: addi a0, a0, 1 1308; RV32IF-NEXT: fcvt.s.wu fa5, a0 1309; RV32IF-NEXT: fsw fa5, 0(a1) 1310; RV32IF-NEXT: ret 1311; 1312; RV64IF-LABEL: fcvt_s_wu_demanded_bits: 1313; RV64IF: # %bb.0: 1314; RV64IF-NEXT: addiw a0, a0, 1 1315; RV64IF-NEXT: fcvt.s.wu fa5, a0 1316; RV64IF-NEXT: fsw fa5, 0(a1) 1317; RV64IF-NEXT: ret 1318; 1319; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits: 1320; RV32IZFINX: # %bb.0: 1321; RV32IZFINX-NEXT: addi a0, a0, 1 1322; RV32IZFINX-NEXT: fcvt.s.wu a2, a0 1323; RV32IZFINX-NEXT: sw a2, 0(a1) 1324; RV32IZFINX-NEXT: ret 1325; 1326; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits: 1327; RV64IZFINX: # %bb.0: 1328; RV64IZFINX-NEXT: addiw a0, a0, 1 1329; RV64IZFINX-NEXT: fcvt.s.wu a2, a0 1330; RV64IZFINX-NEXT: sw a2, 0(a1) 1331; RV64IZFINX-NEXT: ret 1332; 1333; RV32I-LABEL: fcvt_s_wu_demanded_bits: 1334; RV32I: # %bb.0: 1335; RV32I-NEXT: addi sp, sp, -16 1336; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1337; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1338; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1339; RV32I-NEXT: mv s0, a1 1340; RV32I-NEXT: addi s1, a0, 1 1341; RV32I-NEXT: mv a0, s1 1342; RV32I-NEXT: call __floatunsisf 1343; RV32I-NEXT: sw a0, 0(s0) 1344; RV32I-NEXT: mv a0, s1 1345; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1346; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1347; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1348; RV32I-NEXT: addi sp, sp, 16 1349; RV32I-NEXT: ret 1350; 1351; RV64I-LABEL: fcvt_s_wu_demanded_bits: 1352; RV64I: # %bb.0: 1353; RV64I-NEXT: addi sp, sp, -32 1354; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 1355; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 1356; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 1357; RV64I-NEXT: mv s0, a1 1358; RV64I-NEXT: addiw s1, a0, 1 1359; RV64I-NEXT: mv a0, s1 1360; RV64I-NEXT: call __floatunsisf 1361; RV64I-NEXT: sw a0, 0(s0) 1362; RV64I-NEXT: mv a0, s1 1363; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 1364; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 1365; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 1366; RV64I-NEXT: addi sp, sp, 32 1367; RV64I-NEXT: ret 1368 %3 = add i32 %0, 1 1369 %4 = uitofp i32 %3 to float 1370 store float %4, ptr %1, align 4 1371 ret i32 %3 1372} 1373 1374define signext i16 @fcvt_w_s_i16(float %a) nounwind { 1375; RV32IF-LABEL: fcvt_w_s_i16: 1376; RV32IF: # %bb.0: 1377; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz 1378; RV32IF-NEXT: ret 1379; 1380; RV64IF-LABEL: fcvt_w_s_i16: 1381; RV64IF: # %bb.0: 1382; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz 1383; RV64IF-NEXT: ret 1384; 1385; RV32IZFINX-LABEL: fcvt_w_s_i16: 1386; RV32IZFINX: # %bb.0: 1387; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz 1388; RV32IZFINX-NEXT: ret 1389; 1390; RV64IZFINX-LABEL: fcvt_w_s_i16: 1391; RV64IZFINX: # %bb.0: 1392; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz 1393; RV64IZFINX-NEXT: ret 1394; 1395; RV32I-LABEL: fcvt_w_s_i16: 1396; RV32I: # %bb.0: 1397; RV32I-NEXT: addi sp, sp, -16 1398; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1399; RV32I-NEXT: call __fixsfsi 1400; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1401; RV32I-NEXT: addi sp, sp, 16 1402; RV32I-NEXT: ret 1403; 1404; RV64I-LABEL: fcvt_w_s_i16: 1405; RV64I: # %bb.0: 1406; RV64I-NEXT: addi sp, sp, -16 1407; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1408; RV64I-NEXT: call __fixsfdi 1409; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1410; RV64I-NEXT: addi sp, sp, 16 1411; RV64I-NEXT: ret 1412 %1 = fptosi float %a to i16 1413 ret i16 %1 1414} 1415 1416define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { 1417; RV32IF-LABEL: fcvt_w_s_sat_i16: 1418; RV32IF: # %bb.0: # %start 1419; RV32IF-NEXT: feq.s a0, fa0, fa0 1420; RV32IF-NEXT: lui a1, %hi(.LCPI24_0) 1421; RV32IF-NEXT: flw fa5, %lo(.LCPI24_0)(a1) 1422; RV32IF-NEXT: lui a1, 815104 1423; RV32IF-NEXT: fmv.w.x fa4, a1 1424; RV32IF-NEXT: fmax.s fa4, fa0, fa4 1425; RV32IF-NEXT: neg a0, a0 1426; RV32IF-NEXT: fmin.s fa5, fa4, fa5 1427; RV32IF-NEXT: fcvt.w.s a1, fa5, rtz 1428; RV32IF-NEXT: and a0, a0, a1 1429; RV32IF-NEXT: ret 1430; 1431; RV64IF-LABEL: fcvt_w_s_sat_i16: 1432; RV64IF: # %bb.0: # %start 1433; RV64IF-NEXT: feq.s a0, fa0, fa0 1434; RV64IF-NEXT: lui a1, %hi(.LCPI24_0) 1435; RV64IF-NEXT: flw fa5, %lo(.LCPI24_0)(a1) 1436; RV64IF-NEXT: lui a1, 815104 1437; RV64IF-NEXT: fmv.w.x fa4, a1 1438; RV64IF-NEXT: fmax.s fa4, fa0, fa4 1439; RV64IF-NEXT: neg a0, a0 1440; RV64IF-NEXT: fmin.s fa5, fa4, fa5 1441; RV64IF-NEXT: fcvt.l.s a1, fa5, rtz 1442; RV64IF-NEXT: and a0, a0, a1 1443; RV64IF-NEXT: ret 1444; 1445; RV32IZFINX-LABEL: fcvt_w_s_sat_i16: 1446; RV32IZFINX: # %bb.0: # %start 1447; RV32IZFINX-NEXT: feq.s a1, a0, a0 1448; RV32IZFINX-NEXT: lui a2, 815104 1449; RV32IZFINX-NEXT: fmax.s a0, a0, a2 1450; RV32IZFINX-NEXT: lui a2, 290816 1451; RV32IZFINX-NEXT: neg a1, a1 1452; RV32IZFINX-NEXT: addi a2, a2, -512 1453; RV32IZFINX-NEXT: fmin.s a0, a0, a2 1454; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz 1455; RV32IZFINX-NEXT: and a0, a1, a0 1456; RV32IZFINX-NEXT: ret 1457; 1458; RV64IZFINX-LABEL: fcvt_w_s_sat_i16: 1459; RV64IZFINX: # %bb.0: # %start 1460; RV64IZFINX-NEXT: feq.s a1, a0, a0 1461; RV64IZFINX-NEXT: lui a2, 815104 1462; RV64IZFINX-NEXT: fmax.s a0, a0, a2 1463; RV64IZFINX-NEXT: lui a2, 290816 1464; RV64IZFINX-NEXT: neg a1, a1 1465; RV64IZFINX-NEXT: addiw a2, a2, -512 1466; RV64IZFINX-NEXT: fmin.s a0, a0, a2 1467; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz 1468; RV64IZFINX-NEXT: and a0, a1, a0 1469; RV64IZFINX-NEXT: ret 1470; 1471; RV32I-LABEL: fcvt_w_s_sat_i16: 1472; RV32I: # %bb.0: # %start 1473; RV32I-NEXT: addi sp, sp, -16 1474; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1475; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1476; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1477; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill 1478; RV32I-NEXT: mv s0, a0 1479; RV32I-NEXT: lui a1, 815104 1480; RV32I-NEXT: call __gesf2 1481; RV32I-NEXT: mv s2, a0 1482; RV32I-NEXT: mv a0, s0 1483; RV32I-NEXT: call __fixsfsi 1484; RV32I-NEXT: mv s1, a0 1485; RV32I-NEXT: bgez s2, .LBB24_2 1486; RV32I-NEXT: # %bb.1: # %start 1487; RV32I-NEXT: lui s1, 1048568 1488; RV32I-NEXT: .LBB24_2: # %start 1489; RV32I-NEXT: lui a0, 290816 1490; RV32I-NEXT: addi a1, a0, -512 1491; RV32I-NEXT: mv a0, s0 1492; RV32I-NEXT: call __gtsf2 1493; RV32I-NEXT: blez a0, .LBB24_4 1494; RV32I-NEXT: # %bb.3: # %start 1495; RV32I-NEXT: lui s1, 8 1496; RV32I-NEXT: addi s1, s1, -1 1497; RV32I-NEXT: .LBB24_4: # %start 1498; RV32I-NEXT: mv a0, s0 1499; RV32I-NEXT: mv a1, s0 1500; RV32I-NEXT: call __unordsf2 1501; RV32I-NEXT: snez a0, a0 1502; RV32I-NEXT: addi a0, a0, -1 1503; RV32I-NEXT: and a0, a0, s1 1504; RV32I-NEXT: slli a0, a0, 16 1505; RV32I-NEXT: srai a0, a0, 16 1506; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1507; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1508; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1509; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload 1510; RV32I-NEXT: addi sp, sp, 16 1511; RV32I-NEXT: ret 1512; 1513; RV64I-LABEL: fcvt_w_s_sat_i16: 1514; RV64I: # %bb.0: # %start 1515; RV64I-NEXT: addi sp, sp, -32 1516; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 1517; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 1518; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 1519; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 1520; RV64I-NEXT: mv s0, a0 1521; RV64I-NEXT: lui a1, 815104 1522; RV64I-NEXT: call __gesf2 1523; RV64I-NEXT: mv s2, a0 1524; RV64I-NEXT: mv a0, s0 1525; RV64I-NEXT: call __fixsfdi 1526; RV64I-NEXT: mv s1, a0 1527; RV64I-NEXT: bgez s2, .LBB24_2 1528; RV64I-NEXT: # %bb.1: # %start 1529; RV64I-NEXT: lui s1, 1048568 1530; RV64I-NEXT: .LBB24_2: # %start 1531; RV64I-NEXT: lui a0, 290816 1532; RV64I-NEXT: addiw a1, a0, -512 1533; RV64I-NEXT: mv a0, s0 1534; RV64I-NEXT: call __gtsf2 1535; RV64I-NEXT: blez a0, .LBB24_4 1536; RV64I-NEXT: # %bb.3: # %start 1537; RV64I-NEXT: lui s1, 8 1538; RV64I-NEXT: addi s1, s1, -1 1539; RV64I-NEXT: .LBB24_4: # %start 1540; RV64I-NEXT: mv a0, s0 1541; RV64I-NEXT: mv a1, s0 1542; RV64I-NEXT: call __unordsf2 1543; RV64I-NEXT: snez a0, a0 1544; RV64I-NEXT: addi a0, a0, -1 1545; RV64I-NEXT: and a0, a0, s1 1546; RV64I-NEXT: slli a0, a0, 48 1547; RV64I-NEXT: srai a0, a0, 48 1548; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 1549; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 1550; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 1551; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 1552; RV64I-NEXT: addi sp, sp, 32 1553; RV64I-NEXT: ret 1554start: 1555 %0 = tail call i16 @llvm.fptosi.sat.i16.f32(float %a) 1556 ret i16 %0 1557} 1558declare i16 @llvm.fptosi.sat.i16.f32(float) 1559 1560define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind { 1561; RV32IF-LABEL: fcvt_wu_s_i16: 1562; RV32IF: # %bb.0: 1563; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz 1564; RV32IF-NEXT: ret 1565; 1566; RV64IF-LABEL: fcvt_wu_s_i16: 1567; RV64IF: # %bb.0: 1568; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz 1569; RV64IF-NEXT: ret 1570; 1571; RV32IZFINX-LABEL: fcvt_wu_s_i16: 1572; RV32IZFINX: # %bb.0: 1573; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz 1574; RV32IZFINX-NEXT: ret 1575; 1576; RV64IZFINX-LABEL: fcvt_wu_s_i16: 1577; RV64IZFINX: # %bb.0: 1578; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz 1579; RV64IZFINX-NEXT: ret 1580; 1581; RV32I-LABEL: fcvt_wu_s_i16: 1582; RV32I: # %bb.0: 1583; RV32I-NEXT: addi sp, sp, -16 1584; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1585; RV32I-NEXT: call __fixunssfsi 1586; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1587; RV32I-NEXT: addi sp, sp, 16 1588; RV32I-NEXT: ret 1589; 1590; RV64I-LABEL: fcvt_wu_s_i16: 1591; RV64I: # %bb.0: 1592; RV64I-NEXT: addi sp, sp, -16 1593; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1594; RV64I-NEXT: call __fixunssfdi 1595; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1596; RV64I-NEXT: addi sp, sp, 16 1597; RV64I-NEXT: ret 1598 %1 = fptoui float %a to i16 1599 ret i16 %1 1600} 1601 1602define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind { 1603; RV32IF-LABEL: fcvt_wu_s_sat_i16: 1604; RV32IF: # %bb.0: # %start 1605; RV32IF-NEXT: lui a0, %hi(.LCPI26_0) 1606; RV32IF-NEXT: flw fa5, %lo(.LCPI26_0)(a0) 1607; RV32IF-NEXT: fmv.w.x fa4, zero 1608; RV32IF-NEXT: fmax.s fa4, fa0, fa4 1609; RV32IF-NEXT: fmin.s fa5, fa4, fa5 1610; RV32IF-NEXT: fcvt.wu.s a0, fa5, rtz 1611; RV32IF-NEXT: ret 1612; 1613; RV64IF-LABEL: fcvt_wu_s_sat_i16: 1614; RV64IF: # %bb.0: # %start 1615; RV64IF-NEXT: lui a0, %hi(.LCPI26_0) 1616; RV64IF-NEXT: flw fa5, %lo(.LCPI26_0)(a0) 1617; RV64IF-NEXT: fmv.w.x fa4, zero 1618; RV64IF-NEXT: fmax.s fa4, fa0, fa4 1619; RV64IF-NEXT: fmin.s fa5, fa4, fa5 1620; RV64IF-NEXT: fcvt.lu.s a0, fa5, rtz 1621; RV64IF-NEXT: ret 1622; 1623; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16: 1624; RV32IZFINX: # %bb.0: # %start 1625; RV32IZFINX-NEXT: fmax.s a0, a0, zero 1626; RV32IZFINX-NEXT: lui a1, 292864 1627; RV32IZFINX-NEXT: addi a1, a1, -256 1628; RV32IZFINX-NEXT: fmin.s a0, a0, a1 1629; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz 1630; RV32IZFINX-NEXT: ret 1631; 1632; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16: 1633; RV64IZFINX: # %bb.0: # %start 1634; RV64IZFINX-NEXT: fmax.s a0, a0, zero 1635; RV64IZFINX-NEXT: lui a1, 292864 1636; RV64IZFINX-NEXT: addiw a1, a1, -256 1637; RV64IZFINX-NEXT: fmin.s a0, a0, a1 1638; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz 1639; RV64IZFINX-NEXT: ret 1640; 1641; RV32I-LABEL: fcvt_wu_s_sat_i16: 1642; RV32I: # %bb.0: # %start 1643; RV32I-NEXT: addi sp, sp, -16 1644; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1645; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1646; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1647; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill 1648; RV32I-NEXT: mv s2, a0 1649; RV32I-NEXT: li a1, 0 1650; RV32I-NEXT: call __gesf2 1651; RV32I-NEXT: mv s0, a0 1652; RV32I-NEXT: mv a0, s2 1653; RV32I-NEXT: call __fixunssfsi 1654; RV32I-NEXT: mv s1, a0 1655; RV32I-NEXT: lui a0, 292864 1656; RV32I-NEXT: addi a1, a0, -256 1657; RV32I-NEXT: mv a0, s2 1658; RV32I-NEXT: call __gtsf2 1659; RV32I-NEXT: lui a1, 16 1660; RV32I-NEXT: addi a1, a1, -1 1661; RV32I-NEXT: blez a0, .LBB26_2 1662; RV32I-NEXT: # %bb.1: # %start 1663; RV32I-NEXT: mv a0, a1 1664; RV32I-NEXT: j .LBB26_3 1665; RV32I-NEXT: .LBB26_2: 1666; RV32I-NEXT: slti a0, s0, 0 1667; RV32I-NEXT: addi a0, a0, -1 1668; RV32I-NEXT: and a0, a0, s1 1669; RV32I-NEXT: .LBB26_3: # %start 1670; RV32I-NEXT: and a0, a0, a1 1671; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1672; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1673; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1674; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload 1675; RV32I-NEXT: addi sp, sp, 16 1676; RV32I-NEXT: ret 1677; 1678; RV64I-LABEL: fcvt_wu_s_sat_i16: 1679; RV64I: # %bb.0: # %start 1680; RV64I-NEXT: addi sp, sp, -32 1681; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 1682; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 1683; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 1684; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 1685; RV64I-NEXT: mv s2, a0 1686; RV64I-NEXT: li a1, 0 1687; RV64I-NEXT: call __gesf2 1688; RV64I-NEXT: mv s0, a0 1689; RV64I-NEXT: mv a0, s2 1690; RV64I-NEXT: call __fixunssfdi 1691; RV64I-NEXT: mv s1, a0 1692; RV64I-NEXT: lui a0, 292864 1693; RV64I-NEXT: addiw a1, a0, -256 1694; RV64I-NEXT: mv a0, s2 1695; RV64I-NEXT: call __gtsf2 1696; RV64I-NEXT: lui a1, 16 1697; RV64I-NEXT: addiw a1, a1, -1 1698; RV64I-NEXT: blez a0, .LBB26_2 1699; RV64I-NEXT: # %bb.1: # %start 1700; RV64I-NEXT: mv a0, a1 1701; RV64I-NEXT: j .LBB26_3 1702; RV64I-NEXT: .LBB26_2: 1703; RV64I-NEXT: slti a0, s0, 0 1704; RV64I-NEXT: addi a0, a0, -1 1705; RV64I-NEXT: and a0, a0, s1 1706; RV64I-NEXT: .LBB26_3: # %start 1707; RV64I-NEXT: and a0, a0, a1 1708; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 1709; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 1710; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 1711; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 1712; RV64I-NEXT: addi sp, sp, 32 1713; RV64I-NEXT: ret 1714start: 1715 %0 = tail call i16 @llvm.fptoui.sat.i16.f32(float %a) 1716 ret i16 %0 1717} 1718declare i16 @llvm.fptoui.sat.i16.f32(float) 1719 1720define signext i8 @fcvt_w_s_i8(float %a) nounwind { 1721; RV32IF-LABEL: fcvt_w_s_i8: 1722; RV32IF: # %bb.0: 1723; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz 1724; RV32IF-NEXT: ret 1725; 1726; RV64IF-LABEL: fcvt_w_s_i8: 1727; RV64IF: # %bb.0: 1728; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz 1729; RV64IF-NEXT: ret 1730; 1731; RV32IZFINX-LABEL: fcvt_w_s_i8: 1732; RV32IZFINX: # %bb.0: 1733; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz 1734; RV32IZFINX-NEXT: ret 1735; 1736; RV64IZFINX-LABEL: fcvt_w_s_i8: 1737; RV64IZFINX: # %bb.0: 1738; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz 1739; RV64IZFINX-NEXT: ret 1740; 1741; RV32I-LABEL: fcvt_w_s_i8: 1742; RV32I: # %bb.0: 1743; RV32I-NEXT: addi sp, sp, -16 1744; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1745; RV32I-NEXT: call __fixsfsi 1746; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1747; RV32I-NEXT: addi sp, sp, 16 1748; RV32I-NEXT: ret 1749; 1750; RV64I-LABEL: fcvt_w_s_i8: 1751; RV64I: # %bb.0: 1752; RV64I-NEXT: addi sp, sp, -16 1753; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1754; RV64I-NEXT: call __fixsfdi 1755; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1756; RV64I-NEXT: addi sp, sp, 16 1757; RV64I-NEXT: ret 1758 %1 = fptosi float %a to i8 1759 ret i8 %1 1760} 1761 1762define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind { 1763; RV32IF-LABEL: fcvt_w_s_sat_i8: 1764; RV32IF: # %bb.0: # %start 1765; RV32IF-NEXT: feq.s a0, fa0, fa0 1766; RV32IF-NEXT: lui a1, 798720 1767; RV32IF-NEXT: fmv.w.x fa5, a1 1768; RV32IF-NEXT: lui a1, 274400 1769; RV32IF-NEXT: neg a0, a0 1770; RV32IF-NEXT: fmax.s fa5, fa0, fa5 1771; RV32IF-NEXT: fmv.w.x fa4, a1 1772; RV32IF-NEXT: fmin.s fa5, fa5, fa4 1773; RV32IF-NEXT: fcvt.w.s a1, fa5, rtz 1774; RV32IF-NEXT: and a0, a0, a1 1775; RV32IF-NEXT: ret 1776; 1777; RV64IF-LABEL: fcvt_w_s_sat_i8: 1778; RV64IF: # %bb.0: # %start 1779; RV64IF-NEXT: feq.s a0, fa0, fa0 1780; RV64IF-NEXT: lui a1, 798720 1781; RV64IF-NEXT: fmv.w.x fa5, a1 1782; RV64IF-NEXT: lui a1, 274400 1783; RV64IF-NEXT: neg a0, a0 1784; RV64IF-NEXT: fmax.s fa5, fa0, fa5 1785; RV64IF-NEXT: fmv.w.x fa4, a1 1786; RV64IF-NEXT: fmin.s fa5, fa5, fa4 1787; RV64IF-NEXT: fcvt.l.s a1, fa5, rtz 1788; RV64IF-NEXT: and a0, a0, a1 1789; RV64IF-NEXT: ret 1790; 1791; RV32IZFINX-LABEL: fcvt_w_s_sat_i8: 1792; RV32IZFINX: # %bb.0: # %start 1793; RV32IZFINX-NEXT: feq.s a1, a0, a0 1794; RV32IZFINX-NEXT: lui a2, 798720 1795; RV32IZFINX-NEXT: neg a1, a1 1796; RV32IZFINX-NEXT: fmax.s a0, a0, a2 1797; RV32IZFINX-NEXT: lui a2, 274400 1798; RV32IZFINX-NEXT: fmin.s a0, a0, a2 1799; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz 1800; RV32IZFINX-NEXT: and a0, a1, a0 1801; RV32IZFINX-NEXT: ret 1802; 1803; RV64IZFINX-LABEL: fcvt_w_s_sat_i8: 1804; RV64IZFINX: # %bb.0: # %start 1805; RV64IZFINX-NEXT: feq.s a1, a0, a0 1806; RV64IZFINX-NEXT: lui a2, 798720 1807; RV64IZFINX-NEXT: neg a1, a1 1808; RV64IZFINX-NEXT: fmax.s a0, a0, a2 1809; RV64IZFINX-NEXT: lui a2, 274400 1810; RV64IZFINX-NEXT: fmin.s a0, a0, a2 1811; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz 1812; RV64IZFINX-NEXT: and a0, a1, a0 1813; RV64IZFINX-NEXT: ret 1814; 1815; RV32I-LABEL: fcvt_w_s_sat_i8: 1816; RV32I: # %bb.0: # %start 1817; RV32I-NEXT: addi sp, sp, -16 1818; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1819; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1820; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1821; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill 1822; RV32I-NEXT: mv s0, a0 1823; RV32I-NEXT: lui a1, 798720 1824; RV32I-NEXT: call __gesf2 1825; RV32I-NEXT: mv s2, a0 1826; RV32I-NEXT: mv a0, s0 1827; RV32I-NEXT: call __fixsfsi 1828; RV32I-NEXT: mv s1, a0 1829; RV32I-NEXT: bgez s2, .LBB28_2 1830; RV32I-NEXT: # %bb.1: # %start 1831; RV32I-NEXT: li s1, -128 1832; RV32I-NEXT: .LBB28_2: # %start 1833; RV32I-NEXT: lui a1, 274400 1834; RV32I-NEXT: mv a0, s0 1835; RV32I-NEXT: call __gtsf2 1836; RV32I-NEXT: blez a0, .LBB28_4 1837; RV32I-NEXT: # %bb.3: # %start 1838; RV32I-NEXT: li s1, 127 1839; RV32I-NEXT: .LBB28_4: # %start 1840; RV32I-NEXT: mv a0, s0 1841; RV32I-NEXT: mv a1, s0 1842; RV32I-NEXT: call __unordsf2 1843; RV32I-NEXT: snez a0, a0 1844; RV32I-NEXT: addi a0, a0, -1 1845; RV32I-NEXT: and a0, a0, s1 1846; RV32I-NEXT: slli a0, a0, 24 1847; RV32I-NEXT: srai a0, a0, 24 1848; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1849; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1850; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 1851; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload 1852; RV32I-NEXT: addi sp, sp, 16 1853; RV32I-NEXT: ret 1854; 1855; RV64I-LABEL: fcvt_w_s_sat_i8: 1856; RV64I: # %bb.0: # %start 1857; RV64I-NEXT: addi sp, sp, -32 1858; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 1859; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 1860; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 1861; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 1862; RV64I-NEXT: mv s0, a0 1863; RV64I-NEXT: lui a1, 798720 1864; RV64I-NEXT: call __gesf2 1865; RV64I-NEXT: mv s2, a0 1866; RV64I-NEXT: mv a0, s0 1867; RV64I-NEXT: call __fixsfdi 1868; RV64I-NEXT: mv s1, a0 1869; RV64I-NEXT: bgez s2, .LBB28_2 1870; RV64I-NEXT: # %bb.1: # %start 1871; RV64I-NEXT: li s1, -128 1872; RV64I-NEXT: .LBB28_2: # %start 1873; RV64I-NEXT: lui a1, 274400 1874; RV64I-NEXT: mv a0, s0 1875; RV64I-NEXT: call __gtsf2 1876; RV64I-NEXT: blez a0, .LBB28_4 1877; RV64I-NEXT: # %bb.3: # %start 1878; RV64I-NEXT: li s1, 127 1879; RV64I-NEXT: .LBB28_4: # %start 1880; RV64I-NEXT: mv a0, s0 1881; RV64I-NEXT: mv a1, s0 1882; RV64I-NEXT: call __unordsf2 1883; RV64I-NEXT: snez a0, a0 1884; RV64I-NEXT: addi a0, a0, -1 1885; RV64I-NEXT: and a0, a0, s1 1886; RV64I-NEXT: slli a0, a0, 56 1887; RV64I-NEXT: srai a0, a0, 56 1888; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 1889; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 1890; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 1891; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 1892; RV64I-NEXT: addi sp, sp, 32 1893; RV64I-NEXT: ret 1894start: 1895 %0 = tail call i8 @llvm.fptosi.sat.i8.f32(float %a) 1896 ret i8 %0 1897} 1898declare i8 @llvm.fptosi.sat.i8.f32(float) 1899 1900define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind { 1901; RV32IF-LABEL: fcvt_wu_s_i8: 1902; RV32IF: # %bb.0: 1903; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz 1904; RV32IF-NEXT: ret 1905; 1906; RV64IF-LABEL: fcvt_wu_s_i8: 1907; RV64IF: # %bb.0: 1908; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz 1909; RV64IF-NEXT: ret 1910; 1911; RV32IZFINX-LABEL: fcvt_wu_s_i8: 1912; RV32IZFINX: # %bb.0: 1913; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz 1914; RV32IZFINX-NEXT: ret 1915; 1916; RV64IZFINX-LABEL: fcvt_wu_s_i8: 1917; RV64IZFINX: # %bb.0: 1918; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz 1919; RV64IZFINX-NEXT: ret 1920; 1921; RV32I-LABEL: fcvt_wu_s_i8: 1922; RV32I: # %bb.0: 1923; RV32I-NEXT: addi sp, sp, -16 1924; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1925; RV32I-NEXT: call __fixunssfsi 1926; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1927; RV32I-NEXT: addi sp, sp, 16 1928; RV32I-NEXT: ret 1929; 1930; RV64I-LABEL: fcvt_wu_s_i8: 1931; RV64I: # %bb.0: 1932; RV64I-NEXT: addi sp, sp, -16 1933; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1934; RV64I-NEXT: call __fixunssfdi 1935; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1936; RV64I-NEXT: addi sp, sp, 16 1937; RV64I-NEXT: ret 1938 %1 = fptoui float %a to i8 1939 ret i8 %1 1940} 1941 1942define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind { 1943; RV32IF-LABEL: fcvt_wu_s_sat_i8: 1944; RV32IF: # %bb.0: # %start 1945; RV32IF-NEXT: fmv.w.x fa5, zero 1946; RV32IF-NEXT: lui a0, 276464 1947; RV32IF-NEXT: fmax.s fa5, fa0, fa5 1948; RV32IF-NEXT: fmv.w.x fa4, a0 1949; RV32IF-NEXT: fmin.s fa5, fa5, fa4 1950; RV32IF-NEXT: fcvt.wu.s a0, fa5, rtz 1951; RV32IF-NEXT: ret 1952; 1953; RV64IF-LABEL: fcvt_wu_s_sat_i8: 1954; RV64IF: # %bb.0: # %start 1955; RV64IF-NEXT: fmv.w.x fa5, zero 1956; RV64IF-NEXT: lui a0, 276464 1957; RV64IF-NEXT: fmax.s fa5, fa0, fa5 1958; RV64IF-NEXT: fmv.w.x fa4, a0 1959; RV64IF-NEXT: fmin.s fa5, fa5, fa4 1960; RV64IF-NEXT: fcvt.lu.s a0, fa5, rtz 1961; RV64IF-NEXT: ret 1962; 1963; RV32IZFINX-LABEL: fcvt_wu_s_sat_i8: 1964; RV32IZFINX: # %bb.0: # %start 1965; RV32IZFINX-NEXT: fmax.s a0, a0, zero 1966; RV32IZFINX-NEXT: lui a1, 276464 1967; RV32IZFINX-NEXT: fmin.s a0, a0, a1 1968; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz 1969; RV32IZFINX-NEXT: ret 1970; 1971; RV64IZFINX-LABEL: fcvt_wu_s_sat_i8: 1972; RV64IZFINX: # %bb.0: # %start 1973; RV64IZFINX-NEXT: fmax.s a0, a0, zero 1974; RV64IZFINX-NEXT: lui a1, 276464 1975; RV64IZFINX-NEXT: fmin.s a0, a0, a1 1976; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz 1977; RV64IZFINX-NEXT: ret 1978; 1979; RV32I-LABEL: fcvt_wu_s_sat_i8: 1980; RV32I: # %bb.0: # %start 1981; RV32I-NEXT: addi sp, sp, -16 1982; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1983; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1984; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 1985; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill 1986; RV32I-NEXT: mv s2, a0 1987; RV32I-NEXT: li a1, 0 1988; RV32I-NEXT: call __gesf2 1989; RV32I-NEXT: mv s0, a0 1990; RV32I-NEXT: mv a0, s2 1991; RV32I-NEXT: call __fixunssfsi 1992; RV32I-NEXT: mv s1, a0 1993; RV32I-NEXT: lui a1, 276464 1994; RV32I-NEXT: mv a0, s2 1995; RV32I-NEXT: call __gtsf2 1996; RV32I-NEXT: blez a0, .LBB30_2 1997; RV32I-NEXT: # %bb.1: # %start 1998; RV32I-NEXT: li a0, 255 1999; RV32I-NEXT: j .LBB30_3 2000; RV32I-NEXT: .LBB30_2: 2001; RV32I-NEXT: slti a0, s0, 0 2002; RV32I-NEXT: addi a0, a0, -1 2003; RV32I-NEXT: and a0, a0, s1 2004; RV32I-NEXT: .LBB30_3: # %start 2005; RV32I-NEXT: andi a0, a0, 255 2006; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2007; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2008; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2009; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload 2010; RV32I-NEXT: addi sp, sp, 16 2011; RV32I-NEXT: ret 2012; 2013; RV64I-LABEL: fcvt_wu_s_sat_i8: 2014; RV64I: # %bb.0: # %start 2015; RV64I-NEXT: addi sp, sp, -32 2016; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 2017; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 2018; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 2019; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 2020; RV64I-NEXT: mv s2, a0 2021; RV64I-NEXT: li a1, 0 2022; RV64I-NEXT: call __gesf2 2023; RV64I-NEXT: mv s0, a0 2024; RV64I-NEXT: mv a0, s2 2025; RV64I-NEXT: call __fixunssfdi 2026; RV64I-NEXT: mv s1, a0 2027; RV64I-NEXT: lui a1, 276464 2028; RV64I-NEXT: mv a0, s2 2029; RV64I-NEXT: call __gtsf2 2030; RV64I-NEXT: blez a0, .LBB30_2 2031; RV64I-NEXT: # %bb.1: # %start 2032; RV64I-NEXT: li a0, 255 2033; RV64I-NEXT: j .LBB30_3 2034; RV64I-NEXT: .LBB30_2: 2035; RV64I-NEXT: slti a0, s0, 0 2036; RV64I-NEXT: addi a0, a0, -1 2037; RV64I-NEXT: and a0, a0, s1 2038; RV64I-NEXT: .LBB30_3: # %start 2039; RV64I-NEXT: andi a0, a0, 255 2040; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 2041; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 2042; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 2043; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 2044; RV64I-NEXT: addi sp, sp, 32 2045; RV64I-NEXT: ret 2046start: 2047 %0 = tail call i8 @llvm.fptoui.sat.i8.f32(float %a) 2048 ret i8 %0 2049} 2050declare i8 @llvm.fptoui.sat.i8.f32(float) 2051 2052define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { 2053; RV32IF-LABEL: fcvt_wu_s_sat_zext: 2054; RV32IF: # %bb.0: # %start 2055; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz 2056; RV32IF-NEXT: feq.s a1, fa0, fa0 2057; RV32IF-NEXT: seqz a1, a1 2058; RV32IF-NEXT: addi a1, a1, -1 2059; RV32IF-NEXT: and a0, a1, a0 2060; RV32IF-NEXT: ret 2061; 2062; RV64IF-LABEL: fcvt_wu_s_sat_zext: 2063; RV64IF: # %bb.0: # %start 2064; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz 2065; RV64IF-NEXT: feq.s a1, fa0, fa0 2066; RV64IF-NEXT: seqz a1, a1 2067; RV64IF-NEXT: addi a1, a1, -1 2068; RV64IF-NEXT: and a0, a0, a1 2069; RV64IF-NEXT: slli a0, a0, 32 2070; RV64IF-NEXT: srli a0, a0, 32 2071; RV64IF-NEXT: ret 2072; 2073; RV32IZFINX-LABEL: fcvt_wu_s_sat_zext: 2074; RV32IZFINX: # %bb.0: # %start 2075; RV32IZFINX-NEXT: fcvt.wu.s a1, a0, rtz 2076; RV32IZFINX-NEXT: feq.s a0, a0, a0 2077; RV32IZFINX-NEXT: seqz a0, a0 2078; RV32IZFINX-NEXT: addi a0, a0, -1 2079; RV32IZFINX-NEXT: and a0, a0, a1 2080; RV32IZFINX-NEXT: ret 2081; 2082; RV64IZFINX-LABEL: fcvt_wu_s_sat_zext: 2083; RV64IZFINX: # %bb.0: # %start 2084; RV64IZFINX-NEXT: fcvt.wu.s a1, a0, rtz 2085; RV64IZFINX-NEXT: feq.s a0, a0, a0 2086; RV64IZFINX-NEXT: seqz a0, a0 2087; RV64IZFINX-NEXT: addi a0, a0, -1 2088; RV64IZFINX-NEXT: and a0, a1, a0 2089; RV64IZFINX-NEXT: slli a0, a0, 32 2090; RV64IZFINX-NEXT: srli a0, a0, 32 2091; RV64IZFINX-NEXT: ret 2092; 2093; RV32I-LABEL: fcvt_wu_s_sat_zext: 2094; RV32I: # %bb.0: # %start 2095; RV32I-NEXT: addi sp, sp, -16 2096; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2097; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 2098; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 2099; RV32I-NEXT: mv s0, a0 2100; RV32I-NEXT: li a1, 0 2101; RV32I-NEXT: call __gesf2 2102; RV32I-NEXT: slti a0, a0, 0 2103; RV32I-NEXT: addi s1, a0, -1 2104; RV32I-NEXT: mv a0, s0 2105; RV32I-NEXT: call __fixunssfsi 2106; RV32I-NEXT: and s1, s1, a0 2107; RV32I-NEXT: lui a1, 325632 2108; RV32I-NEXT: addi a1, a1, -1 2109; RV32I-NEXT: mv a0, s0 2110; RV32I-NEXT: call __gtsf2 2111; RV32I-NEXT: sgtz a0, a0 2112; RV32I-NEXT: neg a0, a0 2113; RV32I-NEXT: or a0, a0, s1 2114; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2115; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 2116; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 2117; RV32I-NEXT: addi sp, sp, 16 2118; RV32I-NEXT: ret 2119; 2120; RV64I-LABEL: fcvt_wu_s_sat_zext: 2121; RV64I: # %bb.0: # %start 2122; RV64I-NEXT: addi sp, sp, -32 2123; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 2124; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 2125; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 2126; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 2127; RV64I-NEXT: mv s2, a0 2128; RV64I-NEXT: li a1, 0 2129; RV64I-NEXT: call __gesf2 2130; RV64I-NEXT: mv s0, a0 2131; RV64I-NEXT: mv a0, s2 2132; RV64I-NEXT: call __fixunssfdi 2133; RV64I-NEXT: mv s1, a0 2134; RV64I-NEXT: lui a1, 325632 2135; RV64I-NEXT: addiw a1, a1, -1 2136; RV64I-NEXT: mv a0, s2 2137; RV64I-NEXT: call __gtsf2 2138; RV64I-NEXT: blez a0, .LBB31_2 2139; RV64I-NEXT: # %bb.1: # %start 2140; RV64I-NEXT: li a0, -1 2141; RV64I-NEXT: srli a0, a0, 32 2142; RV64I-NEXT: j .LBB31_3 2143; RV64I-NEXT: .LBB31_2: 2144; RV64I-NEXT: slti a0, s0, 0 2145; RV64I-NEXT: addi a0, a0, -1 2146; RV64I-NEXT: and a0, a0, s1 2147; RV64I-NEXT: .LBB31_3: # %start 2148; RV64I-NEXT: slli a0, a0, 32 2149; RV64I-NEXT: srli a0, a0, 32 2150; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 2151; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 2152; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 2153; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 2154; RV64I-NEXT: addi sp, sp, 32 2155; RV64I-NEXT: ret 2156start: 2157 %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a) 2158 ret i32 %0 2159} 2160 2161define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind { 2162; CHECKIF-LABEL: fcvt_w_s_sat_sext: 2163; CHECKIF: # %bb.0: # %start 2164; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz 2165; CHECKIF-NEXT: feq.s a1, fa0, fa0 2166; CHECKIF-NEXT: seqz a1, a1 2167; CHECKIF-NEXT: addi a1, a1, -1 2168; CHECKIF-NEXT: and a0, a1, a0 2169; CHECKIF-NEXT: ret 2170; 2171; CHECKIZFINX-LABEL: fcvt_w_s_sat_sext: 2172; CHECKIZFINX: # %bb.0: # %start 2173; CHECKIZFINX-NEXT: fcvt.w.s a1, a0, rtz 2174; CHECKIZFINX-NEXT: feq.s a0, a0, a0 2175; CHECKIZFINX-NEXT: seqz a0, a0 2176; CHECKIZFINX-NEXT: addi a0, a0, -1 2177; CHECKIZFINX-NEXT: and a0, a0, a1 2178; CHECKIZFINX-NEXT: ret 2179; 2180; RV32I-LABEL: fcvt_w_s_sat_sext: 2181; RV32I: # %bb.0: # %start 2182; RV32I-NEXT: addi sp, sp, -32 2183; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 2184; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 2185; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 2186; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 2187; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 2188; RV32I-NEXT: mv s0, a0 2189; RV32I-NEXT: lui a1, 847872 2190; RV32I-NEXT: call __gesf2 2191; RV32I-NEXT: mv s2, a0 2192; RV32I-NEXT: mv a0, s0 2193; RV32I-NEXT: call __fixsfsi 2194; RV32I-NEXT: mv s1, a0 2195; RV32I-NEXT: lui s3, 524288 2196; RV32I-NEXT: bgez s2, .LBB32_2 2197; RV32I-NEXT: # %bb.1: # %start 2198; RV32I-NEXT: lui s1, 524288 2199; RV32I-NEXT: .LBB32_2: # %start 2200; RV32I-NEXT: lui a1, 323584 2201; RV32I-NEXT: addi a1, a1, -1 2202; RV32I-NEXT: mv a0, s0 2203; RV32I-NEXT: call __gtsf2 2204; RV32I-NEXT: blez a0, .LBB32_4 2205; RV32I-NEXT: # %bb.3: # %start 2206; RV32I-NEXT: addi s1, s3, -1 2207; RV32I-NEXT: .LBB32_4: # %start 2208; RV32I-NEXT: mv a0, s0 2209; RV32I-NEXT: mv a1, s0 2210; RV32I-NEXT: call __unordsf2 2211; RV32I-NEXT: snez a0, a0 2212; RV32I-NEXT: addi a0, a0, -1 2213; RV32I-NEXT: and a0, a0, s1 2214; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 2215; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 2216; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 2217; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 2218; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 2219; RV32I-NEXT: addi sp, sp, 32 2220; RV32I-NEXT: ret 2221; 2222; RV64I-LABEL: fcvt_w_s_sat_sext: 2223; RV64I: # %bb.0: # %start 2224; RV64I-NEXT: addi sp, sp, -48 2225; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill 2226; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill 2227; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill 2228; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill 2229; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill 2230; RV64I-NEXT: mv s0, a0 2231; RV64I-NEXT: lui a1, 847872 2232; RV64I-NEXT: call __gesf2 2233; RV64I-NEXT: mv s2, a0 2234; RV64I-NEXT: mv a0, s0 2235; RV64I-NEXT: call __fixsfdi 2236; RV64I-NEXT: mv s1, a0 2237; RV64I-NEXT: lui s3, 524288 2238; RV64I-NEXT: bgez s2, .LBB32_2 2239; RV64I-NEXT: # %bb.1: # %start 2240; RV64I-NEXT: lui s1, 524288 2241; RV64I-NEXT: .LBB32_2: # %start 2242; RV64I-NEXT: lui a1, 323584 2243; RV64I-NEXT: addiw a1, a1, -1 2244; RV64I-NEXT: mv a0, s0 2245; RV64I-NEXT: call __gtsf2 2246; RV64I-NEXT: blez a0, .LBB32_4 2247; RV64I-NEXT: # %bb.3: # %start 2248; RV64I-NEXT: addi s1, s3, -1 2249; RV64I-NEXT: .LBB32_4: # %start 2250; RV64I-NEXT: mv a0, s0 2251; RV64I-NEXT: mv a1, s0 2252; RV64I-NEXT: call __unordsf2 2253; RV64I-NEXT: snez a0, a0 2254; RV64I-NEXT: addi a0, a0, -1 2255; RV64I-NEXT: and a0, a0, s1 2256; RV64I-NEXT: sext.w a0, a0 2257; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload 2258; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload 2259; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload 2260; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload 2261; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload 2262; RV64I-NEXT: addi sp, sp, 48 2263; RV64I-NEXT: ret 2264start: 2265 %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a) 2266 ret i32 %0 2267} 2268