xref: /llvm-project/llvm/test/CodeGen/RISCV/fixed-csr.ll (revision 84efad0b471543003c0724c85f158f66fccfdc0f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 < %s | FileCheck %s
3
4define noundef signext i32 @foo() {
5; CHECK-LABEL: foo:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    li s8, 321
8; CHECK-NEXT:    li a0, 0
9; CHECK-NEXT:    ret
10  tail call void @llvm.write_register.i64(metadata !0, i64 321)
11  ret i32 0
12}
13
14declare void @llvm.write_register.i64(metadata, i64)
15
16define noundef signext i32 @bar() nounwind {
17; CHECK-LABEL: bar:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    addi sp, sp, -16
20; CHECK-NEXT:    sd s9, 8(sp) # 8-byte Folded Spill
21; CHECK-NEXT:    #APP
22; CHECK-NEXT:    #NO_APP
23; CHECK-NEXT:    li s8, 321
24; CHECK-NEXT:    li a0, 0
25; CHECK-NEXT:    ld s9, 8(sp) # 8-byte Folded Reload
26; CHECK-NEXT:    addi sp, sp, 16
27; CHECK-NEXT:    ret
28  tail call void asm sideeffect "", "~{x25}"() #3
29  tail call void @llvm.write_register.i64(metadata !0, i64 321)
30  ret i32 0
31}
32
33!llvm.named.register.x24 = !{!0}
34!0 = !{!"x24"}
35
36