xref: /llvm-project/llvm/test/CodeGen/RISCV/double-isnan.ll (revision 576d81baa5cf1801bae0fd05892be34acde33c6a)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
3; RUN:   < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
5; RUN:   < %s | FileCheck %s
6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -target-abi ilp32 -verify-machineinstrs \
7; RUN:   < %s | FileCheck --check-prefix=CHECKRV32ZDINX %s
8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -target-abi lp64 -verify-machineinstrs \
9; RUN:   < %s | FileCheck --check-prefix=CHECKRV64ZDINX %s
10
11define zeroext i1 @double_is_nan(double %a) nounwind {
12; CHECK-LABEL: double_is_nan:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    feq.d a0, fa0, fa0
15; CHECK-NEXT:    xori a0, a0, 1
16; CHECK-NEXT:    ret
17;
18; CHECKRV32ZDINX-LABEL: double_is_nan:
19; CHECKRV32ZDINX:       # %bb.0:
20; CHECKRV32ZDINX-NEXT:    feq.d a0, a0, a0
21; CHECKRV32ZDINX-NEXT:    xori a0, a0, 1
22; CHECKRV32ZDINX-NEXT:    ret
23;
24; CHECKRV64ZDINX-LABEL: double_is_nan:
25; CHECKRV64ZDINX:       # %bb.0:
26; CHECKRV64ZDINX-NEXT:    feq.d a0, a0, a0
27; CHECKRV64ZDINX-NEXT:    xori a0, a0, 1
28; CHECKRV64ZDINX-NEXT:    ret
29  %1 = fcmp uno double %a, 0.000000e+00
30  ret i1 %1
31}
32
33define zeroext i1 @double_not_nan(double %a) nounwind {
34; CHECK-LABEL: double_not_nan:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    feq.d a0, fa0, fa0
37; CHECK-NEXT:    ret
38;
39; CHECKRV32ZDINX-LABEL: double_not_nan:
40; CHECKRV32ZDINX:       # %bb.0:
41; CHECKRV32ZDINX-NEXT:    feq.d a0, a0, a0
42; CHECKRV32ZDINX-NEXT:    ret
43;
44; CHECKRV64ZDINX-LABEL: double_not_nan:
45; CHECKRV64ZDINX:       # %bb.0:
46; CHECKRV64ZDINX-NEXT:    feq.d a0, a0, a0
47; CHECKRV64ZDINX-NEXT:    ret
48  %1 = fcmp ord double %a, 0.000000e+00
49  ret i1 %1
50}
51