1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ 3; RUN: -verify-machineinstrs -target-abi=ilp32d \ 4; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s 5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ 6; RUN: -verify-machineinstrs -target-abi=lp64d \ 7; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s 8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \ 9; RUN: -verify-machineinstrs -target-abi=ilp32 \ 10; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s 11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \ 12; RUN: -verify-machineinstrs -target-abi=lp64 \ 13; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s 14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ 15; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s 16; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ 17; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s 18 19declare double @llvm.sqrt.f64(double) 20 21define double @sqrt_f64(double %a) nounwind { 22; CHECKIFD-LABEL: sqrt_f64: 23; CHECKIFD: # %bb.0: 24; CHECKIFD-NEXT: fsqrt.d fa0, fa0 25; CHECKIFD-NEXT: ret 26; 27; RV32IZFINXZDINX-LABEL: sqrt_f64: 28; RV32IZFINXZDINX: # %bb.0: 29; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0 30; RV32IZFINXZDINX-NEXT: ret 31; 32; RV64IZFINXZDINX-LABEL: sqrt_f64: 33; RV64IZFINXZDINX: # %bb.0: 34; RV64IZFINXZDINX-NEXT: fsqrt.d a0, a0 35; RV64IZFINXZDINX-NEXT: ret 36; 37; RV32I-LABEL: sqrt_f64: 38; RV32I: # %bb.0: 39; RV32I-NEXT: addi sp, sp, -16 40; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 41; RV32I-NEXT: call sqrt 42; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 43; RV32I-NEXT: addi sp, sp, 16 44; RV32I-NEXT: ret 45; 46; RV64I-LABEL: sqrt_f64: 47; RV64I: # %bb.0: 48; RV64I-NEXT: addi sp, sp, -16 49; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 50; RV64I-NEXT: call sqrt 51; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 52; RV64I-NEXT: addi sp, sp, 16 53; RV64I-NEXT: ret 54 %1 = call double @llvm.sqrt.f64(double %a) 55 ret double %1 56} 57 58declare double @llvm.powi.f64.i32(double, i32) 59 60define double @powi_f64(double %a, i32 %b) nounwind { 61; RV32IFD-LABEL: powi_f64: 62; RV32IFD: # %bb.0: 63; RV32IFD-NEXT: tail __powidf2 64; 65; RV64IFD-LABEL: powi_f64: 66; RV64IFD: # %bb.0: 67; RV64IFD-NEXT: addi sp, sp, -16 68; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 69; RV64IFD-NEXT: sext.w a0, a0 70; RV64IFD-NEXT: call __powidf2 71; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 72; RV64IFD-NEXT: addi sp, sp, 16 73; RV64IFD-NEXT: ret 74; 75; RV32IZFINXZDINX-LABEL: powi_f64: 76; RV32IZFINXZDINX: # %bb.0: 77; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 78; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 79; RV32IZFINXZDINX-NEXT: call __powidf2 80; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 81; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 82; RV32IZFINXZDINX-NEXT: ret 83; 84; RV64IZFINXZDINX-LABEL: powi_f64: 85; RV64IZFINXZDINX: # %bb.0: 86; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 87; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 88; RV64IZFINXZDINX-NEXT: sext.w a1, a1 89; RV64IZFINXZDINX-NEXT: call __powidf2 90; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 91; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 92; RV64IZFINXZDINX-NEXT: ret 93; 94; RV32I-LABEL: powi_f64: 95; RV32I: # %bb.0: 96; RV32I-NEXT: addi sp, sp, -16 97; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 98; RV32I-NEXT: call __powidf2 99; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 100; RV32I-NEXT: addi sp, sp, 16 101; RV32I-NEXT: ret 102; 103; RV64I-LABEL: powi_f64: 104; RV64I: # %bb.0: 105; RV64I-NEXT: addi sp, sp, -16 106; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 107; RV64I-NEXT: sext.w a1, a1 108; RV64I-NEXT: call __powidf2 109; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 110; RV64I-NEXT: addi sp, sp, 16 111; RV64I-NEXT: ret 112 %1 = call double @llvm.powi.f64.i32(double %a, i32 %b) 113 ret double %1 114} 115 116declare double @llvm.sin.f64(double) 117 118define double @sin_f64(double %a) nounwind { 119; CHECKIFD-LABEL: sin_f64: 120; CHECKIFD: # %bb.0: 121; CHECKIFD-NEXT: tail sin 122; 123; RV32IZFINXZDINX-LABEL: sin_f64: 124; RV32IZFINXZDINX: # %bb.0: 125; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 126; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 127; RV32IZFINXZDINX-NEXT: call sin 128; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 129; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 130; RV32IZFINXZDINX-NEXT: ret 131; 132; RV64IZFINXZDINX-LABEL: sin_f64: 133; RV64IZFINXZDINX: # %bb.0: 134; RV64IZFINXZDINX-NEXT: tail sin 135; 136; RV32I-LABEL: sin_f64: 137; RV32I: # %bb.0: 138; RV32I-NEXT: addi sp, sp, -16 139; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 140; RV32I-NEXT: call sin 141; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 142; RV32I-NEXT: addi sp, sp, 16 143; RV32I-NEXT: ret 144; 145; RV64I-LABEL: sin_f64: 146; RV64I: # %bb.0: 147; RV64I-NEXT: addi sp, sp, -16 148; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 149; RV64I-NEXT: call sin 150; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 151; RV64I-NEXT: addi sp, sp, 16 152; RV64I-NEXT: ret 153 %1 = call double @llvm.sin.f64(double %a) 154 ret double %1 155} 156 157declare double @llvm.cos.f64(double) 158 159define double @cos_f64(double %a) nounwind { 160; CHECKIFD-LABEL: cos_f64: 161; CHECKIFD: # %bb.0: 162; CHECKIFD-NEXT: tail cos 163; 164; RV32IZFINXZDINX-LABEL: cos_f64: 165; RV32IZFINXZDINX: # %bb.0: 166; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 167; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 168; RV32IZFINXZDINX-NEXT: call cos 169; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 170; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 171; RV32IZFINXZDINX-NEXT: ret 172; 173; RV64IZFINXZDINX-LABEL: cos_f64: 174; RV64IZFINXZDINX: # %bb.0: 175; RV64IZFINXZDINX-NEXT: tail cos 176; 177; RV32I-LABEL: cos_f64: 178; RV32I: # %bb.0: 179; RV32I-NEXT: addi sp, sp, -16 180; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 181; RV32I-NEXT: call cos 182; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 183; RV32I-NEXT: addi sp, sp, 16 184; RV32I-NEXT: ret 185; 186; RV64I-LABEL: cos_f64: 187; RV64I: # %bb.0: 188; RV64I-NEXT: addi sp, sp, -16 189; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 190; RV64I-NEXT: call cos 191; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 192; RV64I-NEXT: addi sp, sp, 16 193; RV64I-NEXT: ret 194 %1 = call double @llvm.cos.f64(double %a) 195 ret double %1 196} 197 198; The sin+cos combination results in an FSINCOS SelectionDAG node. 199define double @sincos_f64(double %a) nounwind { 200; RV32IFD-LABEL: sincos_f64: 201; RV32IFD: # %bb.0: 202; RV32IFD-NEXT: addi sp, sp, -32 203; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 204; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill 205; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill 206; RV32IFD-NEXT: fmv.d fs0, fa0 207; RV32IFD-NEXT: call sin 208; RV32IFD-NEXT: fmv.d fs1, fa0 209; RV32IFD-NEXT: fmv.d fa0, fs0 210; RV32IFD-NEXT: call cos 211; RV32IFD-NEXT: fadd.d fa0, fs1, fa0 212; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 213; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload 214; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload 215; RV32IFD-NEXT: addi sp, sp, 32 216; RV32IFD-NEXT: ret 217; 218; RV64IFD-LABEL: sincos_f64: 219; RV64IFD: # %bb.0: 220; RV64IFD-NEXT: addi sp, sp, -32 221; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 222; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill 223; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill 224; RV64IFD-NEXT: fmv.d fs0, fa0 225; RV64IFD-NEXT: call sin 226; RV64IFD-NEXT: fmv.d fs1, fa0 227; RV64IFD-NEXT: fmv.d fa0, fs0 228; RV64IFD-NEXT: call cos 229; RV64IFD-NEXT: fadd.d fa0, fs1, fa0 230; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 231; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload 232; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload 233; RV64IFD-NEXT: addi sp, sp, 32 234; RV64IFD-NEXT: ret 235; 236; RV32IZFINXZDINX-LABEL: sincos_f64: 237; RV32IZFINXZDINX: # %bb.0: 238; RV32IZFINXZDINX-NEXT: addi sp, sp, -32 239; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 240; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 241; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 242; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 243; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 244; RV32IZFINXZDINX-NEXT: mv s0, a1 245; RV32IZFINXZDINX-NEXT: mv s1, a0 246; RV32IZFINXZDINX-NEXT: call sin 247; RV32IZFINXZDINX-NEXT: mv s2, a0 248; RV32IZFINXZDINX-NEXT: mv s3, a1 249; RV32IZFINXZDINX-NEXT: mv a0, s1 250; RV32IZFINXZDINX-NEXT: mv a1, s0 251; RV32IZFINXZDINX-NEXT: call cos 252; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0 253; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 254; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 255; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 256; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 257; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 258; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 259; RV32IZFINXZDINX-NEXT: ret 260; 261; RV64IZFINXZDINX-LABEL: sincos_f64: 262; RV64IZFINXZDINX: # %bb.0: 263; RV64IZFINXZDINX-NEXT: addi sp, sp, -32 264; RV64IZFINXZDINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 265; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 266; RV64IZFINXZDINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 267; RV64IZFINXZDINX-NEXT: mv s0, a0 268; RV64IZFINXZDINX-NEXT: call sin 269; RV64IZFINXZDINX-NEXT: mv s1, a0 270; RV64IZFINXZDINX-NEXT: mv a0, s0 271; RV64IZFINXZDINX-NEXT: call cos 272; RV64IZFINXZDINX-NEXT: fadd.d a0, s1, a0 273; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 274; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 275; RV64IZFINXZDINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 276; RV64IZFINXZDINX-NEXT: addi sp, sp, 32 277; RV64IZFINXZDINX-NEXT: ret 278; 279; RV32I-LABEL: sincos_f64: 280; RV32I: # %bb.0: 281; RV32I-NEXT: addi sp, sp, -32 282; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 283; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 284; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 285; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 286; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 287; RV32I-NEXT: mv s0, a1 288; RV32I-NEXT: mv s1, a0 289; RV32I-NEXT: call sin 290; RV32I-NEXT: mv s2, a0 291; RV32I-NEXT: mv s3, a1 292; RV32I-NEXT: mv a0, s1 293; RV32I-NEXT: mv a1, s0 294; RV32I-NEXT: call cos 295; RV32I-NEXT: mv a2, a0 296; RV32I-NEXT: mv a3, a1 297; RV32I-NEXT: mv a0, s2 298; RV32I-NEXT: mv a1, s3 299; RV32I-NEXT: call __adddf3 300; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 301; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 302; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 303; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 304; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 305; RV32I-NEXT: addi sp, sp, 32 306; RV32I-NEXT: ret 307; 308; RV64I-LABEL: sincos_f64: 309; RV64I: # %bb.0: 310; RV64I-NEXT: addi sp, sp, -32 311; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 312; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 313; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 314; RV64I-NEXT: mv s0, a0 315; RV64I-NEXT: call sin 316; RV64I-NEXT: mv s1, a0 317; RV64I-NEXT: mv a0, s0 318; RV64I-NEXT: call cos 319; RV64I-NEXT: mv a1, a0 320; RV64I-NEXT: mv a0, s1 321; RV64I-NEXT: call __adddf3 322; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 323; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 324; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 325; RV64I-NEXT: addi sp, sp, 32 326; RV64I-NEXT: ret 327 %1 = call double @llvm.sin.f64(double %a) 328 %2 = call double @llvm.cos.f64(double %a) 329 %3 = fadd double %1, %2 330 ret double %3 331} 332 333declare double @llvm.pow.f64(double, double) 334 335define double @pow_f64(double %a, double %b) nounwind { 336; CHECKIFD-LABEL: pow_f64: 337; CHECKIFD: # %bb.0: 338; CHECKIFD-NEXT: tail pow 339; 340; RV32IZFINXZDINX-LABEL: pow_f64: 341; RV32IZFINXZDINX: # %bb.0: 342; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 343; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 344; RV32IZFINXZDINX-NEXT: call pow 345; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 346; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 347; RV32IZFINXZDINX-NEXT: ret 348; 349; RV64IZFINXZDINX-LABEL: pow_f64: 350; RV64IZFINXZDINX: # %bb.0: 351; RV64IZFINXZDINX-NEXT: tail pow 352; 353; RV32I-LABEL: pow_f64: 354; RV32I: # %bb.0: 355; RV32I-NEXT: addi sp, sp, -16 356; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 357; RV32I-NEXT: call pow 358; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 359; RV32I-NEXT: addi sp, sp, 16 360; RV32I-NEXT: ret 361; 362; RV64I-LABEL: pow_f64: 363; RV64I: # %bb.0: 364; RV64I-NEXT: addi sp, sp, -16 365; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 366; RV64I-NEXT: call pow 367; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 368; RV64I-NEXT: addi sp, sp, 16 369; RV64I-NEXT: ret 370 %1 = call double @llvm.pow.f64(double %a, double %b) 371 ret double %1 372} 373 374declare double @llvm.exp.f64(double) 375 376define double @exp_f64(double %a) nounwind { 377; CHECKIFD-LABEL: exp_f64: 378; CHECKIFD: # %bb.0: 379; CHECKIFD-NEXT: tail exp 380; 381; RV32IZFINXZDINX-LABEL: exp_f64: 382; RV32IZFINXZDINX: # %bb.0: 383; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 384; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 385; RV32IZFINXZDINX-NEXT: call exp 386; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 387; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 388; RV32IZFINXZDINX-NEXT: ret 389; 390; RV64IZFINXZDINX-LABEL: exp_f64: 391; RV64IZFINXZDINX: # %bb.0: 392; RV64IZFINXZDINX-NEXT: tail exp 393; 394; RV32I-LABEL: exp_f64: 395; RV32I: # %bb.0: 396; RV32I-NEXT: addi sp, sp, -16 397; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 398; RV32I-NEXT: call exp 399; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 400; RV32I-NEXT: addi sp, sp, 16 401; RV32I-NEXT: ret 402; 403; RV64I-LABEL: exp_f64: 404; RV64I: # %bb.0: 405; RV64I-NEXT: addi sp, sp, -16 406; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 407; RV64I-NEXT: call exp 408; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 409; RV64I-NEXT: addi sp, sp, 16 410; RV64I-NEXT: ret 411 %1 = call double @llvm.exp.f64(double %a) 412 ret double %1 413} 414 415declare double @llvm.exp2.f64(double) 416 417define double @exp2_f64(double %a) nounwind { 418; CHECKIFD-LABEL: exp2_f64: 419; CHECKIFD: # %bb.0: 420; CHECKIFD-NEXT: tail exp2 421; 422; RV32IZFINXZDINX-LABEL: exp2_f64: 423; RV32IZFINXZDINX: # %bb.0: 424; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 425; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 426; RV32IZFINXZDINX-NEXT: call exp2 427; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 428; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 429; RV32IZFINXZDINX-NEXT: ret 430; 431; RV64IZFINXZDINX-LABEL: exp2_f64: 432; RV64IZFINXZDINX: # %bb.0: 433; RV64IZFINXZDINX-NEXT: tail exp2 434; 435; RV32I-LABEL: exp2_f64: 436; RV32I: # %bb.0: 437; RV32I-NEXT: addi sp, sp, -16 438; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 439; RV32I-NEXT: call exp2 440; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 441; RV32I-NEXT: addi sp, sp, 16 442; RV32I-NEXT: ret 443; 444; RV64I-LABEL: exp2_f64: 445; RV64I: # %bb.0: 446; RV64I-NEXT: addi sp, sp, -16 447; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 448; RV64I-NEXT: call exp2 449; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 450; RV64I-NEXT: addi sp, sp, 16 451; RV64I-NEXT: ret 452 %1 = call double @llvm.exp2.f64(double %a) 453 ret double %1 454} 455 456define double @exp10_f64(double %a) nounwind { 457; CHECKIFD-LABEL: exp10_f64: 458; CHECKIFD: # %bb.0: 459; CHECKIFD-NEXT: tail exp10 460; 461; RV32IZFINXZDINX-LABEL: exp10_f64: 462; RV32IZFINXZDINX: # %bb.0: 463; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 464; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 465; RV32IZFINXZDINX-NEXT: call exp10 466; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 467; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 468; RV32IZFINXZDINX-NEXT: ret 469; 470; RV64IZFINXZDINX-LABEL: exp10_f64: 471; RV64IZFINXZDINX: # %bb.0: 472; RV64IZFINXZDINX-NEXT: tail exp10 473; 474; RV32I-LABEL: exp10_f64: 475; RV32I: # %bb.0: 476; RV32I-NEXT: addi sp, sp, -16 477; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 478; RV32I-NEXT: call exp10 479; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 480; RV32I-NEXT: addi sp, sp, 16 481; RV32I-NEXT: ret 482; 483; RV64I-LABEL: exp10_f64: 484; RV64I: # %bb.0: 485; RV64I-NEXT: addi sp, sp, -16 486; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 487; RV64I-NEXT: call exp10 488; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 489; RV64I-NEXT: addi sp, sp, 16 490; RV64I-NEXT: ret 491 %1 = call double @llvm.exp10.f64(double %a) 492 ret double %1 493} 494 495declare double @llvm.log.f64(double) 496 497define double @log_f64(double %a) nounwind { 498; CHECKIFD-LABEL: log_f64: 499; CHECKIFD: # %bb.0: 500; CHECKIFD-NEXT: tail log 501; 502; RV32IZFINXZDINX-LABEL: log_f64: 503; RV32IZFINXZDINX: # %bb.0: 504; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 505; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 506; RV32IZFINXZDINX-NEXT: call log 507; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 508; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 509; RV32IZFINXZDINX-NEXT: ret 510; 511; RV64IZFINXZDINX-LABEL: log_f64: 512; RV64IZFINXZDINX: # %bb.0: 513; RV64IZFINXZDINX-NEXT: tail log 514; 515; RV32I-LABEL: log_f64: 516; RV32I: # %bb.0: 517; RV32I-NEXT: addi sp, sp, -16 518; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 519; RV32I-NEXT: call log 520; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 521; RV32I-NEXT: addi sp, sp, 16 522; RV32I-NEXT: ret 523; 524; RV64I-LABEL: log_f64: 525; RV64I: # %bb.0: 526; RV64I-NEXT: addi sp, sp, -16 527; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 528; RV64I-NEXT: call log 529; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 530; RV64I-NEXT: addi sp, sp, 16 531; RV64I-NEXT: ret 532 %1 = call double @llvm.log.f64(double %a) 533 ret double %1 534} 535 536declare double @llvm.log10.f64(double) 537 538define double @log10_f64(double %a) nounwind { 539; CHECKIFD-LABEL: log10_f64: 540; CHECKIFD: # %bb.0: 541; CHECKIFD-NEXT: tail log10 542; 543; RV32IZFINXZDINX-LABEL: log10_f64: 544; RV32IZFINXZDINX: # %bb.0: 545; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 546; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 547; RV32IZFINXZDINX-NEXT: call log10 548; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 549; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 550; RV32IZFINXZDINX-NEXT: ret 551; 552; RV64IZFINXZDINX-LABEL: log10_f64: 553; RV64IZFINXZDINX: # %bb.0: 554; RV64IZFINXZDINX-NEXT: tail log10 555; 556; RV32I-LABEL: log10_f64: 557; RV32I: # %bb.0: 558; RV32I-NEXT: addi sp, sp, -16 559; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 560; RV32I-NEXT: call log10 561; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 562; RV32I-NEXT: addi sp, sp, 16 563; RV32I-NEXT: ret 564; 565; RV64I-LABEL: log10_f64: 566; RV64I: # %bb.0: 567; RV64I-NEXT: addi sp, sp, -16 568; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 569; RV64I-NEXT: call log10 570; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 571; RV64I-NEXT: addi sp, sp, 16 572; RV64I-NEXT: ret 573 %1 = call double @llvm.log10.f64(double %a) 574 ret double %1 575} 576 577declare double @llvm.log2.f64(double) 578 579define double @log2_f64(double %a) nounwind { 580; CHECKIFD-LABEL: log2_f64: 581; CHECKIFD: # %bb.0: 582; CHECKIFD-NEXT: tail log2 583; 584; RV32IZFINXZDINX-LABEL: log2_f64: 585; RV32IZFINXZDINX: # %bb.0: 586; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 587; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 588; RV32IZFINXZDINX-NEXT: call log2 589; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 590; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 591; RV32IZFINXZDINX-NEXT: ret 592; 593; RV64IZFINXZDINX-LABEL: log2_f64: 594; RV64IZFINXZDINX: # %bb.0: 595; RV64IZFINXZDINX-NEXT: tail log2 596; 597; RV32I-LABEL: log2_f64: 598; RV32I: # %bb.0: 599; RV32I-NEXT: addi sp, sp, -16 600; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 601; RV32I-NEXT: call log2 602; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 603; RV32I-NEXT: addi sp, sp, 16 604; RV32I-NEXT: ret 605; 606; RV64I-LABEL: log2_f64: 607; RV64I: # %bb.0: 608; RV64I-NEXT: addi sp, sp, -16 609; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 610; RV64I-NEXT: call log2 611; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 612; RV64I-NEXT: addi sp, sp, 16 613; RV64I-NEXT: ret 614 %1 = call double @llvm.log2.f64(double %a) 615 ret double %1 616} 617 618declare double @llvm.fma.f64(double, double, double) 619 620define double @fma_f64(double %a, double %b, double %c) nounwind { 621; CHECKIFD-LABEL: fma_f64: 622; CHECKIFD: # %bb.0: 623; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2 624; CHECKIFD-NEXT: ret 625; 626; RV32IZFINXZDINX-LABEL: fma_f64: 627; RV32IZFINXZDINX: # %bb.0: 628; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4 629; RV32IZFINXZDINX-NEXT: ret 630; 631; RV64IZFINXZDINX-LABEL: fma_f64: 632; RV64IZFINXZDINX: # %bb.0: 633; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2 634; RV64IZFINXZDINX-NEXT: ret 635; 636; RV32I-LABEL: fma_f64: 637; RV32I: # %bb.0: 638; RV32I-NEXT: addi sp, sp, -16 639; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 640; RV32I-NEXT: call fma 641; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 642; RV32I-NEXT: addi sp, sp, 16 643; RV32I-NEXT: ret 644; 645; RV64I-LABEL: fma_f64: 646; RV64I: # %bb.0: 647; RV64I-NEXT: addi sp, sp, -16 648; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 649; RV64I-NEXT: call fma 650; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 651; RV64I-NEXT: addi sp, sp, 16 652; RV64I-NEXT: ret 653 %1 = call double @llvm.fma.f64(double %a, double %b, double %c) 654 ret double %1 655} 656 657declare double @llvm.fmuladd.f64(double, double, double) 658 659define double @fmuladd_f64(double %a, double %b, double %c) nounwind { 660; CHECKIFD-LABEL: fmuladd_f64: 661; CHECKIFD: # %bb.0: 662; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2 663; CHECKIFD-NEXT: ret 664; 665; RV32IZFINXZDINX-LABEL: fmuladd_f64: 666; RV32IZFINXZDINX: # %bb.0: 667; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4 668; RV32IZFINXZDINX-NEXT: ret 669; 670; RV64IZFINXZDINX-LABEL: fmuladd_f64: 671; RV64IZFINXZDINX: # %bb.0: 672; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2 673; RV64IZFINXZDINX-NEXT: ret 674; 675; RV32I-LABEL: fmuladd_f64: 676; RV32I: # %bb.0: 677; RV32I-NEXT: addi sp, sp, -16 678; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 679; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 680; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 681; RV32I-NEXT: mv s0, a5 682; RV32I-NEXT: mv s1, a4 683; RV32I-NEXT: call __muldf3 684; RV32I-NEXT: mv a2, s1 685; RV32I-NEXT: mv a3, s0 686; RV32I-NEXT: call __adddf3 687; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 688; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 689; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 690; RV32I-NEXT: addi sp, sp, 16 691; RV32I-NEXT: ret 692; 693; RV64I-LABEL: fmuladd_f64: 694; RV64I: # %bb.0: 695; RV64I-NEXT: addi sp, sp, -16 696; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 697; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 698; RV64I-NEXT: mv s0, a2 699; RV64I-NEXT: call __muldf3 700; RV64I-NEXT: mv a1, s0 701; RV64I-NEXT: call __adddf3 702; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 703; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 704; RV64I-NEXT: addi sp, sp, 16 705; RV64I-NEXT: ret 706 %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c) 707 ret double %1 708} 709 710declare double @llvm.fabs.f64(double) 711 712define double @fabs_f64(double %a) nounwind { 713; CHECKIFD-LABEL: fabs_f64: 714; CHECKIFD: # %bb.0: 715; CHECKIFD-NEXT: fabs.d fa0, fa0 716; CHECKIFD-NEXT: ret 717; 718; RV32IZFINXZDINX-LABEL: fabs_f64: 719; RV32IZFINXZDINX: # %bb.0: 720; RV32IZFINXZDINX-NEXT: fabs.d a0, a0 721; RV32IZFINXZDINX-NEXT: ret 722; 723; RV64IZFINXZDINX-LABEL: fabs_f64: 724; RV64IZFINXZDINX: # %bb.0: 725; RV64IZFINXZDINX-NEXT: fabs.d a0, a0 726; RV64IZFINXZDINX-NEXT: ret 727; 728; RV32I-LABEL: fabs_f64: 729; RV32I: # %bb.0: 730; RV32I-NEXT: slli a1, a1, 1 731; RV32I-NEXT: srli a1, a1, 1 732; RV32I-NEXT: ret 733; 734; RV64I-LABEL: fabs_f64: 735; RV64I: # %bb.0: 736; RV64I-NEXT: slli a0, a0, 1 737; RV64I-NEXT: srli a0, a0, 1 738; RV64I-NEXT: ret 739 %1 = call double @llvm.fabs.f64(double %a) 740 ret double %1 741} 742 743declare double @llvm.minnum.f64(double, double) 744 745define double @minnum_f64(double %a, double %b) nounwind { 746; CHECKIFD-LABEL: minnum_f64: 747; CHECKIFD: # %bb.0: 748; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1 749; CHECKIFD-NEXT: ret 750; 751; RV32IZFINXZDINX-LABEL: minnum_f64: 752; RV32IZFINXZDINX: # %bb.0: 753; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2 754; RV32IZFINXZDINX-NEXT: ret 755; 756; RV64IZFINXZDINX-LABEL: minnum_f64: 757; RV64IZFINXZDINX: # %bb.0: 758; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1 759; RV64IZFINXZDINX-NEXT: ret 760; 761; RV32I-LABEL: minnum_f64: 762; RV32I: # %bb.0: 763; RV32I-NEXT: addi sp, sp, -16 764; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 765; RV32I-NEXT: call fmin 766; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 767; RV32I-NEXT: addi sp, sp, 16 768; RV32I-NEXT: ret 769; 770; RV64I-LABEL: minnum_f64: 771; RV64I: # %bb.0: 772; RV64I-NEXT: addi sp, sp, -16 773; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 774; RV64I-NEXT: call fmin 775; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 776; RV64I-NEXT: addi sp, sp, 16 777; RV64I-NEXT: ret 778 %1 = call double @llvm.minnum.f64(double %a, double %b) 779 ret double %1 780} 781 782declare double @llvm.maxnum.f64(double, double) 783 784define double @maxnum_f64(double %a, double %b) nounwind { 785; CHECKIFD-LABEL: maxnum_f64: 786; CHECKIFD: # %bb.0: 787; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1 788; CHECKIFD-NEXT: ret 789; 790; RV32IZFINXZDINX-LABEL: maxnum_f64: 791; RV32IZFINXZDINX: # %bb.0: 792; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2 793; RV32IZFINXZDINX-NEXT: ret 794; 795; RV64IZFINXZDINX-LABEL: maxnum_f64: 796; RV64IZFINXZDINX: # %bb.0: 797; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1 798; RV64IZFINXZDINX-NEXT: ret 799; 800; RV32I-LABEL: maxnum_f64: 801; RV32I: # %bb.0: 802; RV32I-NEXT: addi sp, sp, -16 803; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 804; RV32I-NEXT: call fmax 805; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 806; RV32I-NEXT: addi sp, sp, 16 807; RV32I-NEXT: ret 808; 809; RV64I-LABEL: maxnum_f64: 810; RV64I: # %bb.0: 811; RV64I-NEXT: addi sp, sp, -16 812; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 813; RV64I-NEXT: call fmax 814; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 815; RV64I-NEXT: addi sp, sp, 16 816; RV64I-NEXT: ret 817 %1 = call double @llvm.maxnum.f64(double %a, double %b) 818 ret double %1 819} 820 821; TODO: FMINNAN and FMAXNAN aren't handled in 822; SelectionDAGLegalize::ExpandNode. 823 824; declare double @llvm.minimum.f64(double, double) 825 826; define double @fminimum_f64(double %a, double %b) nounwind { 827; %1 = call double @llvm.minimum.f64(double %a, double %b) 828; ret double %1 829; } 830 831; declare double @llvm.maximum.f64(double, double) 832 833; define double @fmaximum_f64(double %a, double %b) nounwind { 834; %1 = call double @llvm.maximum.f64(double %a, double %b) 835; ret double %1 836; } 837 838declare double @llvm.copysign.f64(double, double) 839 840define double @copysign_f64(double %a, double %b) nounwind { 841; CHECKIFD-LABEL: copysign_f64: 842; CHECKIFD: # %bb.0: 843; CHECKIFD-NEXT: fsgnj.d fa0, fa0, fa1 844; CHECKIFD-NEXT: ret 845; 846; RV32IZFINXZDINX-LABEL: copysign_f64: 847; RV32IZFINXZDINX: # %bb.0: 848; RV32IZFINXZDINX-NEXT: fsgnj.d a0, a0, a2 849; RV32IZFINXZDINX-NEXT: ret 850; 851; RV64IZFINXZDINX-LABEL: copysign_f64: 852; RV64IZFINXZDINX: # %bb.0: 853; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a0, a1 854; RV64IZFINXZDINX-NEXT: ret 855; 856; RV32I-LABEL: copysign_f64: 857; RV32I: # %bb.0: 858; RV32I-NEXT: lui a2, 524288 859; RV32I-NEXT: slli a1, a1, 1 860; RV32I-NEXT: and a2, a3, a2 861; RV32I-NEXT: srli a1, a1, 1 862; RV32I-NEXT: or a1, a1, a2 863; RV32I-NEXT: ret 864; 865; RV64I-LABEL: copysign_f64: 866; RV64I: # %bb.0: 867; RV64I-NEXT: srli a1, a1, 63 868; RV64I-NEXT: slli a0, a0, 1 869; RV64I-NEXT: slli a1, a1, 63 870; RV64I-NEXT: srli a0, a0, 1 871; RV64I-NEXT: or a0, a0, a1 872; RV64I-NEXT: ret 873 %1 = call double @llvm.copysign.f64(double %a, double %b) 874 ret double %1 875} 876 877declare double @llvm.floor.f64(double) 878 879define double @floor_f64(double %a) nounwind { 880; RV32IFD-LABEL: floor_f64: 881; RV32IFD: # %bb.0: 882; RV32IFD-NEXT: tail floor 883; 884; RV64IFD-LABEL: floor_f64: 885; RV64IFD: # %bb.0: 886; RV64IFD-NEXT: lui a0, %hi(.LCPI18_0) 887; RV64IFD-NEXT: fld fa5, %lo(.LCPI18_0)(a0) 888; RV64IFD-NEXT: fabs.d fa4, fa0 889; RV64IFD-NEXT: flt.d a0, fa4, fa5 890; RV64IFD-NEXT: beqz a0, .LBB18_2 891; RV64IFD-NEXT: # %bb.1: 892; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn 893; RV64IFD-NEXT: fcvt.d.l fa5, a0, rdn 894; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0 895; RV64IFD-NEXT: .LBB18_2: 896; RV64IFD-NEXT: ret 897; 898; RV32IZFINXZDINX-LABEL: floor_f64: 899; RV32IZFINXZDINX: # %bb.0: 900; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 901; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 902; RV32IZFINXZDINX-NEXT: call floor 903; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 904; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 905; RV32IZFINXZDINX-NEXT: ret 906; 907; RV64IZFINXZDINX-LABEL: floor_f64: 908; RV64IZFINXZDINX: # %bb.0: 909; RV64IZFINXZDINX-NEXT: li a1, 1075 910; RV64IZFINXZDINX-NEXT: slli a1, a1, 52 911; RV64IZFINXZDINX-NEXT: fabs.d a2, a0 912; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1 913; RV64IZFINXZDINX-NEXT: beqz a1, .LBB18_2 914; RV64IZFINXZDINX-NEXT: # %bb.1: 915; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rdn 916; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rdn 917; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0 918; RV64IZFINXZDINX-NEXT: .LBB18_2: 919; RV64IZFINXZDINX-NEXT: ret 920; 921; RV32I-LABEL: floor_f64: 922; RV32I: # %bb.0: 923; RV32I-NEXT: addi sp, sp, -16 924; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 925; RV32I-NEXT: call floor 926; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 927; RV32I-NEXT: addi sp, sp, 16 928; RV32I-NEXT: ret 929; 930; RV64I-LABEL: floor_f64: 931; RV64I: # %bb.0: 932; RV64I-NEXT: addi sp, sp, -16 933; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 934; RV64I-NEXT: call floor 935; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 936; RV64I-NEXT: addi sp, sp, 16 937; RV64I-NEXT: ret 938 %1 = call double @llvm.floor.f64(double %a) 939 ret double %1 940} 941 942declare double @llvm.ceil.f64(double) 943 944define double @ceil_f64(double %a) nounwind { 945; RV32IFD-LABEL: ceil_f64: 946; RV32IFD: # %bb.0: 947; RV32IFD-NEXT: tail ceil 948; 949; RV64IFD-LABEL: ceil_f64: 950; RV64IFD: # %bb.0: 951; RV64IFD-NEXT: lui a0, %hi(.LCPI19_0) 952; RV64IFD-NEXT: fld fa5, %lo(.LCPI19_0)(a0) 953; RV64IFD-NEXT: fabs.d fa4, fa0 954; RV64IFD-NEXT: flt.d a0, fa4, fa5 955; RV64IFD-NEXT: beqz a0, .LBB19_2 956; RV64IFD-NEXT: # %bb.1: 957; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup 958; RV64IFD-NEXT: fcvt.d.l fa5, a0, rup 959; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0 960; RV64IFD-NEXT: .LBB19_2: 961; RV64IFD-NEXT: ret 962; 963; RV32IZFINXZDINX-LABEL: ceil_f64: 964; RV32IZFINXZDINX: # %bb.0: 965; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 966; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 967; RV32IZFINXZDINX-NEXT: call ceil 968; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 969; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 970; RV32IZFINXZDINX-NEXT: ret 971; 972; RV64IZFINXZDINX-LABEL: ceil_f64: 973; RV64IZFINXZDINX: # %bb.0: 974; RV64IZFINXZDINX-NEXT: li a1, 1075 975; RV64IZFINXZDINX-NEXT: slli a1, a1, 52 976; RV64IZFINXZDINX-NEXT: fabs.d a2, a0 977; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1 978; RV64IZFINXZDINX-NEXT: beqz a1, .LBB19_2 979; RV64IZFINXZDINX-NEXT: # %bb.1: 980; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rup 981; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rup 982; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0 983; RV64IZFINXZDINX-NEXT: .LBB19_2: 984; RV64IZFINXZDINX-NEXT: ret 985; 986; RV32I-LABEL: ceil_f64: 987; RV32I: # %bb.0: 988; RV32I-NEXT: addi sp, sp, -16 989; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 990; RV32I-NEXT: call ceil 991; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 992; RV32I-NEXT: addi sp, sp, 16 993; RV32I-NEXT: ret 994; 995; RV64I-LABEL: ceil_f64: 996; RV64I: # %bb.0: 997; RV64I-NEXT: addi sp, sp, -16 998; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 999; RV64I-NEXT: call ceil 1000; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1001; RV64I-NEXT: addi sp, sp, 16 1002; RV64I-NEXT: ret 1003 %1 = call double @llvm.ceil.f64(double %a) 1004 ret double %1 1005} 1006 1007declare double @llvm.trunc.f64(double) 1008 1009define double @trunc_f64(double %a) nounwind { 1010; RV32IFD-LABEL: trunc_f64: 1011; RV32IFD: # %bb.0: 1012; RV32IFD-NEXT: tail trunc 1013; 1014; RV64IFD-LABEL: trunc_f64: 1015; RV64IFD: # %bb.0: 1016; RV64IFD-NEXT: lui a0, %hi(.LCPI20_0) 1017; RV64IFD-NEXT: fld fa5, %lo(.LCPI20_0)(a0) 1018; RV64IFD-NEXT: fabs.d fa4, fa0 1019; RV64IFD-NEXT: flt.d a0, fa4, fa5 1020; RV64IFD-NEXT: beqz a0, .LBB20_2 1021; RV64IFD-NEXT: # %bb.1: 1022; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz 1023; RV64IFD-NEXT: fcvt.d.l fa5, a0, rtz 1024; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0 1025; RV64IFD-NEXT: .LBB20_2: 1026; RV64IFD-NEXT: ret 1027; 1028; RV32IZFINXZDINX-LABEL: trunc_f64: 1029; RV32IZFINXZDINX: # %bb.0: 1030; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1031; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1032; RV32IZFINXZDINX-NEXT: call trunc 1033; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1034; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1035; RV32IZFINXZDINX-NEXT: ret 1036; 1037; RV64IZFINXZDINX-LABEL: trunc_f64: 1038; RV64IZFINXZDINX: # %bb.0: 1039; RV64IZFINXZDINX-NEXT: li a1, 1075 1040; RV64IZFINXZDINX-NEXT: slli a1, a1, 52 1041; RV64IZFINXZDINX-NEXT: fabs.d a2, a0 1042; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1 1043; RV64IZFINXZDINX-NEXT: beqz a1, .LBB20_2 1044; RV64IZFINXZDINX-NEXT: # %bb.1: 1045; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rtz 1046; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rtz 1047; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0 1048; RV64IZFINXZDINX-NEXT: .LBB20_2: 1049; RV64IZFINXZDINX-NEXT: ret 1050; 1051; RV32I-LABEL: trunc_f64: 1052; RV32I: # %bb.0: 1053; RV32I-NEXT: addi sp, sp, -16 1054; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1055; RV32I-NEXT: call trunc 1056; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1057; RV32I-NEXT: addi sp, sp, 16 1058; RV32I-NEXT: ret 1059; 1060; RV64I-LABEL: trunc_f64: 1061; RV64I: # %bb.0: 1062; RV64I-NEXT: addi sp, sp, -16 1063; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1064; RV64I-NEXT: call trunc 1065; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1066; RV64I-NEXT: addi sp, sp, 16 1067; RV64I-NEXT: ret 1068 %1 = call double @llvm.trunc.f64(double %a) 1069 ret double %1 1070} 1071 1072declare double @llvm.rint.f64(double) 1073 1074define double @rint_f64(double %a) nounwind { 1075; RV32IFD-LABEL: rint_f64: 1076; RV32IFD: # %bb.0: 1077; RV32IFD-NEXT: tail rint 1078; 1079; RV64IFD-LABEL: rint_f64: 1080; RV64IFD: # %bb.0: 1081; RV64IFD-NEXT: lui a0, %hi(.LCPI21_0) 1082; RV64IFD-NEXT: fld fa5, %lo(.LCPI21_0)(a0) 1083; RV64IFD-NEXT: fabs.d fa4, fa0 1084; RV64IFD-NEXT: flt.d a0, fa4, fa5 1085; RV64IFD-NEXT: beqz a0, .LBB21_2 1086; RV64IFD-NEXT: # %bb.1: 1087; RV64IFD-NEXT: fcvt.l.d a0, fa0 1088; RV64IFD-NEXT: fcvt.d.l fa5, a0 1089; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0 1090; RV64IFD-NEXT: .LBB21_2: 1091; RV64IFD-NEXT: ret 1092; 1093; RV32IZFINXZDINX-LABEL: rint_f64: 1094; RV32IZFINXZDINX: # %bb.0: 1095; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1096; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1097; RV32IZFINXZDINX-NEXT: call rint 1098; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1099; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1100; RV32IZFINXZDINX-NEXT: ret 1101; 1102; RV64IZFINXZDINX-LABEL: rint_f64: 1103; RV64IZFINXZDINX: # %bb.0: 1104; RV64IZFINXZDINX-NEXT: li a1, 1075 1105; RV64IZFINXZDINX-NEXT: slli a1, a1, 52 1106; RV64IZFINXZDINX-NEXT: fabs.d a2, a0 1107; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1 1108; RV64IZFINXZDINX-NEXT: beqz a1, .LBB21_2 1109; RV64IZFINXZDINX-NEXT: # %bb.1: 1110; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0 1111; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1 1112; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0 1113; RV64IZFINXZDINX-NEXT: .LBB21_2: 1114; RV64IZFINXZDINX-NEXT: ret 1115; 1116; RV32I-LABEL: rint_f64: 1117; RV32I: # %bb.0: 1118; RV32I-NEXT: addi sp, sp, -16 1119; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1120; RV32I-NEXT: call rint 1121; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1122; RV32I-NEXT: addi sp, sp, 16 1123; RV32I-NEXT: ret 1124; 1125; RV64I-LABEL: rint_f64: 1126; RV64I: # %bb.0: 1127; RV64I-NEXT: addi sp, sp, -16 1128; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1129; RV64I-NEXT: call rint 1130; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1131; RV64I-NEXT: addi sp, sp, 16 1132; RV64I-NEXT: ret 1133 %1 = call double @llvm.rint.f64(double %a) 1134 ret double %1 1135} 1136 1137declare double @llvm.nearbyint.f64(double) 1138 1139define double @nearbyint_f64(double %a) nounwind { 1140; CHECKIFD-LABEL: nearbyint_f64: 1141; CHECKIFD: # %bb.0: 1142; CHECKIFD-NEXT: tail nearbyint 1143; 1144; RV32IZFINXZDINX-LABEL: nearbyint_f64: 1145; RV32IZFINXZDINX: # %bb.0: 1146; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1147; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1148; RV32IZFINXZDINX-NEXT: call nearbyint 1149; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1150; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1151; RV32IZFINXZDINX-NEXT: ret 1152; 1153; RV64IZFINXZDINX-LABEL: nearbyint_f64: 1154; RV64IZFINXZDINX: # %bb.0: 1155; RV64IZFINXZDINX-NEXT: tail nearbyint 1156; 1157; RV32I-LABEL: nearbyint_f64: 1158; RV32I: # %bb.0: 1159; RV32I-NEXT: addi sp, sp, -16 1160; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1161; RV32I-NEXT: call nearbyint 1162; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1163; RV32I-NEXT: addi sp, sp, 16 1164; RV32I-NEXT: ret 1165; 1166; RV64I-LABEL: nearbyint_f64: 1167; RV64I: # %bb.0: 1168; RV64I-NEXT: addi sp, sp, -16 1169; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1170; RV64I-NEXT: call nearbyint 1171; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1172; RV64I-NEXT: addi sp, sp, 16 1173; RV64I-NEXT: ret 1174 %1 = call double @llvm.nearbyint.f64(double %a) 1175 ret double %1 1176} 1177 1178declare double @llvm.round.f64(double) 1179 1180define double @round_f64(double %a) nounwind { 1181; RV32IFD-LABEL: round_f64: 1182; RV32IFD: # %bb.0: 1183; RV32IFD-NEXT: tail round 1184; 1185; RV64IFD-LABEL: round_f64: 1186; RV64IFD: # %bb.0: 1187; RV64IFD-NEXT: lui a0, %hi(.LCPI23_0) 1188; RV64IFD-NEXT: fld fa5, %lo(.LCPI23_0)(a0) 1189; RV64IFD-NEXT: fabs.d fa4, fa0 1190; RV64IFD-NEXT: flt.d a0, fa4, fa5 1191; RV64IFD-NEXT: beqz a0, .LBB23_2 1192; RV64IFD-NEXT: # %bb.1: 1193; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm 1194; RV64IFD-NEXT: fcvt.d.l fa5, a0, rmm 1195; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0 1196; RV64IFD-NEXT: .LBB23_2: 1197; RV64IFD-NEXT: ret 1198; 1199; RV32IZFINXZDINX-LABEL: round_f64: 1200; RV32IZFINXZDINX: # %bb.0: 1201; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1202; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1203; RV32IZFINXZDINX-NEXT: call round 1204; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1205; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1206; RV32IZFINXZDINX-NEXT: ret 1207; 1208; RV64IZFINXZDINX-LABEL: round_f64: 1209; RV64IZFINXZDINX: # %bb.0: 1210; RV64IZFINXZDINX-NEXT: li a1, 1075 1211; RV64IZFINXZDINX-NEXT: slli a1, a1, 52 1212; RV64IZFINXZDINX-NEXT: fabs.d a2, a0 1213; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1 1214; RV64IZFINXZDINX-NEXT: beqz a1, .LBB23_2 1215; RV64IZFINXZDINX-NEXT: # %bb.1: 1216; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rmm 1217; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rmm 1218; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0 1219; RV64IZFINXZDINX-NEXT: .LBB23_2: 1220; RV64IZFINXZDINX-NEXT: ret 1221; 1222; RV32I-LABEL: round_f64: 1223; RV32I: # %bb.0: 1224; RV32I-NEXT: addi sp, sp, -16 1225; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1226; RV32I-NEXT: call round 1227; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1228; RV32I-NEXT: addi sp, sp, 16 1229; RV32I-NEXT: ret 1230; 1231; RV64I-LABEL: round_f64: 1232; RV64I: # %bb.0: 1233; RV64I-NEXT: addi sp, sp, -16 1234; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1235; RV64I-NEXT: call round 1236; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1237; RV64I-NEXT: addi sp, sp, 16 1238; RV64I-NEXT: ret 1239 %1 = call double @llvm.round.f64(double %a) 1240 ret double %1 1241} 1242 1243declare double @llvm.roundeven.f64(double) 1244 1245define double @roundeven_f64(double %a) nounwind { 1246; RV32IFD-LABEL: roundeven_f64: 1247; RV32IFD: # %bb.0: 1248; RV32IFD-NEXT: tail roundeven 1249; 1250; RV64IFD-LABEL: roundeven_f64: 1251; RV64IFD: # %bb.0: 1252; RV64IFD-NEXT: lui a0, %hi(.LCPI24_0) 1253; RV64IFD-NEXT: fld fa5, %lo(.LCPI24_0)(a0) 1254; RV64IFD-NEXT: fabs.d fa4, fa0 1255; RV64IFD-NEXT: flt.d a0, fa4, fa5 1256; RV64IFD-NEXT: beqz a0, .LBB24_2 1257; RV64IFD-NEXT: # %bb.1: 1258; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne 1259; RV64IFD-NEXT: fcvt.d.l fa5, a0, rne 1260; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa0 1261; RV64IFD-NEXT: .LBB24_2: 1262; RV64IFD-NEXT: ret 1263; 1264; RV32IZFINXZDINX-LABEL: roundeven_f64: 1265; RV32IZFINXZDINX: # %bb.0: 1266; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1267; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1268; RV32IZFINXZDINX-NEXT: call roundeven 1269; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1270; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1271; RV32IZFINXZDINX-NEXT: ret 1272; 1273; RV64IZFINXZDINX-LABEL: roundeven_f64: 1274; RV64IZFINXZDINX: # %bb.0: 1275; RV64IZFINXZDINX-NEXT: li a1, 1075 1276; RV64IZFINXZDINX-NEXT: slli a1, a1, 52 1277; RV64IZFINXZDINX-NEXT: fabs.d a2, a0 1278; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a1 1279; RV64IZFINXZDINX-NEXT: beqz a1, .LBB24_2 1280; RV64IZFINXZDINX-NEXT: # %bb.1: 1281; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rne 1282; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rne 1283; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a0 1284; RV64IZFINXZDINX-NEXT: .LBB24_2: 1285; RV64IZFINXZDINX-NEXT: ret 1286; 1287; RV32I-LABEL: roundeven_f64: 1288; RV32I: # %bb.0: 1289; RV32I-NEXT: addi sp, sp, -16 1290; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1291; RV32I-NEXT: call roundeven 1292; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1293; RV32I-NEXT: addi sp, sp, 16 1294; RV32I-NEXT: ret 1295; 1296; RV64I-LABEL: roundeven_f64: 1297; RV64I: # %bb.0: 1298; RV64I-NEXT: addi sp, sp, -16 1299; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1300; RV64I-NEXT: call roundeven 1301; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1302; RV64I-NEXT: addi sp, sp, 16 1303; RV64I-NEXT: ret 1304 %1 = call double @llvm.roundeven.f64(double %a) 1305 ret double %1 1306} 1307 1308declare iXLen @llvm.lrint.iXLen.f64(double) 1309 1310define iXLen @lrint_f64(double %a) nounwind { 1311; RV32IFD-LABEL: lrint_f64: 1312; RV32IFD: # %bb.0: 1313; RV32IFD-NEXT: fcvt.w.d a0, fa0 1314; RV32IFD-NEXT: ret 1315; 1316; RV64IFD-LABEL: lrint_f64: 1317; RV64IFD: # %bb.0: 1318; RV64IFD-NEXT: fcvt.l.d a0, fa0 1319; RV64IFD-NEXT: ret 1320; 1321; RV32IZFINXZDINX-LABEL: lrint_f64: 1322; RV32IZFINXZDINX: # %bb.0: 1323; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0 1324; RV32IZFINXZDINX-NEXT: ret 1325; 1326; RV64IZFINXZDINX-LABEL: lrint_f64: 1327; RV64IZFINXZDINX: # %bb.0: 1328; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0 1329; RV64IZFINXZDINX-NEXT: ret 1330; 1331; RV32I-LABEL: lrint_f64: 1332; RV32I: # %bb.0: 1333; RV32I-NEXT: addi sp, sp, -16 1334; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1335; RV32I-NEXT: call lrint 1336; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1337; RV32I-NEXT: addi sp, sp, 16 1338; RV32I-NEXT: ret 1339; 1340; RV64I-LABEL: lrint_f64: 1341; RV64I: # %bb.0: 1342; RV64I-NEXT: addi sp, sp, -16 1343; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1344; RV64I-NEXT: call lrint 1345; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1346; RV64I-NEXT: addi sp, sp, 16 1347; RV64I-NEXT: ret 1348 %1 = call iXLen @llvm.lrint.iXLen.f64(double %a) 1349 ret iXLen %1 1350} 1351 1352declare i32 @llvm.lround.i32.f64(double) 1353declare i64 @llvm.lround.i64.f64(double) 1354 1355define iXLen @lround_f64(double %a) nounwind { 1356; RV32IFD-LABEL: lround_f64: 1357; RV32IFD: # %bb.0: 1358; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm 1359; RV32IFD-NEXT: ret 1360; 1361; RV64IFD-LABEL: lround_f64: 1362; RV64IFD: # %bb.0: 1363; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm 1364; RV64IFD-NEXT: ret 1365; 1366; RV32IZFINXZDINX-LABEL: lround_f64: 1367; RV32IZFINXZDINX: # %bb.0: 1368; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm 1369; RV32IZFINXZDINX-NEXT: ret 1370; 1371; RV64IZFINXZDINX-LABEL: lround_f64: 1372; RV64IZFINXZDINX: # %bb.0: 1373; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm 1374; RV64IZFINXZDINX-NEXT: ret 1375; 1376; RV32I-LABEL: lround_f64: 1377; RV32I: # %bb.0: 1378; RV32I-NEXT: addi sp, sp, -16 1379; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1380; RV32I-NEXT: call lround 1381; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1382; RV32I-NEXT: addi sp, sp, 16 1383; RV32I-NEXT: ret 1384; 1385; RV64I-LABEL: lround_f64: 1386; RV64I: # %bb.0: 1387; RV64I-NEXT: addi sp, sp, -16 1388; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1389; RV64I-NEXT: call lround 1390; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1391; RV64I-NEXT: addi sp, sp, 16 1392; RV64I-NEXT: ret 1393 %1 = call iXLen @llvm.lround.iXLen.f64(double %a) 1394 ret iXLen %1 1395} 1396 1397define i32 @lround_i32_f64(double %a) nounwind { 1398; CHECKIFD-LABEL: lround_i32_f64: 1399; CHECKIFD: # %bb.0: 1400; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rmm 1401; CHECKIFD-NEXT: ret 1402; 1403; RV32IZFINXZDINX-LABEL: lround_i32_f64: 1404; RV32IZFINXZDINX: # %bb.0: 1405; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm 1406; RV32IZFINXZDINX-NEXT: ret 1407; 1408; RV64IZFINXZDINX-LABEL: lround_i32_f64: 1409; RV64IZFINXZDINX: # %bb.0: 1410; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm 1411; RV64IZFINXZDINX-NEXT: ret 1412; 1413; RV32I-LABEL: lround_i32_f64: 1414; RV32I: # %bb.0: 1415; RV32I-NEXT: addi sp, sp, -16 1416; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1417; RV32I-NEXT: call lround 1418; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1419; RV32I-NEXT: addi sp, sp, 16 1420; RV32I-NEXT: ret 1421; 1422; RV64I-LABEL: lround_i32_f64: 1423; RV64I: # %bb.0: 1424; RV64I-NEXT: addi sp, sp, -16 1425; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1426; RV64I-NEXT: call lround 1427; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1428; RV64I-NEXT: addi sp, sp, 16 1429; RV64I-NEXT: ret 1430 %1 = call i32 @llvm.lround.i32.f64(double %a) 1431 ret i32 %1 1432} 1433 1434declare i64 @llvm.llrint.i64.f64(double) 1435 1436define i64 @llrint_f64(double %a) nounwind { 1437; RV32IFD-LABEL: llrint_f64: 1438; RV32IFD: # %bb.0: 1439; RV32IFD-NEXT: addi sp, sp, -16 1440; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1441; RV32IFD-NEXT: call llrint 1442; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1443; RV32IFD-NEXT: addi sp, sp, 16 1444; RV32IFD-NEXT: ret 1445; 1446; RV64IFD-LABEL: llrint_f64: 1447; RV64IFD: # %bb.0: 1448; RV64IFD-NEXT: fcvt.l.d a0, fa0 1449; RV64IFD-NEXT: ret 1450; 1451; RV32IZFINXZDINX-LABEL: llrint_f64: 1452; RV32IZFINXZDINX: # %bb.0: 1453; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1454; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1455; RV32IZFINXZDINX-NEXT: call llrint 1456; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1457; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1458; RV32IZFINXZDINX-NEXT: ret 1459; 1460; RV64IZFINXZDINX-LABEL: llrint_f64: 1461; RV64IZFINXZDINX: # %bb.0: 1462; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0 1463; RV64IZFINXZDINX-NEXT: ret 1464; 1465; RV32I-LABEL: llrint_f64: 1466; RV32I: # %bb.0: 1467; RV32I-NEXT: addi sp, sp, -16 1468; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1469; RV32I-NEXT: call llrint 1470; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1471; RV32I-NEXT: addi sp, sp, 16 1472; RV32I-NEXT: ret 1473; 1474; RV64I-LABEL: llrint_f64: 1475; RV64I: # %bb.0: 1476; RV64I-NEXT: addi sp, sp, -16 1477; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1478; RV64I-NEXT: call llrint 1479; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1480; RV64I-NEXT: addi sp, sp, 16 1481; RV64I-NEXT: ret 1482 %1 = call i64 @llvm.llrint.i64.f64(double %a) 1483 ret i64 %1 1484} 1485 1486declare i64 @llvm.llround.i64.f64(double) 1487 1488define i64 @llround_f64(double %a) nounwind { 1489; RV32IFD-LABEL: llround_f64: 1490; RV32IFD: # %bb.0: 1491; RV32IFD-NEXT: addi sp, sp, -16 1492; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1493; RV32IFD-NEXT: call llround 1494; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1495; RV32IFD-NEXT: addi sp, sp, 16 1496; RV32IFD-NEXT: ret 1497; 1498; RV64IFD-LABEL: llround_f64: 1499; RV64IFD: # %bb.0: 1500; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm 1501; RV64IFD-NEXT: ret 1502; 1503; RV32IZFINXZDINX-LABEL: llround_f64: 1504; RV32IZFINXZDINX: # %bb.0: 1505; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1506; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1507; RV32IZFINXZDINX-NEXT: call llround 1508; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1509; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1510; RV32IZFINXZDINX-NEXT: ret 1511; 1512; RV64IZFINXZDINX-LABEL: llround_f64: 1513; RV64IZFINXZDINX: # %bb.0: 1514; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm 1515; RV64IZFINXZDINX-NEXT: ret 1516; 1517; RV32I-LABEL: llround_f64: 1518; RV32I: # %bb.0: 1519; RV32I-NEXT: addi sp, sp, -16 1520; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1521; RV32I-NEXT: call llround 1522; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1523; RV32I-NEXT: addi sp, sp, 16 1524; RV32I-NEXT: ret 1525; 1526; RV64I-LABEL: llround_f64: 1527; RV64I: # %bb.0: 1528; RV64I-NEXT: addi sp, sp, -16 1529; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1530; RV64I-NEXT: call llround 1531; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1532; RV64I-NEXT: addi sp, sp, 16 1533; RV64I-NEXT: ret 1534 %1 = call i64 @llvm.llround.i64.f64(double %a) 1535 ret i64 %1 1536} 1537 1538declare i1 @llvm.is.fpclass.f64(double, i32) 1539define i1 @isnan_d_fpclass(double %x) { 1540; CHECKIFD-LABEL: isnan_d_fpclass: 1541; CHECKIFD: # %bb.0: 1542; CHECKIFD-NEXT: fclass.d a0, fa0 1543; CHECKIFD-NEXT: andi a0, a0, 768 1544; CHECKIFD-NEXT: snez a0, a0 1545; CHECKIFD-NEXT: ret 1546; 1547; RV32IZFINXZDINX-LABEL: isnan_d_fpclass: 1548; RV32IZFINXZDINX: # %bb.0: 1549; RV32IZFINXZDINX-NEXT: fclass.d a0, a0 1550; RV32IZFINXZDINX-NEXT: andi a0, a0, 768 1551; RV32IZFINXZDINX-NEXT: snez a0, a0 1552; RV32IZFINXZDINX-NEXT: ret 1553; 1554; RV64IZFINXZDINX-LABEL: isnan_d_fpclass: 1555; RV64IZFINXZDINX: # %bb.0: 1556; RV64IZFINXZDINX-NEXT: fclass.d a0, a0 1557; RV64IZFINXZDINX-NEXT: andi a0, a0, 768 1558; RV64IZFINXZDINX-NEXT: snez a0, a0 1559; RV64IZFINXZDINX-NEXT: ret 1560; 1561; RV32I-LABEL: isnan_d_fpclass: 1562; RV32I: # %bb.0: 1563; RV32I-NEXT: slli a1, a1, 1 1564; RV32I-NEXT: srli a1, a1, 1 1565; RV32I-NEXT: lui a2, 524032 1566; RV32I-NEXT: beq a1, a2, .LBB30_2 1567; RV32I-NEXT: # %bb.1: 1568; RV32I-NEXT: slt a0, a2, a1 1569; RV32I-NEXT: ret 1570; RV32I-NEXT: .LBB30_2: 1571; RV32I-NEXT: snez a0, a0 1572; RV32I-NEXT: ret 1573; 1574; RV64I-LABEL: isnan_d_fpclass: 1575; RV64I: # %bb.0: 1576; RV64I-NEXT: slli a0, a0, 1 1577; RV64I-NEXT: li a1, 2047 1578; RV64I-NEXT: srli a0, a0, 1 1579; RV64I-NEXT: slli a1, a1, 52 1580; RV64I-NEXT: slt a0, a1, a0 1581; RV64I-NEXT: ret 1582 %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan 1583 ret i1 %1 1584} 1585 1586define double @tan_f64(double %a) nounwind { 1587; CHECKIFD-LABEL: tan_f64: 1588; CHECKIFD: # %bb.0: 1589; CHECKIFD-NEXT: tail tan 1590; 1591; RV32IZFINXZDINX-LABEL: tan_f64: 1592; RV32IZFINXZDINX: # %bb.0: 1593; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1594; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1595; RV32IZFINXZDINX-NEXT: call tan 1596; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1597; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1598; RV32IZFINXZDINX-NEXT: ret 1599; 1600; RV64IZFINXZDINX-LABEL: tan_f64: 1601; RV64IZFINXZDINX: # %bb.0: 1602; RV64IZFINXZDINX-NEXT: tail tan 1603; 1604; RV32I-LABEL: tan_f64: 1605; RV32I: # %bb.0: 1606; RV32I-NEXT: addi sp, sp, -16 1607; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1608; RV32I-NEXT: call tan 1609; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1610; RV32I-NEXT: addi sp, sp, 16 1611; RV32I-NEXT: ret 1612; 1613; RV64I-LABEL: tan_f64: 1614; RV64I: # %bb.0: 1615; RV64I-NEXT: addi sp, sp, -16 1616; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1617; RV64I-NEXT: call tan 1618; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1619; RV64I-NEXT: addi sp, sp, 16 1620; RV64I-NEXT: ret 1621 %1 = call double @llvm.tan.f64(double %a) 1622 ret double %1 1623} 1624 1625declare double @llvm.maximumnum.f64(double, double) 1626 1627define double @maximumnum_double(double %x, double %y) { 1628; CHECKIFD-LABEL: maximumnum_double: 1629; CHECKIFD: # %bb.0: 1630; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1 1631; CHECKIFD-NEXT: ret 1632; 1633; RV32IZFINXZDINX-LABEL: maximumnum_double: 1634; RV32IZFINXZDINX: # %bb.0: 1635; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2 1636; RV32IZFINXZDINX-NEXT: ret 1637; 1638; RV64IZFINXZDINX-LABEL: maximumnum_double: 1639; RV64IZFINXZDINX: # %bb.0: 1640; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1 1641; RV64IZFINXZDINX-NEXT: ret 1642; 1643; RV32I-LABEL: maximumnum_double: 1644; RV32I: # %bb.0: 1645; RV32I-NEXT: addi sp, sp, -16 1646; RV32I-NEXT: .cfi_def_cfa_offset 16 1647; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1648; RV32I-NEXT: .cfi_offset ra, -4 1649; RV32I-NEXT: call fmaximum_num 1650; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1651; RV32I-NEXT: .cfi_restore ra 1652; RV32I-NEXT: addi sp, sp, 16 1653; RV32I-NEXT: .cfi_def_cfa_offset 0 1654; RV32I-NEXT: ret 1655; 1656; RV64I-LABEL: maximumnum_double: 1657; RV64I: # %bb.0: 1658; RV64I-NEXT: addi sp, sp, -16 1659; RV64I-NEXT: .cfi_def_cfa_offset 16 1660; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1661; RV64I-NEXT: .cfi_offset ra, -8 1662; RV64I-NEXT: call fmaximum_num 1663; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1664; RV64I-NEXT: .cfi_restore ra 1665; RV64I-NEXT: addi sp, sp, 16 1666; RV64I-NEXT: .cfi_def_cfa_offset 0 1667; RV64I-NEXT: ret 1668 %z = call double @llvm.maximumnum.f64(double %x, double %y) 1669 ret double %z 1670} 1671 1672declare double @llvm.minimumnum.f64(double, double) 1673 1674define double @minimumnum_double(double %x, double %y) { 1675; CHECKIFD-LABEL: minimumnum_double: 1676; CHECKIFD: # %bb.0: 1677; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1 1678; CHECKIFD-NEXT: ret 1679; 1680; RV32IZFINXZDINX-LABEL: minimumnum_double: 1681; RV32IZFINXZDINX: # %bb.0: 1682; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2 1683; RV32IZFINXZDINX-NEXT: ret 1684; 1685; RV64IZFINXZDINX-LABEL: minimumnum_double: 1686; RV64IZFINXZDINX: # %bb.0: 1687; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1 1688; RV64IZFINXZDINX-NEXT: ret 1689; 1690; RV32I-LABEL: minimumnum_double: 1691; RV32I: # %bb.0: 1692; RV32I-NEXT: addi sp, sp, -16 1693; RV32I-NEXT: .cfi_def_cfa_offset 16 1694; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1695; RV32I-NEXT: .cfi_offset ra, -4 1696; RV32I-NEXT: call fminimum_num 1697; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1698; RV32I-NEXT: .cfi_restore ra 1699; RV32I-NEXT: addi sp, sp, 16 1700; RV32I-NEXT: .cfi_def_cfa_offset 0 1701; RV32I-NEXT: ret 1702; 1703; RV64I-LABEL: minimumnum_double: 1704; RV64I: # %bb.0: 1705; RV64I-NEXT: addi sp, sp, -16 1706; RV64I-NEXT: .cfi_def_cfa_offset 16 1707; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1708; RV64I-NEXT: .cfi_offset ra, -8 1709; RV64I-NEXT: call fminimum_num 1710; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1711; RV64I-NEXT: .cfi_restore ra 1712; RV64I-NEXT: addi sp, sp, 16 1713; RV64I-NEXT: .cfi_def_cfa_offset 0 1714; RV64I-NEXT: ret 1715 %z = call double @llvm.minimumnum.f64(double %x, double %y) 1716 ret double %z 1717} 1718 1719define double @ldexp_double(double %x, i32 signext %y) nounwind { 1720; RV32IFD-LABEL: ldexp_double: 1721; RV32IFD: # %bb.0: 1722; RV32IFD-NEXT: tail ldexp 1723; 1724; RV64IFD-LABEL: ldexp_double: 1725; RV64IFD: # %bb.0: 1726; RV64IFD-NEXT: addi sp, sp, -16 1727; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1728; RV64IFD-NEXT: call ldexp 1729; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1730; RV64IFD-NEXT: addi sp, sp, 16 1731; RV64IFD-NEXT: ret 1732; 1733; RV32IZFINXZDINX-LABEL: ldexp_double: 1734; RV32IZFINXZDINX: # %bb.0: 1735; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1736; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1737; RV32IZFINXZDINX-NEXT: call ldexp 1738; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1739; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1740; RV32IZFINXZDINX-NEXT: ret 1741; 1742; RV64IZFINXZDINX-LABEL: ldexp_double: 1743; RV64IZFINXZDINX: # %bb.0: 1744; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 1745; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1746; RV64IZFINXZDINX-NEXT: call ldexp 1747; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1748; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 1749; RV64IZFINXZDINX-NEXT: ret 1750; 1751; RV32I-LABEL: ldexp_double: 1752; RV32I: # %bb.0: 1753; RV32I-NEXT: addi sp, sp, -16 1754; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1755; RV32I-NEXT: call ldexp 1756; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1757; RV32I-NEXT: addi sp, sp, 16 1758; RV32I-NEXT: ret 1759; 1760; RV64I-LABEL: ldexp_double: 1761; RV64I: # %bb.0: 1762; RV64I-NEXT: addi sp, sp, -16 1763; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1764; RV64I-NEXT: call ldexp 1765; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1766; RV64I-NEXT: addi sp, sp, 16 1767; RV64I-NEXT: ret 1768 %z = call double @llvm.ldexp.f64.i32(double %x, i32 %y) 1769 ret double %z 1770} 1771 1772define {double, i32} @frexp_double(double %x) nounwind { 1773; RV32IFD-LABEL: frexp_double: 1774; RV32IFD: # %bb.0: 1775; RV32IFD-NEXT: addi sp, sp, -16 1776; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1777; RV32IFD-NEXT: addi a0, sp, 8 1778; RV32IFD-NEXT: call frexp 1779; RV32IFD-NEXT: lw a0, 8(sp) 1780; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1781; RV32IFD-NEXT: addi sp, sp, 16 1782; RV32IFD-NEXT: ret 1783; 1784; RV64IFD-LABEL: frexp_double: 1785; RV64IFD: # %bb.0: 1786; RV64IFD-NEXT: addi sp, sp, -16 1787; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1788; RV64IFD-NEXT: mv a0, sp 1789; RV64IFD-NEXT: call frexp 1790; RV64IFD-NEXT: ld a0, 0(sp) 1791; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1792; RV64IFD-NEXT: addi sp, sp, 16 1793; RV64IFD-NEXT: ret 1794; 1795; RV32IZFINXZDINX-LABEL: frexp_double: 1796; RV32IZFINXZDINX: # %bb.0: 1797; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1798; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1799; RV32IZFINXZDINX-NEXT: addi a2, sp, 8 1800; RV32IZFINXZDINX-NEXT: call frexp 1801; RV32IZFINXZDINX-NEXT: lw a2, 8(sp) 1802; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1803; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1804; RV32IZFINXZDINX-NEXT: ret 1805; 1806; RV64IZFINXZDINX-LABEL: frexp_double: 1807; RV64IZFINXZDINX: # %bb.0: 1808; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 1809; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1810; RV64IZFINXZDINX-NEXT: mv a1, sp 1811; RV64IZFINXZDINX-NEXT: call frexp 1812; RV64IZFINXZDINX-NEXT: ld a1, 0(sp) 1813; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1814; RV64IZFINXZDINX-NEXT: addi sp, sp, 16 1815; RV64IZFINXZDINX-NEXT: ret 1816; 1817; RV32I-LABEL: frexp_double: 1818; RV32I: # %bb.0: 1819; RV32I-NEXT: addi sp, sp, -16 1820; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1821; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 1822; RV32I-NEXT: mv a3, a2 1823; RV32I-NEXT: mv s0, a0 1824; RV32I-NEXT: addi a2, sp, 4 1825; RV32I-NEXT: mv a0, a1 1826; RV32I-NEXT: mv a1, a3 1827; RV32I-NEXT: call frexp 1828; RV32I-NEXT: lw a2, 4(sp) 1829; RV32I-NEXT: sw a0, 0(s0) 1830; RV32I-NEXT: sw a1, 4(s0) 1831; RV32I-NEXT: sw a2, 8(s0) 1832; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1833; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 1834; RV32I-NEXT: addi sp, sp, 16 1835; RV32I-NEXT: ret 1836; 1837; RV64I-LABEL: frexp_double: 1838; RV64I: # %bb.0: 1839; RV64I-NEXT: addi sp, sp, -16 1840; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1841; RV64I-NEXT: addi a1, sp, 4 1842; RV64I-NEXT: call frexp 1843; RV64I-NEXT: lw a1, 4(sp) 1844; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1845; RV64I-NEXT: addi sp, sp, 16 1846; RV64I-NEXT: ret 1847 %a = call {double, i32} @llvm.frexp.f64.i32(double %x) 1848 ret {double, i32} %a 1849} 1850 1851define double @asin_f64(double %a) nounwind { 1852; CHECKIFD-LABEL: asin_f64: 1853; CHECKIFD: # %bb.0: 1854; CHECKIFD-NEXT: tail asin 1855; 1856; RV32IZFINXZDINX-LABEL: asin_f64: 1857; RV32IZFINXZDINX: # %bb.0: 1858; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1859; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1860; RV32IZFINXZDINX-NEXT: call asin 1861; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1862; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1863; RV32IZFINXZDINX-NEXT: ret 1864; 1865; RV64IZFINXZDINX-LABEL: asin_f64: 1866; RV64IZFINXZDINX: # %bb.0: 1867; RV64IZFINXZDINX-NEXT: tail asin 1868; 1869; RV32I-LABEL: asin_f64: 1870; RV32I: # %bb.0: 1871; RV32I-NEXT: addi sp, sp, -16 1872; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1873; RV32I-NEXT: call asin 1874; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1875; RV32I-NEXT: addi sp, sp, 16 1876; RV32I-NEXT: ret 1877; 1878; RV64I-LABEL: asin_f64: 1879; RV64I: # %bb.0: 1880; RV64I-NEXT: addi sp, sp, -16 1881; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1882; RV64I-NEXT: call asin 1883; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1884; RV64I-NEXT: addi sp, sp, 16 1885; RV64I-NEXT: ret 1886 %1 = call double @llvm.asin.f64(double %a) 1887 ret double %1 1888} 1889 1890define double @acos_f64(double %a) nounwind { 1891; CHECKIFD-LABEL: acos_f64: 1892; CHECKIFD: # %bb.0: 1893; CHECKIFD-NEXT: tail acos 1894; 1895; RV32IZFINXZDINX-LABEL: acos_f64: 1896; RV32IZFINXZDINX: # %bb.0: 1897; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1898; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1899; RV32IZFINXZDINX-NEXT: call acos 1900; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1901; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1902; RV32IZFINXZDINX-NEXT: ret 1903; 1904; RV64IZFINXZDINX-LABEL: acos_f64: 1905; RV64IZFINXZDINX: # %bb.0: 1906; RV64IZFINXZDINX-NEXT: tail acos 1907; 1908; RV32I-LABEL: acos_f64: 1909; RV32I: # %bb.0: 1910; RV32I-NEXT: addi sp, sp, -16 1911; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1912; RV32I-NEXT: call acos 1913; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1914; RV32I-NEXT: addi sp, sp, 16 1915; RV32I-NEXT: ret 1916; 1917; RV64I-LABEL: acos_f64: 1918; RV64I: # %bb.0: 1919; RV64I-NEXT: addi sp, sp, -16 1920; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1921; RV64I-NEXT: call acos 1922; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1923; RV64I-NEXT: addi sp, sp, 16 1924; RV64I-NEXT: ret 1925 %1 = call double @llvm.acos.f64(double %a) 1926 ret double %1 1927} 1928 1929define double @atan_f64(double %a) nounwind { 1930; CHECKIFD-LABEL: atan_f64: 1931; CHECKIFD: # %bb.0: 1932; CHECKIFD-NEXT: tail atan 1933; 1934; RV32IZFINXZDINX-LABEL: atan_f64: 1935; RV32IZFINXZDINX: # %bb.0: 1936; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1937; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1938; RV32IZFINXZDINX-NEXT: call atan 1939; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1940; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1941; RV32IZFINXZDINX-NEXT: ret 1942; 1943; RV64IZFINXZDINX-LABEL: atan_f64: 1944; RV64IZFINXZDINX: # %bb.0: 1945; RV64IZFINXZDINX-NEXT: tail atan 1946; 1947; RV32I-LABEL: atan_f64: 1948; RV32I: # %bb.0: 1949; RV32I-NEXT: addi sp, sp, -16 1950; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1951; RV32I-NEXT: call atan 1952; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1953; RV32I-NEXT: addi sp, sp, 16 1954; RV32I-NEXT: ret 1955; 1956; RV64I-LABEL: atan_f64: 1957; RV64I: # %bb.0: 1958; RV64I-NEXT: addi sp, sp, -16 1959; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1960; RV64I-NEXT: call atan 1961; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 1962; RV64I-NEXT: addi sp, sp, 16 1963; RV64I-NEXT: ret 1964 %1 = call double @llvm.atan.f64(double %a) 1965 ret double %1 1966} 1967 1968define double @atan2_f64(double %a, double %b) nounwind { 1969; CHECKIFD-LABEL: atan2_f64: 1970; CHECKIFD: # %bb.0: 1971; CHECKIFD-NEXT: tail atan2 1972; 1973; RV32IZFINXZDINX-LABEL: atan2_f64: 1974; RV32IZFINXZDINX: # %bb.0: 1975; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 1976; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1977; RV32IZFINXZDINX-NEXT: call atan2 1978; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1979; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 1980; RV32IZFINXZDINX-NEXT: ret 1981; 1982; RV64IZFINXZDINX-LABEL: atan2_f64: 1983; RV64IZFINXZDINX: # %bb.0: 1984; RV64IZFINXZDINX-NEXT: tail atan2 1985; 1986; RV32I-LABEL: atan2_f64: 1987; RV32I: # %bb.0: 1988; RV32I-NEXT: addi sp, sp, -16 1989; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 1990; RV32I-NEXT: call atan2 1991; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 1992; RV32I-NEXT: addi sp, sp, 16 1993; RV32I-NEXT: ret 1994; 1995; RV64I-LABEL: atan2_f64: 1996; RV64I: # %bb.0: 1997; RV64I-NEXT: addi sp, sp, -16 1998; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 1999; RV64I-NEXT: call atan2 2000; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2001; RV64I-NEXT: addi sp, sp, 16 2002; RV64I-NEXT: ret 2003 %1 = call double @llvm.atan2.f64(double %a, double %b) 2004 ret double %1 2005} 2006 2007define double @sinh_f64(double %a) nounwind { 2008; CHECKIFD-LABEL: sinh_f64: 2009; CHECKIFD: # %bb.0: 2010; CHECKIFD-NEXT: tail sinh 2011; 2012; RV32IZFINXZDINX-LABEL: sinh_f64: 2013; RV32IZFINXZDINX: # %bb.0: 2014; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 2015; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2016; RV32IZFINXZDINX-NEXT: call sinh 2017; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2018; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 2019; RV32IZFINXZDINX-NEXT: ret 2020; 2021; RV64IZFINXZDINX-LABEL: sinh_f64: 2022; RV64IZFINXZDINX: # %bb.0: 2023; RV64IZFINXZDINX-NEXT: tail sinh 2024; 2025; RV32I-LABEL: sinh_f64: 2026; RV32I: # %bb.0: 2027; RV32I-NEXT: addi sp, sp, -16 2028; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2029; RV32I-NEXT: call sinh 2030; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2031; RV32I-NEXT: addi sp, sp, 16 2032; RV32I-NEXT: ret 2033; 2034; RV64I-LABEL: sinh_f64: 2035; RV64I: # %bb.0: 2036; RV64I-NEXT: addi sp, sp, -16 2037; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2038; RV64I-NEXT: call sinh 2039; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2040; RV64I-NEXT: addi sp, sp, 16 2041; RV64I-NEXT: ret 2042 %1 = call double @llvm.sinh.f64(double %a) 2043 ret double %1 2044} 2045 2046define double @cosh_f64(double %a) nounwind { 2047; CHECKIFD-LABEL: cosh_f64: 2048; CHECKIFD: # %bb.0: 2049; CHECKIFD-NEXT: tail cosh 2050; 2051; RV32IZFINXZDINX-LABEL: cosh_f64: 2052; RV32IZFINXZDINX: # %bb.0: 2053; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 2054; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2055; RV32IZFINXZDINX-NEXT: call cosh 2056; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2057; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 2058; RV32IZFINXZDINX-NEXT: ret 2059; 2060; RV64IZFINXZDINX-LABEL: cosh_f64: 2061; RV64IZFINXZDINX: # %bb.0: 2062; RV64IZFINXZDINX-NEXT: tail cosh 2063; 2064; RV32I-LABEL: cosh_f64: 2065; RV32I: # %bb.0: 2066; RV32I-NEXT: addi sp, sp, -16 2067; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2068; RV32I-NEXT: call cosh 2069; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2070; RV32I-NEXT: addi sp, sp, 16 2071; RV32I-NEXT: ret 2072; 2073; RV64I-LABEL: cosh_f64: 2074; RV64I: # %bb.0: 2075; RV64I-NEXT: addi sp, sp, -16 2076; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2077; RV64I-NEXT: call cosh 2078; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2079; RV64I-NEXT: addi sp, sp, 16 2080; RV64I-NEXT: ret 2081 %1 = call double @llvm.cosh.f64(double %a) 2082 ret double %1 2083} 2084 2085define double @tanh_f64(double %a) nounwind { 2086; CHECKIFD-LABEL: tanh_f64: 2087; CHECKIFD: # %bb.0: 2088; CHECKIFD-NEXT: tail tanh 2089; 2090; RV32IZFINXZDINX-LABEL: tanh_f64: 2091; RV32IZFINXZDINX: # %bb.0: 2092; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 2093; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2094; RV32IZFINXZDINX-NEXT: call tanh 2095; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2096; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 2097; RV32IZFINXZDINX-NEXT: ret 2098; 2099; RV64IZFINXZDINX-LABEL: tanh_f64: 2100; RV64IZFINXZDINX: # %bb.0: 2101; RV64IZFINXZDINX-NEXT: tail tanh 2102; 2103; RV32I-LABEL: tanh_f64: 2104; RV32I: # %bb.0: 2105; RV32I-NEXT: addi sp, sp, -16 2106; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 2107; RV32I-NEXT: call tanh 2108; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 2109; RV32I-NEXT: addi sp, sp, 16 2110; RV32I-NEXT: ret 2111; 2112; RV64I-LABEL: tanh_f64: 2113; RV64I: # %bb.0: 2114; RV64I-NEXT: addi sp, sp, -16 2115; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 2116; RV64I-NEXT: call tanh 2117; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 2118; RV64I-NEXT: addi sp, sp, 16 2119; RV64I-NEXT: ret 2120 %1 = call double @llvm.tanh.f64(double %a) 2121 ret double %1 2122} 2123