1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ 3; RUN: -target-abi=ilp32d | FileCheck %s --check-prefix=CHECK32D 4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ 5; RUN: -target-abi=lp64d | FileCheck %s --check-prefix=CHECK64D 6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \ 7; RUN: -target-abi=ilp32 | FileCheck --check-prefix=CHECKRV32ZDINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \ 9; RUN: -target-abi=lp64 | FileCheck --check-prefix=CHECKRV64ZDINX %s 10 11define double @double_imm() nounwind { 12; CHECK32D-LABEL: double_imm: 13; CHECK32D: # %bb.0: 14; CHECK32D-NEXT: lui a0, %hi(.LCPI0_0) 15; CHECK32D-NEXT: fld fa0, %lo(.LCPI0_0)(a0) 16; CHECK32D-NEXT: ret 17; 18; CHECK64D-LABEL: double_imm: 19; CHECK64D: # %bb.0: 20; CHECK64D-NEXT: lui a0, %hi(.LCPI0_0) 21; CHECK64D-NEXT: fld fa0, %lo(.LCPI0_0)(a0) 22; CHECK64D-NEXT: ret 23; 24; CHECKRV32ZDINX-LABEL: double_imm: 25; CHECKRV32ZDINX: # %bb.0: 26; CHECKRV32ZDINX-NEXT: lui a0, 345155 27; CHECKRV32ZDINX-NEXT: lui a1, 262290 28; CHECKRV32ZDINX-NEXT: addi a0, a0, -744 29; CHECKRV32ZDINX-NEXT: addi a1, a1, 507 30; CHECKRV32ZDINX-NEXT: ret 31; 32; CHECKRV64ZDINX-LABEL: double_imm: 33; CHECKRV64ZDINX: # %bb.0: 34; CHECKRV64ZDINX-NEXT: lui a0, %hi(.LCPI0_0) 35; CHECKRV64ZDINX-NEXT: ld a0, %lo(.LCPI0_0)(a0) 36; CHECKRV64ZDINX-NEXT: ret 37 ret double 3.1415926535897931159979634685441851615905761718750 38} 39 40define double @double_imm_op(double %a) nounwind { 41; CHECK32D-LABEL: double_imm_op: 42; CHECK32D: # %bb.0: 43; CHECK32D-NEXT: lui a0, %hi(.LCPI1_0) 44; CHECK32D-NEXT: fld fa5, %lo(.LCPI1_0)(a0) 45; CHECK32D-NEXT: fadd.d fa0, fa0, fa5 46; CHECK32D-NEXT: ret 47; 48; CHECK64D-LABEL: double_imm_op: 49; CHECK64D: # %bb.0: 50; CHECK64D-NEXT: lui a0, %hi(.LCPI1_0) 51; CHECK64D-NEXT: fld fa5, %lo(.LCPI1_0)(a0) 52; CHECK64D-NEXT: fadd.d fa0, fa0, fa5 53; CHECK64D-NEXT: ret 54; 55; CHECKRV32ZDINX-LABEL: double_imm_op: 56; CHECKRV32ZDINX: # %bb.0: 57; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0) 58; CHECKRV32ZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2) 59; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) 60; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a2 61; CHECKRV32ZDINX-NEXT: ret 62; 63; CHECKRV64ZDINX-LABEL: double_imm_op: 64; CHECKRV64ZDINX: # %bb.0: 65; CHECKRV64ZDINX-NEXT: li a1, 1023 66; CHECKRV64ZDINX-NEXT: slli a1, a1, 52 67; CHECKRV64ZDINX-NEXT: fadd.d a0, a0, a1 68; CHECKRV64ZDINX-NEXT: ret 69 %1 = fadd double %a, 1.0 70 ret double %1 71} 72 73define double @double_positive_zero(ptr %pd) nounwind { 74; CHECK32D-LABEL: double_positive_zero: 75; CHECK32D: # %bb.0: 76; CHECK32D-NEXT: fcvt.d.w fa0, zero 77; CHECK32D-NEXT: ret 78; 79; CHECK64D-LABEL: double_positive_zero: 80; CHECK64D: # %bb.0: 81; CHECK64D-NEXT: fmv.d.x fa0, zero 82; CHECK64D-NEXT: ret 83; 84; CHECKRV32ZDINX-LABEL: double_positive_zero: 85; CHECKRV32ZDINX: # %bb.0: 86; CHECKRV32ZDINX-NEXT: li a0, 0 87; CHECKRV32ZDINX-NEXT: li a1, 0 88; CHECKRV32ZDINX-NEXT: ret 89; 90; CHECKRV64ZDINX-LABEL: double_positive_zero: 91; CHECKRV64ZDINX: # %bb.0: 92; CHECKRV64ZDINX-NEXT: li a0, 0 93; CHECKRV64ZDINX-NEXT: ret 94 ret double 0.0 95} 96 97define double @double_negative_zero(ptr %pd) nounwind { 98; CHECK32D-LABEL: double_negative_zero: 99; CHECK32D: # %bb.0: 100; CHECK32D-NEXT: fcvt.d.w fa5, zero 101; CHECK32D-NEXT: fneg.d fa0, fa5 102; CHECK32D-NEXT: ret 103; 104; CHECK64D-LABEL: double_negative_zero: 105; CHECK64D: # %bb.0: 106; CHECK64D-NEXT: fmv.d.x fa5, zero 107; CHECK64D-NEXT: fneg.d fa0, fa5 108; CHECK64D-NEXT: ret 109; 110; CHECKRV32ZDINX-LABEL: double_negative_zero: 111; CHECKRV32ZDINX: # %bb.0: 112; CHECKRV32ZDINX-NEXT: lui a1, 524288 113; CHECKRV32ZDINX-NEXT: li a0, 0 114; CHECKRV32ZDINX-NEXT: ret 115; 116; CHECKRV64ZDINX-LABEL: double_negative_zero: 117; CHECKRV64ZDINX: # %bb.0: 118; CHECKRV64ZDINX-NEXT: fneg.d a0, zero 119; CHECKRV64ZDINX-NEXT: ret 120 ret double -0.0 121} 122define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind { 123; CHECK32D-LABEL: negzero_sel: 124; CHECK32D: # %bb.0: # %entry 125; CHECK32D-NEXT: slli a0, a0, 16 126; CHECK32D-NEXT: fcvt.d.w fa5, zero 127; CHECK32D-NEXT: beqz a0, .LBB4_2 128; CHECK32D-NEXT: # %bb.1: # %entry 129; CHECK32D-NEXT: fneg.d fa0, fa5 130; CHECK32D-NEXT: .LBB4_2: # %entry 131; CHECK32D-NEXT: ret 132; 133; CHECK64D-LABEL: negzero_sel: 134; CHECK64D: # %bb.0: # %entry 135; CHECK64D-NEXT: slli a0, a0, 48 136; CHECK64D-NEXT: beqz a0, .LBB4_2 137; CHECK64D-NEXT: # %bb.1: # %entry 138; CHECK64D-NEXT: fmv.d.x fa5, zero 139; CHECK64D-NEXT: fneg.d fa0, fa5 140; CHECK64D-NEXT: .LBB4_2: # %entry 141; CHECK64D-NEXT: ret 142; 143; CHECKRV32ZDINX-LABEL: negzero_sel: 144; CHECKRV32ZDINX: # %bb.0: # %entry 145; CHECKRV32ZDINX-NEXT: slli a0, a0, 16 146; CHECKRV32ZDINX-NEXT: fcvt.d.w a4, zero 147; CHECKRV32ZDINX-NEXT: beqz a0, .LBB4_2 148; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry 149; CHECKRV32ZDINX-NEXT: fneg.d a2, a4 150; CHECKRV32ZDINX-NEXT: j .LBB4_3 151; CHECKRV32ZDINX-NEXT: .LBB4_2: 152; CHECKRV32ZDINX-NEXT: mv a3, a2 153; CHECKRV32ZDINX-NEXT: mv a2, a1 154; CHECKRV32ZDINX-NEXT: .LBB4_3: # %entry 155; CHECKRV32ZDINX-NEXT: mv a0, a2 156; CHECKRV32ZDINX-NEXT: mv a1, a3 157; CHECKRV32ZDINX-NEXT: ret 158; 159; CHECKRV64ZDINX-LABEL: negzero_sel: 160; CHECKRV64ZDINX: # %bb.0: # %entry 161; CHECKRV64ZDINX-NEXT: slli a2, a0, 48 162; CHECKRV64ZDINX-NEXT: mv a0, a1 163; CHECKRV64ZDINX-NEXT: beqz a2, .LBB4_2 164; CHECKRV64ZDINX-NEXT: # %bb.1: # %entry 165; CHECKRV64ZDINX-NEXT: fneg.d a0, zero 166; CHECKRV64ZDINX-NEXT: .LBB4_2: # %entry 167; CHECKRV64ZDINX-NEXT: ret 168entry: 169 %tobool.not = icmp eq i16 %a, 0 170 %d. = select i1 %tobool.not, double %d, double -0.000000e+00 171 ret double %d. 172} 173