1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ 3; RUN: -target-abi=ilp32d | FileCheck -check-prefix=CHECKIFD %s 4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ 5; RUN: -target-abi=lp64d | FileCheck -check-prefix=CHECKIFD %s 6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \ 7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINXZDINX,CHECKRV32IZFINXZDINX %s 8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \ 9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINXZDINX,CHECKRV64IZFINXZDINX %s 10; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 11; RUN: | FileCheck -check-prefix=RV32I %s 12; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 13; RUN: | FileCheck -check-prefix=RV64I %s 14 15define i32 @fcmp_false(double %a, double %b) nounwind { 16; CHECKIFD-LABEL: fcmp_false: 17; CHECKIFD: # %bb.0: 18; CHECKIFD-NEXT: li a0, 0 19; CHECKIFD-NEXT: ret 20; 21; CHECKIZFINXZDINX-LABEL: fcmp_false: 22; CHECKIZFINXZDINX: # %bb.0: 23; CHECKIZFINXZDINX-NEXT: li a0, 0 24; CHECKIZFINXZDINX-NEXT: ret 25; 26; RV32I-LABEL: fcmp_false: 27; RV32I: # %bb.0: 28; RV32I-NEXT: li a0, 0 29; RV32I-NEXT: ret 30; 31; RV64I-LABEL: fcmp_false: 32; RV64I: # %bb.0: 33; RV64I-NEXT: li a0, 0 34; RV64I-NEXT: ret 35 %1 = fcmp false double %a, %b 36 %2 = zext i1 %1 to i32 37 ret i32 %2 38} 39 40define i32 @fcmp_oeq(double %a, double %b) nounwind { 41; CHECKIFD-LABEL: fcmp_oeq: 42; CHECKIFD: # %bb.0: 43; CHECKIFD-NEXT: feq.d a0, fa0, fa1 44; CHECKIFD-NEXT: ret 45; 46; CHECKRV32IZFINXZDINX-LABEL: fcmp_oeq: 47; CHECKRV32IZFINXZDINX: # %bb.0: 48; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a2 49; CHECKRV32IZFINXZDINX-NEXT: ret 50; 51; CHECKRV64IZFINXZDINX-LABEL: fcmp_oeq: 52; CHECKRV64IZFINXZDINX: # %bb.0: 53; CHECKRV64IZFINXZDINX-NEXT: feq.d a0, a0, a1 54; CHECKRV64IZFINXZDINX-NEXT: ret 55; 56; RV32I-LABEL: fcmp_oeq: 57; RV32I: # %bb.0: 58; RV32I-NEXT: addi sp, sp, -16 59; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 60; RV32I-NEXT: call __eqdf2 61; RV32I-NEXT: seqz a0, a0 62; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 63; RV32I-NEXT: addi sp, sp, 16 64; RV32I-NEXT: ret 65; 66; RV64I-LABEL: fcmp_oeq: 67; RV64I: # %bb.0: 68; RV64I-NEXT: addi sp, sp, -16 69; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 70; RV64I-NEXT: call __eqdf2 71; RV64I-NEXT: seqz a0, a0 72; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 73; RV64I-NEXT: addi sp, sp, 16 74; RV64I-NEXT: ret 75 %1 = fcmp oeq double %a, %b 76 %2 = zext i1 %1 to i32 77 ret i32 %2 78} 79 80define i32 @fcmp_ogt(double %a, double %b) nounwind { 81; CHECKIFD-LABEL: fcmp_ogt: 82; CHECKIFD: # %bb.0: 83; CHECKIFD-NEXT: flt.d a0, fa1, fa0 84; CHECKIFD-NEXT: ret 85; 86; CHECKRV32IZFINXZDINX-LABEL: fcmp_ogt: 87; CHECKRV32IZFINXZDINX: # %bb.0: 88; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 89; CHECKRV32IZFINXZDINX-NEXT: ret 90; 91; CHECKRV64IZFINXZDINX-LABEL: fcmp_ogt: 92; CHECKRV64IZFINXZDINX: # %bb.0: 93; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 94; CHECKRV64IZFINXZDINX-NEXT: ret 95; 96; RV32I-LABEL: fcmp_ogt: 97; RV32I: # %bb.0: 98; RV32I-NEXT: addi sp, sp, -16 99; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 100; RV32I-NEXT: call __gtdf2 101; RV32I-NEXT: sgtz a0, a0 102; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 103; RV32I-NEXT: addi sp, sp, 16 104; RV32I-NEXT: ret 105; 106; RV64I-LABEL: fcmp_ogt: 107; RV64I: # %bb.0: 108; RV64I-NEXT: addi sp, sp, -16 109; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 110; RV64I-NEXT: call __gtdf2 111; RV64I-NEXT: sgtz a0, a0 112; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 113; RV64I-NEXT: addi sp, sp, 16 114; RV64I-NEXT: ret 115 %1 = fcmp ogt double %a, %b 116 %2 = zext i1 %1 to i32 117 ret i32 %2 118} 119 120define i32 @fcmp_oge(double %a, double %b) nounwind { 121; CHECKIFD-LABEL: fcmp_oge: 122; CHECKIFD: # %bb.0: 123; CHECKIFD-NEXT: fle.d a0, fa1, fa0 124; CHECKIFD-NEXT: ret 125; 126; CHECKRV32IZFINXZDINX-LABEL: fcmp_oge: 127; CHECKRV32IZFINXZDINX: # %bb.0: 128; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a2, a0 129; CHECKRV32IZFINXZDINX-NEXT: ret 130; 131; CHECKRV64IZFINXZDINX-LABEL: fcmp_oge: 132; CHECKRV64IZFINXZDINX: # %bb.0: 133; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a1, a0 134; CHECKRV64IZFINXZDINX-NEXT: ret 135; 136; RV32I-LABEL: fcmp_oge: 137; RV32I: # %bb.0: 138; RV32I-NEXT: addi sp, sp, -16 139; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 140; RV32I-NEXT: call __gedf2 141; RV32I-NEXT: slti a0, a0, 0 142; RV32I-NEXT: xori a0, a0, 1 143; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 144; RV32I-NEXT: addi sp, sp, 16 145; RV32I-NEXT: ret 146; 147; RV64I-LABEL: fcmp_oge: 148; RV64I: # %bb.0: 149; RV64I-NEXT: addi sp, sp, -16 150; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 151; RV64I-NEXT: call __gedf2 152; RV64I-NEXT: slti a0, a0, 0 153; RV64I-NEXT: xori a0, a0, 1 154; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 155; RV64I-NEXT: addi sp, sp, 16 156; RV64I-NEXT: ret 157 %1 = fcmp oge double %a, %b 158 %2 = zext i1 %1 to i32 159 ret i32 %2 160} 161 162define i32 @fcmp_olt(double %a, double %b) nounwind { 163; CHECKIFD-LABEL: fcmp_olt: 164; CHECKIFD: # %bb.0: 165; CHECKIFD-NEXT: flt.d a0, fa0, fa1 166; CHECKIFD-NEXT: ret 167; 168; CHECKRV32IZFINXZDINX-LABEL: fcmp_olt: 169; CHECKRV32IZFINXZDINX: # %bb.0: 170; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a0, a2 171; CHECKRV32IZFINXZDINX-NEXT: ret 172; 173; CHECKRV64IZFINXZDINX-LABEL: fcmp_olt: 174; CHECKRV64IZFINXZDINX: # %bb.0: 175; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a0, a1 176; CHECKRV64IZFINXZDINX-NEXT: ret 177; 178; RV32I-LABEL: fcmp_olt: 179; RV32I: # %bb.0: 180; RV32I-NEXT: addi sp, sp, -16 181; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 182; RV32I-NEXT: call __ltdf2 183; RV32I-NEXT: slti a0, a0, 0 184; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 185; RV32I-NEXT: addi sp, sp, 16 186; RV32I-NEXT: ret 187; 188; RV64I-LABEL: fcmp_olt: 189; RV64I: # %bb.0: 190; RV64I-NEXT: addi sp, sp, -16 191; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 192; RV64I-NEXT: call __ltdf2 193; RV64I-NEXT: slti a0, a0, 0 194; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 195; RV64I-NEXT: addi sp, sp, 16 196; RV64I-NEXT: ret 197 %1 = fcmp olt double %a, %b 198 %2 = zext i1 %1 to i32 199 ret i32 %2 200} 201 202define i32 @fcmp_ole(double %a, double %b) nounwind { 203; CHECKIFD-LABEL: fcmp_ole: 204; CHECKIFD: # %bb.0: 205; CHECKIFD-NEXT: fle.d a0, fa0, fa1 206; CHECKIFD-NEXT: ret 207; 208; CHECKRV32IZFINXZDINX-LABEL: fcmp_ole: 209; CHECKRV32IZFINXZDINX: # %bb.0: 210; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a0, a2 211; CHECKRV32IZFINXZDINX-NEXT: ret 212; 213; CHECKRV64IZFINXZDINX-LABEL: fcmp_ole: 214; CHECKRV64IZFINXZDINX: # %bb.0: 215; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a0, a1 216; CHECKRV64IZFINXZDINX-NEXT: ret 217; 218; RV32I-LABEL: fcmp_ole: 219; RV32I: # %bb.0: 220; RV32I-NEXT: addi sp, sp, -16 221; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 222; RV32I-NEXT: call __ledf2 223; RV32I-NEXT: slti a0, a0, 1 224; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 225; RV32I-NEXT: addi sp, sp, 16 226; RV32I-NEXT: ret 227; 228; RV64I-LABEL: fcmp_ole: 229; RV64I: # %bb.0: 230; RV64I-NEXT: addi sp, sp, -16 231; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 232; RV64I-NEXT: call __ledf2 233; RV64I-NEXT: slti a0, a0, 1 234; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 235; RV64I-NEXT: addi sp, sp, 16 236; RV64I-NEXT: ret 237 %1 = fcmp ole double %a, %b 238 %2 = zext i1 %1 to i32 239 ret i32 %2 240} 241 242define i32 @fcmp_one(double %a, double %b) nounwind { 243; CHECKIFD-LABEL: fcmp_one: 244; CHECKIFD: # %bb.0: 245; CHECKIFD-NEXT: flt.d a0, fa0, fa1 246; CHECKIFD-NEXT: flt.d a1, fa1, fa0 247; CHECKIFD-NEXT: or a0, a1, a0 248; CHECKIFD-NEXT: ret 249; 250; CHECKRV32IZFINXZDINX-LABEL: fcmp_one: 251; CHECKRV32IZFINXZDINX: # %bb.0: 252; CHECKRV32IZFINXZDINX-NEXT: flt.d a4, a0, a2 253; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 254; CHECKRV32IZFINXZDINX-NEXT: or a0, a0, a4 255; CHECKRV32IZFINXZDINX-NEXT: ret 256; 257; CHECKRV64IZFINXZDINX-LABEL: fcmp_one: 258; CHECKRV64IZFINXZDINX: # %bb.0: 259; CHECKRV64IZFINXZDINX-NEXT: flt.d a2, a0, a1 260; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 261; CHECKRV64IZFINXZDINX-NEXT: or a0, a0, a2 262; CHECKRV64IZFINXZDINX-NEXT: ret 263; 264; RV32I-LABEL: fcmp_one: 265; RV32I: # %bb.0: 266; RV32I-NEXT: addi sp, sp, -32 267; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 268; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 269; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 270; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 271; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 272; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill 273; RV32I-NEXT: mv s0, a3 274; RV32I-NEXT: mv s1, a2 275; RV32I-NEXT: mv s2, a1 276; RV32I-NEXT: mv s3, a0 277; RV32I-NEXT: call __eqdf2 278; RV32I-NEXT: snez s4, a0 279; RV32I-NEXT: mv a0, s3 280; RV32I-NEXT: mv a1, s2 281; RV32I-NEXT: mv a2, s1 282; RV32I-NEXT: mv a3, s0 283; RV32I-NEXT: call __unorddf2 284; RV32I-NEXT: seqz a0, a0 285; RV32I-NEXT: and a0, a0, s4 286; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 287; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 288; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 289; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 290; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 291; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload 292; RV32I-NEXT: addi sp, sp, 32 293; RV32I-NEXT: ret 294; 295; RV64I-LABEL: fcmp_one: 296; RV64I: # %bb.0: 297; RV64I-NEXT: addi sp, sp, -32 298; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 299; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 300; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 301; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 302; RV64I-NEXT: mv s0, a1 303; RV64I-NEXT: mv s1, a0 304; RV64I-NEXT: call __eqdf2 305; RV64I-NEXT: snez s2, a0 306; RV64I-NEXT: mv a0, s1 307; RV64I-NEXT: mv a1, s0 308; RV64I-NEXT: call __unorddf2 309; RV64I-NEXT: seqz a0, a0 310; RV64I-NEXT: and a0, a0, s2 311; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 312; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 313; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 314; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 315; RV64I-NEXT: addi sp, sp, 32 316; RV64I-NEXT: ret 317 %1 = fcmp one double %a, %b 318 %2 = zext i1 %1 to i32 319 ret i32 %2 320} 321 322define i32 @fcmp_ord(double %a, double %b) nounwind { 323; CHECKIFD-LABEL: fcmp_ord: 324; CHECKIFD: # %bb.0: 325; CHECKIFD-NEXT: feq.d a0, fa1, fa1 326; CHECKIFD-NEXT: feq.d a1, fa0, fa0 327; CHECKIFD-NEXT: and a0, a1, a0 328; CHECKIFD-NEXT: ret 329; 330; CHECKRV32IZFINXZDINX-LABEL: fcmp_ord: 331; CHECKRV32IZFINXZDINX: # %bb.0: 332; CHECKRV32IZFINXZDINX-NEXT: feq.d a2, a2, a2 333; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a0 334; CHECKRV32IZFINXZDINX-NEXT: and a0, a0, a2 335; CHECKRV32IZFINXZDINX-NEXT: ret 336; 337; CHECKRV64IZFINXZDINX-LABEL: fcmp_ord: 338; CHECKRV64IZFINXZDINX: # %bb.0: 339; CHECKRV64IZFINXZDINX-NEXT: feq.d a1, a1, a1 340; CHECKRV64IZFINXZDINX-NEXT: feq.d a0, a0, a0 341; CHECKRV64IZFINXZDINX-NEXT: and a0, a0, a1 342; CHECKRV64IZFINXZDINX-NEXT: ret 343; 344; RV32I-LABEL: fcmp_ord: 345; RV32I: # %bb.0: 346; RV32I-NEXT: addi sp, sp, -16 347; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 348; RV32I-NEXT: call __unorddf2 349; RV32I-NEXT: seqz a0, a0 350; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 351; RV32I-NEXT: addi sp, sp, 16 352; RV32I-NEXT: ret 353; 354; RV64I-LABEL: fcmp_ord: 355; RV64I: # %bb.0: 356; RV64I-NEXT: addi sp, sp, -16 357; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 358; RV64I-NEXT: call __unorddf2 359; RV64I-NEXT: seqz a0, a0 360; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 361; RV64I-NEXT: addi sp, sp, 16 362; RV64I-NEXT: ret 363 %1 = fcmp ord double %a, %b 364 %2 = zext i1 %1 to i32 365 ret i32 %2 366} 367 368define i32 @fcmp_ueq(double %a, double %b) nounwind { 369; CHECKIFD-LABEL: fcmp_ueq: 370; CHECKIFD: # %bb.0: 371; CHECKIFD-NEXT: flt.d a0, fa0, fa1 372; CHECKIFD-NEXT: flt.d a1, fa1, fa0 373; CHECKIFD-NEXT: or a0, a1, a0 374; CHECKIFD-NEXT: xori a0, a0, 1 375; CHECKIFD-NEXT: ret 376; 377; CHECKRV32IZFINXZDINX-LABEL: fcmp_ueq: 378; CHECKRV32IZFINXZDINX: # %bb.0: 379; CHECKRV32IZFINXZDINX-NEXT: flt.d a4, a0, a2 380; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 381; CHECKRV32IZFINXZDINX-NEXT: or a0, a0, a4 382; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 383; CHECKRV32IZFINXZDINX-NEXT: ret 384; 385; CHECKRV64IZFINXZDINX-LABEL: fcmp_ueq: 386; CHECKRV64IZFINXZDINX: # %bb.0: 387; CHECKRV64IZFINXZDINX-NEXT: flt.d a2, a0, a1 388; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 389; CHECKRV64IZFINXZDINX-NEXT: or a0, a0, a2 390; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 391; CHECKRV64IZFINXZDINX-NEXT: ret 392; 393; RV32I-LABEL: fcmp_ueq: 394; RV32I: # %bb.0: 395; RV32I-NEXT: addi sp, sp, -32 396; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill 397; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill 398; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill 399; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill 400; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill 401; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill 402; RV32I-NEXT: mv s0, a3 403; RV32I-NEXT: mv s1, a2 404; RV32I-NEXT: mv s2, a1 405; RV32I-NEXT: mv s3, a0 406; RV32I-NEXT: call __eqdf2 407; RV32I-NEXT: seqz s4, a0 408; RV32I-NEXT: mv a0, s3 409; RV32I-NEXT: mv a1, s2 410; RV32I-NEXT: mv a2, s1 411; RV32I-NEXT: mv a3, s0 412; RV32I-NEXT: call __unorddf2 413; RV32I-NEXT: snez a0, a0 414; RV32I-NEXT: or a0, a0, s4 415; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload 416; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload 417; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload 418; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload 419; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload 420; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload 421; RV32I-NEXT: addi sp, sp, 32 422; RV32I-NEXT: ret 423; 424; RV64I-LABEL: fcmp_ueq: 425; RV64I: # %bb.0: 426; RV64I-NEXT: addi sp, sp, -32 427; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 428; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 429; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 430; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 431; RV64I-NEXT: mv s0, a1 432; RV64I-NEXT: mv s1, a0 433; RV64I-NEXT: call __eqdf2 434; RV64I-NEXT: seqz s2, a0 435; RV64I-NEXT: mv a0, s1 436; RV64I-NEXT: mv a1, s0 437; RV64I-NEXT: call __unorddf2 438; RV64I-NEXT: snez a0, a0 439; RV64I-NEXT: or a0, a0, s2 440; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 441; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 442; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 443; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 444; RV64I-NEXT: addi sp, sp, 32 445; RV64I-NEXT: ret 446 %1 = fcmp ueq double %a, %b 447 %2 = zext i1 %1 to i32 448 ret i32 %2 449} 450 451define i32 @fcmp_ugt(double %a, double %b) nounwind { 452; CHECKIFD-LABEL: fcmp_ugt: 453; CHECKIFD: # %bb.0: 454; CHECKIFD-NEXT: fle.d a0, fa0, fa1 455; CHECKIFD-NEXT: xori a0, a0, 1 456; CHECKIFD-NEXT: ret 457; 458; CHECKRV32IZFINXZDINX-LABEL: fcmp_ugt: 459; CHECKRV32IZFINXZDINX: # %bb.0: 460; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a0, a2 461; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 462; CHECKRV32IZFINXZDINX-NEXT: ret 463; 464; CHECKRV64IZFINXZDINX-LABEL: fcmp_ugt: 465; CHECKRV64IZFINXZDINX: # %bb.0: 466; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a0, a1 467; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 468; CHECKRV64IZFINXZDINX-NEXT: ret 469; 470; RV32I-LABEL: fcmp_ugt: 471; RV32I: # %bb.0: 472; RV32I-NEXT: addi sp, sp, -16 473; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 474; RV32I-NEXT: call __ledf2 475; RV32I-NEXT: sgtz a0, a0 476; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 477; RV32I-NEXT: addi sp, sp, 16 478; RV32I-NEXT: ret 479; 480; RV64I-LABEL: fcmp_ugt: 481; RV64I: # %bb.0: 482; RV64I-NEXT: addi sp, sp, -16 483; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 484; RV64I-NEXT: call __ledf2 485; RV64I-NEXT: sgtz a0, a0 486; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 487; RV64I-NEXT: addi sp, sp, 16 488; RV64I-NEXT: ret 489 %1 = fcmp ugt double %a, %b 490 %2 = zext i1 %1 to i32 491 ret i32 %2 492} 493 494define i32 @fcmp_uge(double %a, double %b) nounwind { 495; CHECKIFD-LABEL: fcmp_uge: 496; CHECKIFD: # %bb.0: 497; CHECKIFD-NEXT: flt.d a0, fa0, fa1 498; CHECKIFD-NEXT: xori a0, a0, 1 499; CHECKIFD-NEXT: ret 500; 501; CHECKRV32IZFINXZDINX-LABEL: fcmp_uge: 502; CHECKRV32IZFINXZDINX: # %bb.0: 503; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a0, a2 504; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 505; CHECKRV32IZFINXZDINX-NEXT: ret 506; 507; CHECKRV64IZFINXZDINX-LABEL: fcmp_uge: 508; CHECKRV64IZFINXZDINX: # %bb.0: 509; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a0, a1 510; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 511; CHECKRV64IZFINXZDINX-NEXT: ret 512; 513; RV32I-LABEL: fcmp_uge: 514; RV32I: # %bb.0: 515; RV32I-NEXT: addi sp, sp, -16 516; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 517; RV32I-NEXT: call __ltdf2 518; RV32I-NEXT: slti a0, a0, 0 519; RV32I-NEXT: xori a0, a0, 1 520; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 521; RV32I-NEXT: addi sp, sp, 16 522; RV32I-NEXT: ret 523; 524; RV64I-LABEL: fcmp_uge: 525; RV64I: # %bb.0: 526; RV64I-NEXT: addi sp, sp, -16 527; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 528; RV64I-NEXT: call __ltdf2 529; RV64I-NEXT: slti a0, a0, 0 530; RV64I-NEXT: xori a0, a0, 1 531; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 532; RV64I-NEXT: addi sp, sp, 16 533; RV64I-NEXT: ret 534 %1 = fcmp uge double %a, %b 535 %2 = zext i1 %1 to i32 536 ret i32 %2 537} 538 539define i32 @fcmp_ult(double %a, double %b) nounwind { 540; CHECKIFD-LABEL: fcmp_ult: 541; CHECKIFD: # %bb.0: 542; CHECKIFD-NEXT: fle.d a0, fa1, fa0 543; CHECKIFD-NEXT: xori a0, a0, 1 544; CHECKIFD-NEXT: ret 545; 546; CHECKRV32IZFINXZDINX-LABEL: fcmp_ult: 547; CHECKRV32IZFINXZDINX: # %bb.0: 548; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a2, a0 549; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 550; CHECKRV32IZFINXZDINX-NEXT: ret 551; 552; CHECKRV64IZFINXZDINX-LABEL: fcmp_ult: 553; CHECKRV64IZFINXZDINX: # %bb.0: 554; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a1, a0 555; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 556; CHECKRV64IZFINXZDINX-NEXT: ret 557; 558; RV32I-LABEL: fcmp_ult: 559; RV32I: # %bb.0: 560; RV32I-NEXT: addi sp, sp, -16 561; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 562; RV32I-NEXT: call __gedf2 563; RV32I-NEXT: slti a0, a0, 0 564; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 565; RV32I-NEXT: addi sp, sp, 16 566; RV32I-NEXT: ret 567; 568; RV64I-LABEL: fcmp_ult: 569; RV64I: # %bb.0: 570; RV64I-NEXT: addi sp, sp, -16 571; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 572; RV64I-NEXT: call __gedf2 573; RV64I-NEXT: slti a0, a0, 0 574; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 575; RV64I-NEXT: addi sp, sp, 16 576; RV64I-NEXT: ret 577 %1 = fcmp ult double %a, %b 578 %2 = zext i1 %1 to i32 579 ret i32 %2 580} 581 582define i32 @fcmp_ule(double %a, double %b) nounwind { 583; CHECKIFD-LABEL: fcmp_ule: 584; CHECKIFD: # %bb.0: 585; CHECKIFD-NEXT: flt.d a0, fa1, fa0 586; CHECKIFD-NEXT: xori a0, a0, 1 587; CHECKIFD-NEXT: ret 588; 589; CHECKRV32IZFINXZDINX-LABEL: fcmp_ule: 590; CHECKRV32IZFINXZDINX: # %bb.0: 591; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 592; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 593; CHECKRV32IZFINXZDINX-NEXT: ret 594; 595; CHECKRV64IZFINXZDINX-LABEL: fcmp_ule: 596; CHECKRV64IZFINXZDINX: # %bb.0: 597; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 598; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 599; CHECKRV64IZFINXZDINX-NEXT: ret 600; 601; RV32I-LABEL: fcmp_ule: 602; RV32I: # %bb.0: 603; RV32I-NEXT: addi sp, sp, -16 604; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 605; RV32I-NEXT: call __gtdf2 606; RV32I-NEXT: slti a0, a0, 1 607; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 608; RV32I-NEXT: addi sp, sp, 16 609; RV32I-NEXT: ret 610; 611; RV64I-LABEL: fcmp_ule: 612; RV64I: # %bb.0: 613; RV64I-NEXT: addi sp, sp, -16 614; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 615; RV64I-NEXT: call __gtdf2 616; RV64I-NEXT: slti a0, a0, 1 617; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 618; RV64I-NEXT: addi sp, sp, 16 619; RV64I-NEXT: ret 620 %1 = fcmp ule double %a, %b 621 %2 = zext i1 %1 to i32 622 ret i32 %2 623} 624 625define i32 @fcmp_une(double %a, double %b) nounwind { 626; CHECKIFD-LABEL: fcmp_une: 627; CHECKIFD: # %bb.0: 628; CHECKIFD-NEXT: feq.d a0, fa0, fa1 629; CHECKIFD-NEXT: xori a0, a0, 1 630; CHECKIFD-NEXT: ret 631; 632; CHECKRV32IZFINXZDINX-LABEL: fcmp_une: 633; CHECKRV32IZFINXZDINX: # %bb.0: 634; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a2 635; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 636; CHECKRV32IZFINXZDINX-NEXT: ret 637; 638; CHECKRV64IZFINXZDINX-LABEL: fcmp_une: 639; CHECKRV64IZFINXZDINX: # %bb.0: 640; CHECKRV64IZFINXZDINX-NEXT: feq.d a0, a0, a1 641; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 642; CHECKRV64IZFINXZDINX-NEXT: ret 643; 644; RV32I-LABEL: fcmp_une: 645; RV32I: # %bb.0: 646; RV32I-NEXT: addi sp, sp, -16 647; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 648; RV32I-NEXT: call __nedf2 649; RV32I-NEXT: snez a0, a0 650; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 651; RV32I-NEXT: addi sp, sp, 16 652; RV32I-NEXT: ret 653; 654; RV64I-LABEL: fcmp_une: 655; RV64I: # %bb.0: 656; RV64I-NEXT: addi sp, sp, -16 657; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 658; RV64I-NEXT: call __nedf2 659; RV64I-NEXT: snez a0, a0 660; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 661; RV64I-NEXT: addi sp, sp, 16 662; RV64I-NEXT: ret 663 %1 = fcmp une double %a, %b 664 %2 = zext i1 %1 to i32 665 ret i32 %2 666} 667 668define i32 @fcmp_uno(double %a, double %b) nounwind { 669; CHECKIFD-LABEL: fcmp_uno: 670; CHECKIFD: # %bb.0: 671; CHECKIFD-NEXT: feq.d a0, fa1, fa1 672; CHECKIFD-NEXT: feq.d a1, fa0, fa0 673; CHECKIFD-NEXT: and a0, a1, a0 674; CHECKIFD-NEXT: xori a0, a0, 1 675; CHECKIFD-NEXT: ret 676; 677; CHECKRV32IZFINXZDINX-LABEL: fcmp_uno: 678; CHECKRV32IZFINXZDINX: # %bb.0: 679; CHECKRV32IZFINXZDINX-NEXT: feq.d a2, a2, a2 680; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a0 681; CHECKRV32IZFINXZDINX-NEXT: and a0, a0, a2 682; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 683; CHECKRV32IZFINXZDINX-NEXT: ret 684; 685; CHECKRV64IZFINXZDINX-LABEL: fcmp_uno: 686; CHECKRV64IZFINXZDINX: # %bb.0: 687; CHECKRV64IZFINXZDINX-NEXT: feq.d a1, a1, a1 688; CHECKRV64IZFINXZDINX-NEXT: feq.d a0, a0, a0 689; CHECKRV64IZFINXZDINX-NEXT: and a0, a0, a1 690; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 691; CHECKRV64IZFINXZDINX-NEXT: ret 692; 693; RV32I-LABEL: fcmp_uno: 694; RV32I: # %bb.0: 695; RV32I-NEXT: addi sp, sp, -16 696; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 697; RV32I-NEXT: call __unorddf2 698; RV32I-NEXT: snez a0, a0 699; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 700; RV32I-NEXT: addi sp, sp, 16 701; RV32I-NEXT: ret 702; 703; RV64I-LABEL: fcmp_uno: 704; RV64I: # %bb.0: 705; RV64I-NEXT: addi sp, sp, -16 706; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 707; RV64I-NEXT: call __unorddf2 708; RV64I-NEXT: snez a0, a0 709; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 710; RV64I-NEXT: addi sp, sp, 16 711; RV64I-NEXT: ret 712 %1 = fcmp uno double %a, %b 713 %2 = zext i1 %1 to i32 714 ret i32 %2 715} 716 717define i32 @fcmp_true(double %a, double %b) nounwind { 718; CHECKIFD-LABEL: fcmp_true: 719; CHECKIFD: # %bb.0: 720; CHECKIFD-NEXT: li a0, 1 721; CHECKIFD-NEXT: ret 722; 723; CHECKIZFINXZDINX-LABEL: fcmp_true: 724; CHECKIZFINXZDINX: # %bb.0: 725; CHECKIZFINXZDINX-NEXT: li a0, 1 726; CHECKIZFINXZDINX-NEXT: ret 727; 728; RV32I-LABEL: fcmp_true: 729; RV32I: # %bb.0: 730; RV32I-NEXT: li a0, 1 731; RV32I-NEXT: ret 732; 733; RV64I-LABEL: fcmp_true: 734; RV64I: # %bb.0: 735; RV64I-NEXT: li a0, 1 736; RV64I-NEXT: ret 737 %1 = fcmp true double %a, %b 738 %2 = zext i1 %1 to i32 739 ret i32 %2 740} 741