1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefixes=RV32IM %s 4; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefixes=RV64IM %s 6 7define i32 @testsize1(i32 %x) minsize nounwind { 8; RV32IM-LABEL: testsize1: 9; RV32IM: # %bb.0: # %entry 10; RV32IM-NEXT: li a1, 32 11; RV32IM-NEXT: div a0, a0, a1 12; RV32IM-NEXT: ret 13; 14; RV64IM-LABEL: testsize1: 15; RV64IM: # %bb.0: # %entry 16; RV64IM-NEXT: li a1, 32 17; RV64IM-NEXT: divw a0, a0, a1 18; RV64IM-NEXT: ret 19entry: 20 %div = sdiv i32 %x, 32 21 ret i32 %div 22} 23 24define i32 @testsize2(i32 %x) minsize nounwind { 25; RV32IM-LABEL: testsize2: 26; RV32IM: # %bb.0: # %entry 27; RV32IM-NEXT: li a1, 33 28; RV32IM-NEXT: div a0, a0, a1 29; RV32IM-NEXT: ret 30; 31; RV64IM-LABEL: testsize2: 32; RV64IM: # %bb.0: # %entry 33; RV64IM-NEXT: li a1, 33 34; RV64IM-NEXT: divw a0, a0, a1 35; RV64IM-NEXT: ret 36entry: 37 %div = sdiv i32 %x, 33 38 ret i32 %div 39} 40 41define i32 @testsize3(i32 %x) minsize nounwind { 42; RV32IM-LABEL: testsize3: 43; RV32IM: # %bb.0: # %entry 44; RV32IM-NEXT: srli a0, a0, 5 45; RV32IM-NEXT: ret 46; 47; RV64IM-LABEL: testsize3: 48; RV64IM: # %bb.0: # %entry 49; RV64IM-NEXT: srliw a0, a0, 5 50; RV64IM-NEXT: ret 51entry: 52 %div = udiv i32 %x, 32 53 ret i32 %div 54} 55 56define i32 @testsize4(i32 %x) minsize nounwind { 57; RV32IM-LABEL: testsize4: 58; RV32IM: # %bb.0: 59; RV32IM-NEXT: li a1, 33 60; RV32IM-NEXT: divu a0, a0, a1 61; RV32IM-NEXT: ret 62; 63; RV64IM-LABEL: testsize4: 64; RV64IM: # %bb.0: 65; RV64IM-NEXT: li a1, 33 66; RV64IM-NEXT: divuw a0, a0, a1 67; RV64IM-NEXT: ret 68 %div = udiv i32 %x, 33 69 ret i32 %div 70} 71