xref: /llvm-project/llvm/test/CodeGen/RISCV/div-by-constant.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefixes=RV32,RV32IM %s
4; RUN: llc -mtriple=riscv32 -mattr=+m,+zba,+zbb \
5; RUN:    -verify-machineinstrs < %s \
6; RUN:   | FileCheck -check-prefixes=RV32,RV32IMZB %s
7; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
8; RUN:   | FileCheck -check-prefixes=RV64,RV64IM %s
9; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb \
10; RUN:   -verify-machineinstrs < %s \
11; RUN:   | FileCheck -check-prefixes=RV64,RV64IMZB %s
12
13; Test that there is a single shift after the mul and no addition.
14define i32 @udiv_constant_no_add(i32 %a) nounwind {
15; RV32-LABEL: udiv_constant_no_add:
16; RV32:       # %bb.0:
17; RV32-NEXT:    lui a1, 838861
18; RV32-NEXT:    addi a1, a1, -819
19; RV32-NEXT:    mulhu a0, a0, a1
20; RV32-NEXT:    srli a0, a0, 2
21; RV32-NEXT:    ret
22;
23; RV64-LABEL: udiv_constant_no_add:
24; RV64:       # %bb.0:
25; RV64-NEXT:    slli a0, a0, 32
26; RV64-NEXT:    lui a1, 838861
27; RV64-NEXT:    addi a1, a1, -819
28; RV64-NEXT:    slli a1, a1, 32
29; RV64-NEXT:    mulhu a0, a0, a1
30; RV64-NEXT:    srli a0, a0, 34
31; RV64-NEXT:    ret
32  %1 = udiv i32 %a, 5
33  ret i32 %1
34}
35
36; This constant requires a sub, shrli, add sequence after the mul.
37define i32 @udiv_constant_add(i32 %a) nounwind {
38; RV32-LABEL: udiv_constant_add:
39; RV32:       # %bb.0:
40; RV32-NEXT:    lui a1, 149797
41; RV32-NEXT:    addi a1, a1, -1755
42; RV32-NEXT:    mulhu a1, a0, a1
43; RV32-NEXT:    sub a0, a0, a1
44; RV32-NEXT:    srli a0, a0, 1
45; RV32-NEXT:    add a0, a0, a1
46; RV32-NEXT:    srli a0, a0, 2
47; RV32-NEXT:    ret
48;
49; RV64IM-LABEL: udiv_constant_add:
50; RV64IM:       # %bb.0:
51; RV64IM-NEXT:    slli a1, a0, 32
52; RV64IM-NEXT:    lui a2, 149797
53; RV64IM-NEXT:    addi a2, a2, -1755
54; RV64IM-NEXT:    slli a2, a2, 32
55; RV64IM-NEXT:    mulhu a1, a1, a2
56; RV64IM-NEXT:    srli a1, a1, 32
57; RV64IM-NEXT:    subw a0, a0, a1
58; RV64IM-NEXT:    srliw a0, a0, 1
59; RV64IM-NEXT:    add a0, a0, a1
60; RV64IM-NEXT:    srli a0, a0, 2
61; RV64IM-NEXT:    ret
62;
63; RV64IMZB-LABEL: udiv_constant_add:
64; RV64IMZB:       # %bb.0:
65; RV64IMZB-NEXT:    zext.w a1, a0
66; RV64IMZB-NEXT:    lui a2, 149797
67; RV64IMZB-NEXT:    addiw a2, a2, -1755
68; RV64IMZB-NEXT:    mul a1, a1, a2
69; RV64IMZB-NEXT:    srli a1, a1, 32
70; RV64IMZB-NEXT:    subw a0, a0, a1
71; RV64IMZB-NEXT:    srliw a0, a0, 1
72; RV64IMZB-NEXT:    add a0, a0, a1
73; RV64IMZB-NEXT:    srli a0, a0, 2
74; RV64IMZB-NEXT:    ret
75  %1 = udiv i32 %a, 7
76  ret i32 %1
77}
78
79define i64 @udiv64_constant_no_add(i64 %a) nounwind {
80; RV32-LABEL: udiv64_constant_no_add:
81; RV32:       # %bb.0:
82; RV32-NEXT:    add a2, a0, a1
83; RV32-NEXT:    lui a3, 838861
84; RV32-NEXT:    sltu a4, a2, a0
85; RV32-NEXT:    addi a5, a3, -819
86; RV32-NEXT:    addi a3, a3, -820
87; RV32-NEXT:    add a2, a2, a4
88; RV32-NEXT:    mulhu a4, a2, a5
89; RV32-NEXT:    srli a6, a4, 2
90; RV32-NEXT:    andi a4, a4, -4
91; RV32-NEXT:    add a4, a4, a6
92; RV32-NEXT:    sub a2, a2, a4
93; RV32-NEXT:    sub a4, a0, a2
94; RV32-NEXT:    sltu a0, a0, a2
95; RV32-NEXT:    mul a2, a4, a3
96; RV32-NEXT:    mulhu a3, a4, a5
97; RV32-NEXT:    sub a1, a1, a0
98; RV32-NEXT:    add a2, a3, a2
99; RV32-NEXT:    mul a1, a1, a5
100; RV32-NEXT:    add a1, a2, a1
101; RV32-NEXT:    mul a0, a4, a5
102; RV32-NEXT:    ret
103;
104; RV64-LABEL: udiv64_constant_no_add:
105; RV64:       # %bb.0:
106; RV64-NEXT:    lui a1, 838861
107; RV64-NEXT:    addiw a1, a1, -819
108; RV64-NEXT:    slli a2, a1, 32
109; RV64-NEXT:    add a1, a1, a2
110; RV64-NEXT:    mulhu a0, a0, a1
111; RV64-NEXT:    srli a0, a0, 2
112; RV64-NEXT:    ret
113  %1 = udiv i64 %a, 5
114  ret i64 %1
115}
116
117define i64 @udiv64_constant_add(i64 %a) nounwind {
118; RV32-LABEL: udiv64_constant_add:
119; RV32:       # %bb.0:
120; RV32-NEXT:    addi sp, sp, -16
121; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
122; RV32-NEXT:    li a2, 7
123; RV32-NEXT:    li a3, 0
124; RV32-NEXT:    call __udivdi3
125; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
126; RV32-NEXT:    addi sp, sp, 16
127; RV32-NEXT:    ret
128;
129; RV64-LABEL: udiv64_constant_add:
130; RV64:       # %bb.0:
131; RV64-NEXT:    lui a1, %hi(.LCPI3_0)
132; RV64-NEXT:    ld a1, %lo(.LCPI3_0)(a1)
133; RV64-NEXT:    mulhu a1, a0, a1
134; RV64-NEXT:    sub a0, a0, a1
135; RV64-NEXT:    srli a0, a0, 1
136; RV64-NEXT:    add a0, a0, a1
137; RV64-NEXT:    srli a0, a0, 2
138; RV64-NEXT:    ret
139  %1 = udiv i64 %a, 7
140  ret i64 %1
141}
142
143define i8 @udiv8_constant_no_add(i8 %a) nounwind {
144; RV32-LABEL: udiv8_constant_no_add:
145; RV32:       # %bb.0:
146; RV32-NEXT:    andi a0, a0, 255
147; RV32-NEXT:    li a1, 205
148; RV32-NEXT:    mul a0, a0, a1
149; RV32-NEXT:    srli a0, a0, 10
150; RV32-NEXT:    ret
151;
152; RV64-LABEL: udiv8_constant_no_add:
153; RV64:       # %bb.0:
154; RV64-NEXT:    andi a0, a0, 255
155; RV64-NEXT:    li a1, 205
156; RV64-NEXT:    mul a0, a0, a1
157; RV64-NEXT:    srli a0, a0, 10
158; RV64-NEXT:    ret
159  %1 = udiv i8 %a, 5
160  ret i8 %1
161}
162
163define i8 @udiv8_constant_add(i8 %a) nounwind {
164; RV32IM-LABEL: udiv8_constant_add:
165; RV32IM:       # %bb.0:
166; RV32IM-NEXT:    andi a1, a0, 255
167; RV32IM-NEXT:    li a2, 37
168; RV32IM-NEXT:    mul a1, a1, a2
169; RV32IM-NEXT:    srli a1, a1, 8
170; RV32IM-NEXT:    sub a0, a0, a1
171; RV32IM-NEXT:    slli a0, a0, 24
172; RV32IM-NEXT:    srli a0, a0, 25
173; RV32IM-NEXT:    add a0, a0, a1
174; RV32IM-NEXT:    srli a0, a0, 2
175; RV32IM-NEXT:    ret
176;
177; RV32IMZB-LABEL: udiv8_constant_add:
178; RV32IMZB:       # %bb.0:
179; RV32IMZB-NEXT:    andi a1, a0, 255
180; RV32IMZB-NEXT:    sh3add a2, a1, a1
181; RV32IMZB-NEXT:    sh2add a1, a2, a1
182; RV32IMZB-NEXT:    srli a1, a1, 8
183; RV32IMZB-NEXT:    sub a0, a0, a1
184; RV32IMZB-NEXT:    slli a0, a0, 24
185; RV32IMZB-NEXT:    srli a0, a0, 25
186; RV32IMZB-NEXT:    add a0, a0, a1
187; RV32IMZB-NEXT:    srli a0, a0, 2
188; RV32IMZB-NEXT:    ret
189;
190; RV64IM-LABEL: udiv8_constant_add:
191; RV64IM:       # %bb.0:
192; RV64IM-NEXT:    andi a1, a0, 255
193; RV64IM-NEXT:    li a2, 37
194; RV64IM-NEXT:    mul a1, a1, a2
195; RV64IM-NEXT:    srli a1, a1, 8
196; RV64IM-NEXT:    subw a0, a0, a1
197; RV64IM-NEXT:    slli a0, a0, 56
198; RV64IM-NEXT:    srli a0, a0, 57
199; RV64IM-NEXT:    add a0, a0, a1
200; RV64IM-NEXT:    srli a0, a0, 2
201; RV64IM-NEXT:    ret
202;
203; RV64IMZB-LABEL: udiv8_constant_add:
204; RV64IMZB:       # %bb.0:
205; RV64IMZB-NEXT:    andi a1, a0, 255
206; RV64IMZB-NEXT:    sh3add a2, a1, a1
207; RV64IMZB-NEXT:    sh2add a1, a2, a1
208; RV64IMZB-NEXT:    srli a1, a1, 8
209; RV64IMZB-NEXT:    subw a0, a0, a1
210; RV64IMZB-NEXT:    slli a0, a0, 56
211; RV64IMZB-NEXT:    srli a0, a0, 57
212; RV64IMZB-NEXT:    add a0, a0, a1
213; RV64IMZB-NEXT:    srli a0, a0, 2
214; RV64IMZB-NEXT:    ret
215  %1 = udiv i8 %a, 7
216  ret i8 %1
217}
218
219define i16 @udiv16_constant_no_add(i16 %a) nounwind {
220; RV32-LABEL: udiv16_constant_no_add:
221; RV32:       # %bb.0:
222; RV32-NEXT:    slli a0, a0, 16
223; RV32-NEXT:    lui a1, 838864
224; RV32-NEXT:    mulhu a0, a0, a1
225; RV32-NEXT:    srli a0, a0, 18
226; RV32-NEXT:    ret
227;
228; RV64-LABEL: udiv16_constant_no_add:
229; RV64:       # %bb.0:
230; RV64-NEXT:    lui a1, 52429
231; RV64-NEXT:    slli a1, a1, 4
232; RV64-NEXT:    slli a0, a0, 48
233; RV64-NEXT:    mulhu a0, a0, a1
234; RV64-NEXT:    srli a0, a0, 18
235; RV64-NEXT:    ret
236  %1 = udiv i16 %a, 5
237  ret i16 %1
238}
239
240define i16 @udiv16_constant_add(i16 %a) nounwind {
241; RV32-LABEL: udiv16_constant_add:
242; RV32:       # %bb.0:
243; RV32-NEXT:    slli a1, a0, 16
244; RV32-NEXT:    lui a2, 149808
245; RV32-NEXT:    mulhu a1, a1, a2
246; RV32-NEXT:    srli a1, a1, 16
247; RV32-NEXT:    sub a0, a0, a1
248; RV32-NEXT:    slli a0, a0, 16
249; RV32-NEXT:    srli a0, a0, 17
250; RV32-NEXT:    add a0, a0, a1
251; RV32-NEXT:    srli a0, a0, 2
252; RV32-NEXT:    ret
253;
254; RV64-LABEL: udiv16_constant_add:
255; RV64:       # %bb.0:
256; RV64-NEXT:    slli a1, a0, 48
257; RV64-NEXT:    lui a2, 149808
258; RV64-NEXT:    mulhu a1, a1, a2
259; RV64-NEXT:    srli a1, a1, 16
260; RV64-NEXT:    subw a0, a0, a1
261; RV64-NEXT:    slli a0, a0, 48
262; RV64-NEXT:    srli a0, a0, 49
263; RV64-NEXT:    add a0, a0, a1
264; RV64-NEXT:    srli a0, a0, 2
265; RV64-NEXT:    ret
266  %1 = udiv i16 %a, 7
267  ret i16 %1
268}
269
270; Test the simplest case a srli and an add after the mul. No srai.
271define i32 @sdiv_constant_no_srai(i32 %a) nounwind {
272; RV32-LABEL: sdiv_constant_no_srai:
273; RV32:       # %bb.0:
274; RV32-NEXT:    lui a1, 349525
275; RV32-NEXT:    addi a1, a1, 1366
276; RV32-NEXT:    mulh a0, a0, a1
277; RV32-NEXT:    srli a1, a0, 31
278; RV32-NEXT:    add a0, a0, a1
279; RV32-NEXT:    ret
280;
281; RV64-LABEL: sdiv_constant_no_srai:
282; RV64:       # %bb.0:
283; RV64-NEXT:    sext.w a0, a0
284; RV64-NEXT:    lui a1, 349525
285; RV64-NEXT:    addiw a1, a1, 1366
286; RV64-NEXT:    mul a0, a0, a1
287; RV64-NEXT:    srli a1, a0, 63
288; RV64-NEXT:    srli a0, a0, 32
289; RV64-NEXT:    addw a0, a0, a1
290; RV64-NEXT:    ret
291  %1 = sdiv i32 %a, 3
292  ret i32 %1
293}
294
295; This constant requires an srai between the mul and the add.
296define i32 @sdiv_constant_srai(i32 %a) nounwind {
297; RV32-LABEL: sdiv_constant_srai:
298; RV32:       # %bb.0:
299; RV32-NEXT:    lui a1, 419430
300; RV32-NEXT:    addi a1, a1, 1639
301; RV32-NEXT:    mulh a0, a0, a1
302; RV32-NEXT:    srli a1, a0, 31
303; RV32-NEXT:    srai a0, a0, 1
304; RV32-NEXT:    add a0, a0, a1
305; RV32-NEXT:    ret
306;
307; RV64-LABEL: sdiv_constant_srai:
308; RV64:       # %bb.0:
309; RV64-NEXT:    sext.w a0, a0
310; RV64-NEXT:    lui a1, 419430
311; RV64-NEXT:    addiw a1, a1, 1639
312; RV64-NEXT:    mul a0, a0, a1
313; RV64-NEXT:    srli a1, a0, 63
314; RV64-NEXT:    srai a0, a0, 33
315; RV64-NEXT:    add a0, a0, a1
316; RV64-NEXT:    ret
317  %1 = sdiv i32 %a, 5
318  ret i32 %1
319}
320
321; This constant requires an add and an srai after the mul.
322define i32 @sdiv_constant_add_srai(i32 %a) nounwind {
323; RV32-LABEL: sdiv_constant_add_srai:
324; RV32:       # %bb.0:
325; RV32-NEXT:    lui a1, 599186
326; RV32-NEXT:    addi a1, a1, 1171
327; RV32-NEXT:    mulh a1, a0, a1
328; RV32-NEXT:    add a0, a1, a0
329; RV32-NEXT:    srli a1, a0, 31
330; RV32-NEXT:    srai a0, a0, 2
331; RV32-NEXT:    add a0, a0, a1
332; RV32-NEXT:    ret
333;
334; RV64-LABEL: sdiv_constant_add_srai:
335; RV64:       # %bb.0:
336; RV64-NEXT:    sext.w a1, a0
337; RV64-NEXT:    lui a2, 599186
338; RV64-NEXT:    addiw a2, a2, 1171
339; RV64-NEXT:    mul a1, a1, a2
340; RV64-NEXT:    srli a1, a1, 32
341; RV64-NEXT:    add a0, a1, a0
342; RV64-NEXT:    srliw a1, a0, 31
343; RV64-NEXT:    sraiw a0, a0, 2
344; RV64-NEXT:    add a0, a0, a1
345; RV64-NEXT:    ret
346  %1 = sdiv i32 %a, 7
347  ret i32 %1
348}
349
350; This constant requires a sub and an srai after the mul.
351define i32 @sdiv_constant_sub_srai(i32 %a) nounwind {
352; RV32-LABEL: sdiv_constant_sub_srai:
353; RV32:       # %bb.0:
354; RV32-NEXT:    lui a1, 449390
355; RV32-NEXT:    addi a1, a1, -1171
356; RV32-NEXT:    mulh a1, a0, a1
357; RV32-NEXT:    sub a1, a1, a0
358; RV32-NEXT:    srli a0, a1, 31
359; RV32-NEXT:    srai a1, a1, 2
360; RV32-NEXT:    add a0, a1, a0
361; RV32-NEXT:    ret
362;
363; RV64-LABEL: sdiv_constant_sub_srai:
364; RV64:       # %bb.0:
365; RV64-NEXT:    sext.w a1, a0
366; RV64-NEXT:    lui a2, 449390
367; RV64-NEXT:    addiw a2, a2, -1171
368; RV64-NEXT:    mul a1, a1, a2
369; RV64-NEXT:    srli a1, a1, 32
370; RV64-NEXT:    subw a1, a1, a0
371; RV64-NEXT:    srliw a0, a1, 31
372; RV64-NEXT:    sraiw a1, a1, 2
373; RV64-NEXT:    add a0, a1, a0
374; RV64-NEXT:    ret
375  %1 = sdiv i32 %a, -7
376  ret i32 %1
377}
378
379define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {
380; RV32-LABEL: sdiv64_constant_no_srai:
381; RV32:       # %bb.0:
382; RV32-NEXT:    addi sp, sp, -16
383; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
384; RV32-NEXT:    li a2, 3
385; RV32-NEXT:    li a3, 0
386; RV32-NEXT:    call __divdi3
387; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
388; RV32-NEXT:    addi sp, sp, 16
389; RV32-NEXT:    ret
390;
391; RV64-LABEL: sdiv64_constant_no_srai:
392; RV64:       # %bb.0:
393; RV64-NEXT:    lui a1, %hi(.LCPI12_0)
394; RV64-NEXT:    ld a1, %lo(.LCPI12_0)(a1)
395; RV64-NEXT:    mulh a0, a0, a1
396; RV64-NEXT:    srli a1, a0, 63
397; RV64-NEXT:    add a0, a0, a1
398; RV64-NEXT:    ret
399  %1 = sdiv i64 %a, 3
400  ret i64 %1
401}
402
403define i64 @sdiv64_constant_srai(i64 %a) nounwind {
404; RV32-LABEL: sdiv64_constant_srai:
405; RV32:       # %bb.0:
406; RV32-NEXT:    addi sp, sp, -16
407; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
408; RV32-NEXT:    li a2, 5
409; RV32-NEXT:    li a3, 0
410; RV32-NEXT:    call __divdi3
411; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
412; RV32-NEXT:    addi sp, sp, 16
413; RV32-NEXT:    ret
414;
415; RV64-LABEL: sdiv64_constant_srai:
416; RV64:       # %bb.0:
417; RV64-NEXT:    lui a1, %hi(.LCPI13_0)
418; RV64-NEXT:    ld a1, %lo(.LCPI13_0)(a1)
419; RV64-NEXT:    mulh a0, a0, a1
420; RV64-NEXT:    srli a1, a0, 63
421; RV64-NEXT:    srai a0, a0, 1
422; RV64-NEXT:    add a0, a0, a1
423; RV64-NEXT:    ret
424  %1 = sdiv i64 %a, 5
425  ret i64 %1
426}
427
428define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {
429; RV32-LABEL: sdiv64_constant_add_srai:
430; RV32:       # %bb.0:
431; RV32-NEXT:    addi sp, sp, -16
432; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
433; RV32-NEXT:    li a2, 15
434; RV32-NEXT:    li a3, 0
435; RV32-NEXT:    call __divdi3
436; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
437; RV32-NEXT:    addi sp, sp, 16
438; RV32-NEXT:    ret
439;
440; RV64-LABEL: sdiv64_constant_add_srai:
441; RV64:       # %bb.0:
442; RV64-NEXT:    lui a1, 559241
443; RV64-NEXT:    addiw a1, a1, -1911
444; RV64-NEXT:    slli a2, a1, 32
445; RV64-NEXT:    add a1, a1, a2
446; RV64-NEXT:    mulh a1, a0, a1
447; RV64-NEXT:    add a0, a1, a0
448; RV64-NEXT:    srli a1, a0, 63
449; RV64-NEXT:    srai a0, a0, 3
450; RV64-NEXT:    add a0, a0, a1
451; RV64-NEXT:    ret
452  %1 = sdiv i64 %a, 15
453  ret i64 %1
454}
455
456define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {
457; RV32-LABEL: sdiv64_constant_sub_srai:
458; RV32:       # %bb.0:
459; RV32-NEXT:    addi sp, sp, -16
460; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
461; RV32-NEXT:    li a2, -3
462; RV32-NEXT:    li a3, -1
463; RV32-NEXT:    call __divdi3
464; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
465; RV32-NEXT:    addi sp, sp, 16
466; RV32-NEXT:    ret
467;
468; RV64-LABEL: sdiv64_constant_sub_srai:
469; RV64:       # %bb.0:
470; RV64-NEXT:    lui a1, 349525
471; RV64-NEXT:    addiw a1, a1, 1365
472; RV64-NEXT:    slli a2, a1, 32
473; RV64-NEXT:    add a1, a1, a2
474; RV64-NEXT:    mulh a1, a0, a1
475; RV64-NEXT:    sub a1, a1, a0
476; RV64-NEXT:    srli a0, a1, 63
477; RV64-NEXT:    srai a1, a1, 1
478; RV64-NEXT:    add a0, a1, a0
479; RV64-NEXT:    ret
480  %1 = sdiv i64 %a, -3
481  ret i64 %1
482}
483
484define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
485; RV32IM-LABEL: sdiv8_constant_no_srai:
486; RV32IM:       # %bb.0:
487; RV32IM-NEXT:    slli a0, a0, 24
488; RV32IM-NEXT:    li a1, 86
489; RV32IM-NEXT:    srai a0, a0, 24
490; RV32IM-NEXT:    mul a0, a0, a1
491; RV32IM-NEXT:    srli a1, a0, 31
492; RV32IM-NEXT:    srli a0, a0, 8
493; RV32IM-NEXT:    add a0, a0, a1
494; RV32IM-NEXT:    ret
495;
496; RV32IMZB-LABEL: sdiv8_constant_no_srai:
497; RV32IMZB:       # %bb.0:
498; RV32IMZB-NEXT:    sext.b a0, a0
499; RV32IMZB-NEXT:    li a1, 86
500; RV32IMZB-NEXT:    mul a0, a0, a1
501; RV32IMZB-NEXT:    srli a1, a0, 31
502; RV32IMZB-NEXT:    srli a0, a0, 8
503; RV32IMZB-NEXT:    add a0, a0, a1
504; RV32IMZB-NEXT:    ret
505;
506; RV64IM-LABEL: sdiv8_constant_no_srai:
507; RV64IM:       # %bb.0:
508; RV64IM-NEXT:    slli a0, a0, 56
509; RV64IM-NEXT:    li a1, 86
510; RV64IM-NEXT:    srai a0, a0, 56
511; RV64IM-NEXT:    mul a0, a0, a1
512; RV64IM-NEXT:    srli a1, a0, 63
513; RV64IM-NEXT:    srli a0, a0, 8
514; RV64IM-NEXT:    add a0, a0, a1
515; RV64IM-NEXT:    ret
516;
517; RV64IMZB-LABEL: sdiv8_constant_no_srai:
518; RV64IMZB:       # %bb.0:
519; RV64IMZB-NEXT:    sext.b a0, a0
520; RV64IMZB-NEXT:    li a1, 86
521; RV64IMZB-NEXT:    mul a0, a0, a1
522; RV64IMZB-NEXT:    srli a1, a0, 63
523; RV64IMZB-NEXT:    srli a0, a0, 8
524; RV64IMZB-NEXT:    add a0, a0, a1
525; RV64IMZB-NEXT:    ret
526  %1 = sdiv i8 %a, 3
527  ret i8 %1
528}
529
530define i8 @sdiv8_constant_srai(i8 %a) nounwind {
531; RV32IM-LABEL: sdiv8_constant_srai:
532; RV32IM:       # %bb.0:
533; RV32IM-NEXT:    slli a0, a0, 24
534; RV32IM-NEXT:    li a1, 103
535; RV32IM-NEXT:    srai a0, a0, 24
536; RV32IM-NEXT:    mul a0, a0, a1
537; RV32IM-NEXT:    srli a1, a0, 31
538; RV32IM-NEXT:    srai a0, a0, 9
539; RV32IM-NEXT:    add a0, a0, a1
540; RV32IM-NEXT:    ret
541;
542; RV32IMZB-LABEL: sdiv8_constant_srai:
543; RV32IMZB:       # %bb.0:
544; RV32IMZB-NEXT:    sext.b a0, a0
545; RV32IMZB-NEXT:    li a1, 103
546; RV32IMZB-NEXT:    mul a0, a0, a1
547; RV32IMZB-NEXT:    srli a1, a0, 31
548; RV32IMZB-NEXT:    srai a0, a0, 9
549; RV32IMZB-NEXT:    add a0, a0, a1
550; RV32IMZB-NEXT:    ret
551;
552; RV64IM-LABEL: sdiv8_constant_srai:
553; RV64IM:       # %bb.0:
554; RV64IM-NEXT:    slli a0, a0, 56
555; RV64IM-NEXT:    li a1, 103
556; RV64IM-NEXT:    srai a0, a0, 56
557; RV64IM-NEXT:    mul a0, a0, a1
558; RV64IM-NEXT:    srli a1, a0, 63
559; RV64IM-NEXT:    srai a0, a0, 9
560; RV64IM-NEXT:    add a0, a0, a1
561; RV64IM-NEXT:    ret
562;
563; RV64IMZB-LABEL: sdiv8_constant_srai:
564; RV64IMZB:       # %bb.0:
565; RV64IMZB-NEXT:    sext.b a0, a0
566; RV64IMZB-NEXT:    li a1, 103
567; RV64IMZB-NEXT:    mul a0, a0, a1
568; RV64IMZB-NEXT:    srli a1, a0, 63
569; RV64IMZB-NEXT:    srai a0, a0, 9
570; RV64IMZB-NEXT:    add a0, a0, a1
571; RV64IMZB-NEXT:    ret
572  %1 = sdiv i8 %a, 5
573  ret i8 %1
574}
575
576define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
577; RV32IM-LABEL: sdiv8_constant_add_srai:
578; RV32IM:       # %bb.0:
579; RV32IM-NEXT:    slli a1, a0, 24
580; RV32IM-NEXT:    li a2, -109
581; RV32IM-NEXT:    srai a1, a1, 24
582; RV32IM-NEXT:    mul a1, a1, a2
583; RV32IM-NEXT:    srli a1, a1, 8
584; RV32IM-NEXT:    add a0, a1, a0
585; RV32IM-NEXT:    slli a0, a0, 24
586; RV32IM-NEXT:    srli a1, a0, 31
587; RV32IM-NEXT:    srai a0, a0, 26
588; RV32IM-NEXT:    add a0, a0, a1
589; RV32IM-NEXT:    ret
590;
591; RV32IMZB-LABEL: sdiv8_constant_add_srai:
592; RV32IMZB:       # %bb.0:
593; RV32IMZB-NEXT:    sext.b a1, a0
594; RV32IMZB-NEXT:    li a2, -109
595; RV32IMZB-NEXT:    mul a1, a1, a2
596; RV32IMZB-NEXT:    srli a1, a1, 8
597; RV32IMZB-NEXT:    add a0, a1, a0
598; RV32IMZB-NEXT:    slli a0, a0, 24
599; RV32IMZB-NEXT:    srli a1, a0, 31
600; RV32IMZB-NEXT:    srai a0, a0, 26
601; RV32IMZB-NEXT:    add a0, a0, a1
602; RV32IMZB-NEXT:    ret
603;
604; RV64IM-LABEL: sdiv8_constant_add_srai:
605; RV64IM:       # %bb.0:
606; RV64IM-NEXT:    slli a1, a0, 56
607; RV64IM-NEXT:    li a2, -109
608; RV64IM-NEXT:    srai a1, a1, 56
609; RV64IM-NEXT:    mul a1, a1, a2
610; RV64IM-NEXT:    srli a1, a1, 8
611; RV64IM-NEXT:    add a0, a1, a0
612; RV64IM-NEXT:    slli a0, a0, 56
613; RV64IM-NEXT:    srli a1, a0, 63
614; RV64IM-NEXT:    srai a0, a0, 58
615; RV64IM-NEXT:    add a0, a0, a1
616; RV64IM-NEXT:    ret
617;
618; RV64IMZB-LABEL: sdiv8_constant_add_srai:
619; RV64IMZB:       # %bb.0:
620; RV64IMZB-NEXT:    sext.b a1, a0
621; RV64IMZB-NEXT:    li a2, -109
622; RV64IMZB-NEXT:    mul a1, a1, a2
623; RV64IMZB-NEXT:    srli a1, a1, 8
624; RV64IMZB-NEXT:    add a0, a1, a0
625; RV64IMZB-NEXT:    slli a0, a0, 56
626; RV64IMZB-NEXT:    srli a1, a0, 63
627; RV64IMZB-NEXT:    srai a0, a0, 58
628; RV64IMZB-NEXT:    add a0, a0, a1
629; RV64IMZB-NEXT:    ret
630  %1 = sdiv i8 %a, 7
631  ret i8 %1
632}
633
634define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
635; RV32IM-LABEL: sdiv8_constant_sub_srai:
636; RV32IM:       # %bb.0:
637; RV32IM-NEXT:    slli a1, a0, 24
638; RV32IM-NEXT:    li a2, 109
639; RV32IM-NEXT:    srai a1, a1, 24
640; RV32IM-NEXT:    mul a1, a1, a2
641; RV32IM-NEXT:    srli a1, a1, 8
642; RV32IM-NEXT:    sub a1, a1, a0
643; RV32IM-NEXT:    slli a1, a1, 24
644; RV32IM-NEXT:    srli a0, a1, 31
645; RV32IM-NEXT:    srai a1, a1, 26
646; RV32IM-NEXT:    add a0, a1, a0
647; RV32IM-NEXT:    ret
648;
649; RV32IMZB-LABEL: sdiv8_constant_sub_srai:
650; RV32IMZB:       # %bb.0:
651; RV32IMZB-NEXT:    sext.b a1, a0
652; RV32IMZB-NEXT:    li a2, 109
653; RV32IMZB-NEXT:    mul a1, a1, a2
654; RV32IMZB-NEXT:    srli a1, a1, 8
655; RV32IMZB-NEXT:    sub a1, a1, a0
656; RV32IMZB-NEXT:    slli a1, a1, 24
657; RV32IMZB-NEXT:    srli a0, a1, 31
658; RV32IMZB-NEXT:    srai a1, a1, 26
659; RV32IMZB-NEXT:    add a0, a1, a0
660; RV32IMZB-NEXT:    ret
661;
662; RV64IM-LABEL: sdiv8_constant_sub_srai:
663; RV64IM:       # %bb.0:
664; RV64IM-NEXT:    slli a1, a0, 56
665; RV64IM-NEXT:    li a2, 109
666; RV64IM-NEXT:    srai a1, a1, 56
667; RV64IM-NEXT:    mul a1, a1, a2
668; RV64IM-NEXT:    srli a1, a1, 8
669; RV64IM-NEXT:    subw a1, a1, a0
670; RV64IM-NEXT:    slli a1, a1, 56
671; RV64IM-NEXT:    srli a0, a1, 63
672; RV64IM-NEXT:    srai a1, a1, 58
673; RV64IM-NEXT:    add a0, a1, a0
674; RV64IM-NEXT:    ret
675;
676; RV64IMZB-LABEL: sdiv8_constant_sub_srai:
677; RV64IMZB:       # %bb.0:
678; RV64IMZB-NEXT:    sext.b a1, a0
679; RV64IMZB-NEXT:    li a2, 109
680; RV64IMZB-NEXT:    mul a1, a1, a2
681; RV64IMZB-NEXT:    srli a1, a1, 8
682; RV64IMZB-NEXT:    subw a1, a1, a0
683; RV64IMZB-NEXT:    slli a1, a1, 56
684; RV64IMZB-NEXT:    srli a0, a1, 63
685; RV64IMZB-NEXT:    srai a1, a1, 58
686; RV64IMZB-NEXT:    add a0, a1, a0
687; RV64IMZB-NEXT:    ret
688  %1 = sdiv i8 %a, -7
689  ret i8 %1
690}
691
692define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
693; RV32IM-LABEL: sdiv16_constant_no_srai:
694; RV32IM:       # %bb.0:
695; RV32IM-NEXT:    slli a0, a0, 16
696; RV32IM-NEXT:    lui a1, 5
697; RV32IM-NEXT:    srai a0, a0, 16
698; RV32IM-NEXT:    addi a1, a1, 1366
699; RV32IM-NEXT:    mul a0, a0, a1
700; RV32IM-NEXT:    srli a1, a0, 31
701; RV32IM-NEXT:    srli a0, a0, 16
702; RV32IM-NEXT:    add a0, a0, a1
703; RV32IM-NEXT:    ret
704;
705; RV32IMZB-LABEL: sdiv16_constant_no_srai:
706; RV32IMZB:       # %bb.0:
707; RV32IMZB-NEXT:    sext.h a0, a0
708; RV32IMZB-NEXT:    lui a1, 5
709; RV32IMZB-NEXT:    addi a1, a1, 1366
710; RV32IMZB-NEXT:    mul a0, a0, a1
711; RV32IMZB-NEXT:    srli a1, a0, 31
712; RV32IMZB-NEXT:    srli a0, a0, 16
713; RV32IMZB-NEXT:    add a0, a0, a1
714; RV32IMZB-NEXT:    ret
715;
716; RV64IM-LABEL: sdiv16_constant_no_srai:
717; RV64IM:       # %bb.0:
718; RV64IM-NEXT:    slli a0, a0, 48
719; RV64IM-NEXT:    lui a1, 5
720; RV64IM-NEXT:    srai a0, a0, 48
721; RV64IM-NEXT:    addiw a1, a1, 1366
722; RV64IM-NEXT:    mul a0, a0, a1
723; RV64IM-NEXT:    srli a1, a0, 63
724; RV64IM-NEXT:    srli a0, a0, 16
725; RV64IM-NEXT:    add a0, a0, a1
726; RV64IM-NEXT:    ret
727;
728; RV64IMZB-LABEL: sdiv16_constant_no_srai:
729; RV64IMZB:       # %bb.0:
730; RV64IMZB-NEXT:    sext.h a0, a0
731; RV64IMZB-NEXT:    lui a1, 5
732; RV64IMZB-NEXT:    addiw a1, a1, 1366
733; RV64IMZB-NEXT:    mul a0, a0, a1
734; RV64IMZB-NEXT:    srli a1, a0, 63
735; RV64IMZB-NEXT:    srli a0, a0, 16
736; RV64IMZB-NEXT:    add a0, a0, a1
737; RV64IMZB-NEXT:    ret
738  %1 = sdiv i16 %a, 3
739  ret i16 %1
740}
741
742define i16 @sdiv16_constant_srai(i16 %a) nounwind {
743; RV32IM-LABEL: sdiv16_constant_srai:
744; RV32IM:       # %bb.0:
745; RV32IM-NEXT:    slli a0, a0, 16
746; RV32IM-NEXT:    lui a1, 6
747; RV32IM-NEXT:    srai a0, a0, 16
748; RV32IM-NEXT:    addi a1, a1, 1639
749; RV32IM-NEXT:    mul a0, a0, a1
750; RV32IM-NEXT:    srli a1, a0, 31
751; RV32IM-NEXT:    srai a0, a0, 17
752; RV32IM-NEXT:    add a0, a0, a1
753; RV32IM-NEXT:    ret
754;
755; RV32IMZB-LABEL: sdiv16_constant_srai:
756; RV32IMZB:       # %bb.0:
757; RV32IMZB-NEXT:    sext.h a0, a0
758; RV32IMZB-NEXT:    lui a1, 6
759; RV32IMZB-NEXT:    addi a1, a1, 1639
760; RV32IMZB-NEXT:    mul a0, a0, a1
761; RV32IMZB-NEXT:    srli a1, a0, 31
762; RV32IMZB-NEXT:    srai a0, a0, 17
763; RV32IMZB-NEXT:    add a0, a0, a1
764; RV32IMZB-NEXT:    ret
765;
766; RV64IM-LABEL: sdiv16_constant_srai:
767; RV64IM:       # %bb.0:
768; RV64IM-NEXT:    slli a0, a0, 48
769; RV64IM-NEXT:    lui a1, 6
770; RV64IM-NEXT:    srai a0, a0, 48
771; RV64IM-NEXT:    addiw a1, a1, 1639
772; RV64IM-NEXT:    mul a0, a0, a1
773; RV64IM-NEXT:    srli a1, a0, 63
774; RV64IM-NEXT:    srai a0, a0, 17
775; RV64IM-NEXT:    add a0, a0, a1
776; RV64IM-NEXT:    ret
777;
778; RV64IMZB-LABEL: sdiv16_constant_srai:
779; RV64IMZB:       # %bb.0:
780; RV64IMZB-NEXT:    sext.h a0, a0
781; RV64IMZB-NEXT:    lui a1, 6
782; RV64IMZB-NEXT:    addiw a1, a1, 1639
783; RV64IMZB-NEXT:    mul a0, a0, a1
784; RV64IMZB-NEXT:    srli a1, a0, 63
785; RV64IMZB-NEXT:    srai a0, a0, 17
786; RV64IMZB-NEXT:    add a0, a0, a1
787; RV64IMZB-NEXT:    ret
788  %1 = sdiv i16 %a, 5
789  ret i16 %1
790}
791
792define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
793; RV32IM-LABEL: sdiv16_constant_add_srai:
794; RV32IM:       # %bb.0:
795; RV32IM-NEXT:    slli a1, a0, 16
796; RV32IM-NEXT:    lui a2, 1048569
797; RV32IM-NEXT:    srai a1, a1, 16
798; RV32IM-NEXT:    addi a2, a2, -1911
799; RV32IM-NEXT:    mul a1, a1, a2
800; RV32IM-NEXT:    srli a1, a1, 16
801; RV32IM-NEXT:    add a0, a1, a0
802; RV32IM-NEXT:    slli a0, a0, 16
803; RV32IM-NEXT:    srli a1, a0, 31
804; RV32IM-NEXT:    srai a0, a0, 19
805; RV32IM-NEXT:    add a0, a0, a1
806; RV32IM-NEXT:    ret
807;
808; RV32IMZB-LABEL: sdiv16_constant_add_srai:
809; RV32IMZB:       # %bb.0:
810; RV32IMZB-NEXT:    sext.h a1, a0
811; RV32IMZB-NEXT:    lui a2, 1048569
812; RV32IMZB-NEXT:    addi a2, a2, -1911
813; RV32IMZB-NEXT:    mul a1, a1, a2
814; RV32IMZB-NEXT:    srli a1, a1, 16
815; RV32IMZB-NEXT:    add a0, a1, a0
816; RV32IMZB-NEXT:    slli a0, a0, 16
817; RV32IMZB-NEXT:    srli a1, a0, 31
818; RV32IMZB-NEXT:    srai a0, a0, 19
819; RV32IMZB-NEXT:    add a0, a0, a1
820; RV32IMZB-NEXT:    ret
821;
822; RV64IM-LABEL: sdiv16_constant_add_srai:
823; RV64IM:       # %bb.0:
824; RV64IM-NEXT:    slli a1, a0, 48
825; RV64IM-NEXT:    lui a2, 1048569
826; RV64IM-NEXT:    srai a1, a1, 48
827; RV64IM-NEXT:    addiw a2, a2, -1911
828; RV64IM-NEXT:    mul a1, a1, a2
829; RV64IM-NEXT:    srli a1, a1, 16
830; RV64IM-NEXT:    add a0, a1, a0
831; RV64IM-NEXT:    slli a0, a0, 48
832; RV64IM-NEXT:    srli a1, a0, 63
833; RV64IM-NEXT:    srai a0, a0, 51
834; RV64IM-NEXT:    add a0, a0, a1
835; RV64IM-NEXT:    ret
836;
837; RV64IMZB-LABEL: sdiv16_constant_add_srai:
838; RV64IMZB:       # %bb.0:
839; RV64IMZB-NEXT:    sext.h a1, a0
840; RV64IMZB-NEXT:    lui a2, 1048569
841; RV64IMZB-NEXT:    addiw a2, a2, -1911
842; RV64IMZB-NEXT:    mul a1, a1, a2
843; RV64IMZB-NEXT:    srli a1, a1, 16
844; RV64IMZB-NEXT:    add a0, a1, a0
845; RV64IMZB-NEXT:    slli a0, a0, 48
846; RV64IMZB-NEXT:    srli a1, a0, 63
847; RV64IMZB-NEXT:    srai a0, a0, 51
848; RV64IMZB-NEXT:    add a0, a0, a1
849; RV64IMZB-NEXT:    ret
850  %1 = sdiv i16 %a, 15
851  ret i16 %1
852}
853
854define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
855; RV32IM-LABEL: sdiv16_constant_sub_srai:
856; RV32IM:       # %bb.0:
857; RV32IM-NEXT:    slli a1, a0, 16
858; RV32IM-NEXT:    lui a2, 7
859; RV32IM-NEXT:    srai a1, a1, 16
860; RV32IM-NEXT:    addi a2, a2, 1911
861; RV32IM-NEXT:    mul a1, a1, a2
862; RV32IM-NEXT:    srli a1, a1, 16
863; RV32IM-NEXT:    sub a1, a1, a0
864; RV32IM-NEXT:    slli a1, a1, 16
865; RV32IM-NEXT:    srli a0, a1, 31
866; RV32IM-NEXT:    srai a1, a1, 19
867; RV32IM-NEXT:    add a0, a1, a0
868; RV32IM-NEXT:    ret
869;
870; RV32IMZB-LABEL: sdiv16_constant_sub_srai:
871; RV32IMZB:       # %bb.0:
872; RV32IMZB-NEXT:    sext.h a1, a0
873; RV32IMZB-NEXT:    lui a2, 7
874; RV32IMZB-NEXT:    addi a2, a2, 1911
875; RV32IMZB-NEXT:    mul a1, a1, a2
876; RV32IMZB-NEXT:    srli a1, a1, 16
877; RV32IMZB-NEXT:    sub a1, a1, a0
878; RV32IMZB-NEXT:    slli a1, a1, 16
879; RV32IMZB-NEXT:    srli a0, a1, 31
880; RV32IMZB-NEXT:    srai a1, a1, 19
881; RV32IMZB-NEXT:    add a0, a1, a0
882; RV32IMZB-NEXT:    ret
883;
884; RV64IM-LABEL: sdiv16_constant_sub_srai:
885; RV64IM:       # %bb.0:
886; RV64IM-NEXT:    slli a1, a0, 48
887; RV64IM-NEXT:    lui a2, 7
888; RV64IM-NEXT:    srai a1, a1, 48
889; RV64IM-NEXT:    addiw a2, a2, 1911
890; RV64IM-NEXT:    mul a1, a1, a2
891; RV64IM-NEXT:    srli a1, a1, 16
892; RV64IM-NEXT:    subw a1, a1, a0
893; RV64IM-NEXT:    slli a1, a1, 48
894; RV64IM-NEXT:    srli a0, a1, 63
895; RV64IM-NEXT:    srai a1, a1, 51
896; RV64IM-NEXT:    add a0, a1, a0
897; RV64IM-NEXT:    ret
898;
899; RV64IMZB-LABEL: sdiv16_constant_sub_srai:
900; RV64IMZB:       # %bb.0:
901; RV64IMZB-NEXT:    sext.h a1, a0
902; RV64IMZB-NEXT:    lui a2, 7
903; RV64IMZB-NEXT:    addiw a2, a2, 1911
904; RV64IMZB-NEXT:    mul a1, a1, a2
905; RV64IMZB-NEXT:    srli a1, a1, 16
906; RV64IMZB-NEXT:    subw a1, a1, a0
907; RV64IMZB-NEXT:    slli a1, a1, 48
908; RV64IMZB-NEXT:    srli a0, a1, 63
909; RV64IMZB-NEXT:    srai a1, a1, 51
910; RV64IMZB-NEXT:    add a0, a1, a0
911; RV64IMZB-NEXT:    ret
912  %1 = sdiv i16 %a, -15
913  ret i16 %1
914}
915