xref: /llvm-project/llvm/test/CodeGen/RISCV/compress-float.ll (revision c532ba4edd7ad7675ba450ba43268aa9e7bda46b)
1; This test is designed to run three times, once with function attributes, once
2; with all target attributes added on the command line, and once with compress
3; added with the command line and float added via function attributes, all
4; three of these should result in the same output.
5;
6; RUN: cat %s > %t.tgtattr
7; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
8; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \
9; RUN:   -disable-block-placement < %t.tgtattr \
10; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
11; RUN:   | FileCheck -check-prefix=RV32IFDC %s
12;
13; RUN: cat %s > %t.fnattr
14; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr
15; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
16; RUN:   -disable-block-placement < %t.fnattr \
17; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
18; RUN:   | FileCheck -check-prefix=RV32IFDC %s
19;
20; RUN: cat %s > %t.mixedattr
21; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
22; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \
23; RUN:   -disable-block-placement < %t.mixedattr \
24; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
25; RUN:   | FileCheck -check-prefix=RV32IFDC %s
26;
27; RUN: cat %s > %t.tgtattr
28; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
29; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \
30; RUN:   -disable-block-placement < %t.tgtattr \
31; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
32; RUN:   | FileCheck -check-prefix=RV32IFDC %s
33;
34; RUN: cat %s > %t.fnattr
35; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcf,+f" }' >> %t.fnattr
36; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
37; RUN:   -disable-block-placement < %t.fnattr \
38; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
39; RUN:   | FileCheck -check-prefix=RV32IFDC %s
40;
41; RUN: cat %s > %t.mixedattr
42; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
43; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf -filetype=obj \
44; RUN:   -disable-block-placement < %t.mixedattr \
45; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
46; RUN:   | FileCheck -check-prefix=RV32IFDC %s
47;
48; RUN: cat %s > %t.tgtattr
49; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
50; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \
51; RUN:   -disable-block-placement < %t.tgtattr \
52; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
53; RUN:   | FileCheck -check-prefix=RV32IFDC %s
54;
55; RUN: cat %s > %t.fnattr
56; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr
57; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
58; RUN:   -disable-block-placement < %t.fnattr \
59; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
60; RUN:   | FileCheck -check-prefix=RV32IFDC %s
61;
62; RUN: cat %s > %t.mixedattr
63; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
64; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \
65; RUN:   -disable-block-placement < %t.mixedattr \
66; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
67; RUN:   | FileCheck -check-prefix=RV32IFDC %s
68
69; This acts as a basic correctness check for the codegen instruction compression
70; path, verifying that the assembled file contains compressed instructions when
71; expected. Handling of the compressed ISA is implemented so the same
72; transformation patterns should be used whether compressing an input .s file or
73; compressing codegen output. This file contains basic functionality tests using
74; instructions which also require one of the floating point extensions.
75
76define float @float_load(ptr %a) #0 {
77; RV32IFDC-LABEL: <float_load>:
78; RV32IFDC:         c.flw fa0, 0x0(a0)
79; RV32IFDC-NEXT:    c.jr ra
80  %1 = load volatile float, ptr %a
81  ret float %1
82}
83