1; This test is designed to run three times, once with function attributes, once 2; with all target attributes added on the command line, and once with compress 3; added with the command line and float added via function attributes, all 4; three of these should result in the same output. 5; 6; RUN: cat %s > %t.tgtattr 7; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr 8; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zcd,+d -filetype=obj \ 9; RUN: -disable-block-placement < %t.tgtattr \ 10; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \ 11; RUN: | FileCheck -check-prefix=RV32IFDC %s 12; 13; RUN: cat %s > %t.fnattr 14; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcd,+d" }' >> %t.fnattr 15; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \ 16; RUN: -disable-block-placement < %t.fnattr \ 17; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \ 18; RUN: | FileCheck -check-prefix=RV32IFDC %s 19; 20; RUN: cat %s > %t.mixedattr 21; RUN: echo 'attributes #0 = { nounwind "target-features"="+d" }' >> %t.mixedattr 22; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zcd -filetype=obj \ 23; RUN: -disable-block-placement < %t.mixedattr \ 24; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \ 25; RUN: | FileCheck -check-prefix=RV32IFDC %s 26 27; This acts as a basic correctness check for the codegen instruction compression 28; path, verifying that the assembled file contains compressed instructions when 29; expected. Handling of the compressed ISA is implemented so the same 30; transformation patterns should be used whether compressing an input .s file or 31; compressing codegen output. This file contains basic functionality tests using 32; instructions which also require one of the floating point extensions. 33 34define double @double_load(ptr %a) #0 { 35; RV32IFDC-LABEL: <double_load>: 36; RV32IFDC: c.fld fa0, 0x0(a0) 37; RV32IFDC-NEXT: c.jr ra 38 %1 = load volatile double, ptr %a 39 ret double %1 40} 41