1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32F-SMALL 4; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=medium -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32F-MEDIUM 6; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=small -verify-machineinstrs < %s \ 7; RUN: | FileCheck %s -check-prefixes=RV64I-SMALL,RV64F-SMALL 8; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=medium -verify-machineinstrs < %s \ 9; RUN: | FileCheck %s -check-prefixes=RV64I-MEDIUM,RV64F-MEDIUM 10; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=large -verify-machineinstrs < %s \ 11; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64F-LARGE 12; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs < %s \ 13; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32FINX-SMALL 14; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=medium -verify-machineinstrs < %s \ 15; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32FINX-MEDIUM 16; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=small -verify-machineinstrs < %s \ 17; RUN: | FileCheck %s -check-prefixes=RV64I-SMALL,RV64FINX-SMALL 18; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=medium -verify-machineinstrs < %s \ 19; RUN: | FileCheck %s -check-prefixes=RV64I-MEDIUM,RV64FINX-MEDIUM 20; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=large -verify-machineinstrs < %s \ 21; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64FINX-LARGE 22 23; Check lowering of globals 24@G = global i32 0 25 26define i32 @lower_global(i32 %a) nounwind { 27; RV32I-SMALL-LABEL: lower_global: 28; RV32I-SMALL: # %bb.0: 29; RV32I-SMALL-NEXT: lui a0, %hi(G) 30; RV32I-SMALL-NEXT: lw a0, %lo(G)(a0) 31; RV32I-SMALL-NEXT: ret 32; 33; RV32I-MEDIUM-LABEL: lower_global: 34; RV32I-MEDIUM: # %bb.0: 35; RV32I-MEDIUM-NEXT: .Lpcrel_hi0: 36; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(G) 37; RV32I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0) 38; RV32I-MEDIUM-NEXT: ret 39; 40; RV64I-SMALL-LABEL: lower_global: 41; RV64I-SMALL: # %bb.0: 42; RV64I-SMALL-NEXT: lui a0, %hi(G) 43; RV64I-SMALL-NEXT: lw a0, %lo(G)(a0) 44; RV64I-SMALL-NEXT: ret 45; 46; RV64I-MEDIUM-LABEL: lower_global: 47; RV64I-MEDIUM: # %bb.0: 48; RV64I-MEDIUM-NEXT: .Lpcrel_hi0: 49; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(G) 50; RV64I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0) 51; RV64I-MEDIUM-NEXT: ret 52; 53; RV64I-LARGE-LABEL: lower_global: 54; RV64I-LARGE: # %bb.0: 55; RV64I-LARGE-NEXT: .Lpcrel_hi0: 56; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI0_0) 57; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) 58; RV64I-LARGE-NEXT: lw a0, 0(a0) 59; RV64I-LARGE-NEXT: ret 60 %1 = load volatile i32, ptr @G 61 ret i32 %1 62} 63 64; Check lowering of blockaddresses 65 66@addr = global ptr null 67 68define void @lower_blockaddress() nounwind { 69; RV32I-SMALL-LABEL: lower_blockaddress: 70; RV32I-SMALL: # %bb.0: 71; RV32I-SMALL-NEXT: lui a0, %hi(addr) 72; RV32I-SMALL-NEXT: li a1, 1 73; RV32I-SMALL-NEXT: sw a1, %lo(addr)(a0) 74; RV32I-SMALL-NEXT: ret 75; 76; RV32I-MEDIUM-LABEL: lower_blockaddress: 77; RV32I-MEDIUM: # %bb.0: 78; RV32I-MEDIUM-NEXT: .Lpcrel_hi1: 79; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(addr) 80; RV32I-MEDIUM-NEXT: li a1, 1 81; RV32I-MEDIUM-NEXT: sw a1, %pcrel_lo(.Lpcrel_hi1)(a0) 82; RV32I-MEDIUM-NEXT: ret 83; 84; RV64I-SMALL-LABEL: lower_blockaddress: 85; RV64I-SMALL: # %bb.0: 86; RV64I-SMALL-NEXT: lui a0, %hi(addr) 87; RV64I-SMALL-NEXT: li a1, 1 88; RV64I-SMALL-NEXT: sd a1, %lo(addr)(a0) 89; RV64I-SMALL-NEXT: ret 90; 91; RV64I-MEDIUM-LABEL: lower_blockaddress: 92; RV64I-MEDIUM: # %bb.0: 93; RV64I-MEDIUM-NEXT: .Lpcrel_hi1: 94; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(addr) 95; RV64I-MEDIUM-NEXT: li a1, 1 96; RV64I-MEDIUM-NEXT: sd a1, %pcrel_lo(.Lpcrel_hi1)(a0) 97; RV64I-MEDIUM-NEXT: ret 98; 99; RV64I-LARGE-LABEL: lower_blockaddress: 100; RV64I-LARGE: # %bb.0: 101; RV64I-LARGE-NEXT: .Lpcrel_hi1: 102; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI1_0) 103; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) 104; RV64I-LARGE-NEXT: li a1, 1 105; RV64I-LARGE-NEXT: sd a1, 0(a0) 106; RV64I-LARGE-NEXT: ret 107 store volatile ptr blockaddress(@lower_blockaddress, %block), ptr @addr 108 ret void 109 110block: 111 unreachable 112} 113 114; Check lowering of blockaddress that forces a displacement to be added 115 116define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind { 117; RV32I-SMALL-LABEL: lower_blockaddress_displ: 118; RV32I-SMALL: # %bb.0: # %entry 119; RV32I-SMALL-NEXT: addi sp, sp, -16 120; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0) 121; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0) 122; RV32I-SMALL-NEXT: li a2, 101 123; RV32I-SMALL-NEXT: sw a1, 8(sp) 124; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3 125; RV32I-SMALL-NEXT: # %bb.1: # %if.then 126; RV32I-SMALL-NEXT: lw a0, 8(sp) 127; RV32I-SMALL-NEXT: jr a0 128; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken 129; RV32I-SMALL-NEXT: .LBB2_2: # %return 130; RV32I-SMALL-NEXT: li a0, 4 131; RV32I-SMALL-NEXT: addi sp, sp, 16 132; RV32I-SMALL-NEXT: ret 133; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone 134; RV32I-SMALL-NEXT: li a0, 3 135; RV32I-SMALL-NEXT: addi sp, sp, 16 136; RV32I-SMALL-NEXT: ret 137; 138; RV32I-MEDIUM-LABEL: lower_blockaddress_displ: 139; RV32I-MEDIUM: # %bb.0: # %entry 140; RV32I-MEDIUM-NEXT: addi sp, sp, -16 141; RV32I-MEDIUM-NEXT: .Lpcrel_hi2: 142; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0) 143; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2) 144; RV32I-MEDIUM-NEXT: li a2, 101 145; RV32I-MEDIUM-NEXT: sw a1, 8(sp) 146; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3 147; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then 148; RV32I-MEDIUM-NEXT: lw a0, 8(sp) 149; RV32I-MEDIUM-NEXT: jr a0 150; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken 151; RV32I-MEDIUM-NEXT: .LBB2_2: # %return 152; RV32I-MEDIUM-NEXT: li a0, 4 153; RV32I-MEDIUM-NEXT: addi sp, sp, 16 154; RV32I-MEDIUM-NEXT: ret 155; RV32I-MEDIUM-NEXT: .LBB2_3: # %return.clone 156; RV32I-MEDIUM-NEXT: li a0, 3 157; RV32I-MEDIUM-NEXT: addi sp, sp, 16 158; RV32I-MEDIUM-NEXT: ret 159; 160; RV64I-SMALL-LABEL: lower_blockaddress_displ: 161; RV64I-SMALL: # %bb.0: # %entry 162; RV64I-SMALL-NEXT: addi sp, sp, -16 163; RV64I-SMALL-NEXT: lui a1, %hi(.Ltmp0) 164; RV64I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0) 165; RV64I-SMALL-NEXT: li a2, 101 166; RV64I-SMALL-NEXT: sd a1, 8(sp) 167; RV64I-SMALL-NEXT: blt a0, a2, .LBB2_3 168; RV64I-SMALL-NEXT: # %bb.1: # %if.then 169; RV64I-SMALL-NEXT: ld a0, 8(sp) 170; RV64I-SMALL-NEXT: jr a0 171; RV64I-SMALL-NEXT: .Ltmp0: # Block address taken 172; RV64I-SMALL-NEXT: .LBB2_2: # %return 173; RV64I-SMALL-NEXT: li a0, 4 174; RV64I-SMALL-NEXT: addi sp, sp, 16 175; RV64I-SMALL-NEXT: ret 176; RV64I-SMALL-NEXT: .LBB2_3: # %return.clone 177; RV64I-SMALL-NEXT: li a0, 3 178; RV64I-SMALL-NEXT: addi sp, sp, 16 179; RV64I-SMALL-NEXT: ret 180; 181; RV64I-MEDIUM-LABEL: lower_blockaddress_displ: 182; RV64I-MEDIUM: # %bb.0: # %entry 183; RV64I-MEDIUM-NEXT: addi sp, sp, -16 184; RV64I-MEDIUM-NEXT: .Lpcrel_hi2: 185; RV64I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0) 186; RV64I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2) 187; RV64I-MEDIUM-NEXT: li a2, 101 188; RV64I-MEDIUM-NEXT: sd a1, 8(sp) 189; RV64I-MEDIUM-NEXT: blt a0, a2, .LBB2_3 190; RV64I-MEDIUM-NEXT: # %bb.1: # %if.then 191; RV64I-MEDIUM-NEXT: ld a0, 8(sp) 192; RV64I-MEDIUM-NEXT: jr a0 193; RV64I-MEDIUM-NEXT: .Ltmp0: # Block address taken 194; RV64I-MEDIUM-NEXT: .LBB2_2: # %return 195; RV64I-MEDIUM-NEXT: li a0, 4 196; RV64I-MEDIUM-NEXT: addi sp, sp, 16 197; RV64I-MEDIUM-NEXT: ret 198; RV64I-MEDIUM-NEXT: .LBB2_3: # %return.clone 199; RV64I-MEDIUM-NEXT: li a0, 3 200; RV64I-MEDIUM-NEXT: addi sp, sp, 16 201; RV64I-MEDIUM-NEXT: ret 202; 203; RV64I-LARGE-LABEL: lower_blockaddress_displ: 204; RV64I-LARGE: # %bb.0: # %entry 205; RV64I-LARGE-NEXT: addi sp, sp, -16 206; RV64I-LARGE-NEXT: .Lpcrel_hi2: 207; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.Ltmp0) 208; RV64I-LARGE-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2) 209; RV64I-LARGE-NEXT: li a2, 101 210; RV64I-LARGE-NEXT: sd a1, 8(sp) 211; RV64I-LARGE-NEXT: blt a0, a2, .LBB2_3 212; RV64I-LARGE-NEXT: # %bb.1: # %if.then 213; RV64I-LARGE-NEXT: ld a0, 8(sp) 214; RV64I-LARGE-NEXT: jr a0 215; RV64I-LARGE-NEXT: .Ltmp0: # Block address taken 216; RV64I-LARGE-NEXT: .LBB2_2: # %return 217; RV64I-LARGE-NEXT: li a0, 4 218; RV64I-LARGE-NEXT: addi sp, sp, 16 219; RV64I-LARGE-NEXT: ret 220; RV64I-LARGE-NEXT: .LBB2_3: # %return.clone 221; RV64I-LARGE-NEXT: li a0, 3 222; RV64I-LARGE-NEXT: addi sp, sp, 16 223; RV64I-LARGE-NEXT: ret 224entry: 225 %x = alloca ptr, align 8 226 store ptr blockaddress(@lower_blockaddress_displ, %test_block), ptr %x, align 8 227 %cmp = icmp sgt i32 %w, 100 228 br i1 %cmp, label %if.then, label %if.end 229 230if.then: 231 %addr = load ptr, ptr %x, align 8 232 br label %indirectgoto 233 234if.end: 235 br label %return 236 237test_block: 238 br label %return 239 240return: 241 %retval = phi i32 [ 3, %if.end ], [ 4, %test_block ] 242 ret i32 %retval 243 244indirectgoto: 245 indirectbr ptr %addr, [ label %test_block ] 246} 247 248; Check lowering of constantpools 249 250define float @lower_constantpool(float %a) nounwind { 251; RV32F-SMALL-LABEL: lower_constantpool: 252; RV32F-SMALL: # %bb.0: 253; RV32F-SMALL-NEXT: lui a0, %hi(.LCPI3_0) 254; RV32F-SMALL-NEXT: flw fa5, %lo(.LCPI3_0)(a0) 255; RV32F-SMALL-NEXT: fadd.s fa0, fa0, fa5 256; RV32F-SMALL-NEXT: ret 257; 258; RV32F-MEDIUM-LABEL: lower_constantpool: 259; RV32F-MEDIUM: # %bb.0: 260; RV32F-MEDIUM-NEXT: .Lpcrel_hi3: 261; RV32F-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0) 262; RV32F-MEDIUM-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0) 263; RV32F-MEDIUM-NEXT: fadd.s fa0, fa0, fa5 264; RV32F-MEDIUM-NEXT: ret 265; 266; RV64F-SMALL-LABEL: lower_constantpool: 267; RV64F-SMALL: # %bb.0: 268; RV64F-SMALL-NEXT: lui a0, %hi(.LCPI3_0) 269; RV64F-SMALL-NEXT: flw fa5, %lo(.LCPI3_0)(a0) 270; RV64F-SMALL-NEXT: fadd.s fa0, fa0, fa5 271; RV64F-SMALL-NEXT: ret 272; 273; RV64F-MEDIUM-LABEL: lower_constantpool: 274; RV64F-MEDIUM: # %bb.0: 275; RV64F-MEDIUM-NEXT: .Lpcrel_hi3: 276; RV64F-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0) 277; RV64F-MEDIUM-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0) 278; RV64F-MEDIUM-NEXT: fadd.s fa0, fa0, fa5 279; RV64F-MEDIUM-NEXT: ret 280; 281; RV64F-LARGE-LABEL: lower_constantpool: 282; RV64F-LARGE: # %bb.0: 283; RV64F-LARGE-NEXT: .Lpcrel_hi3: 284; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_0) 285; RV64F-LARGE-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0) 286; RV64F-LARGE-NEXT: fadd.s fa0, fa0, fa5 287; RV64F-LARGE-NEXT: ret 288; 289; RV32FINX-SMALL-LABEL: lower_constantpool: 290; RV32FINX-SMALL: # %bb.0: 291; RV32FINX-SMALL-NEXT: lui a1, 260097 292; RV32FINX-SMALL-NEXT: addi a1, a1, -2048 293; RV32FINX-SMALL-NEXT: fadd.s a0, a0, a1 294; RV32FINX-SMALL-NEXT: ret 295; 296; RV32FINX-MEDIUM-LABEL: lower_constantpool: 297; RV32FINX-MEDIUM: # %bb.0: 298; RV32FINX-MEDIUM-NEXT: lui a1, 260097 299; RV32FINX-MEDIUM-NEXT: addi a1, a1, -2048 300; RV32FINX-MEDIUM-NEXT: fadd.s a0, a0, a1 301; RV32FINX-MEDIUM-NEXT: ret 302; 303; RV64FINX-SMALL-LABEL: lower_constantpool: 304; RV64FINX-SMALL: # %bb.0: 305; RV64FINX-SMALL-NEXT: lui a1, 260097 306; RV64FINX-SMALL-NEXT: addiw a1, a1, -2048 307; RV64FINX-SMALL-NEXT: fadd.s a0, a0, a1 308; RV64FINX-SMALL-NEXT: ret 309; 310; RV64FINX-MEDIUM-LABEL: lower_constantpool: 311; RV64FINX-MEDIUM: # %bb.0: 312; RV64FINX-MEDIUM-NEXT: lui a1, 260097 313; RV64FINX-MEDIUM-NEXT: addiw a1, a1, -2048 314; RV64FINX-MEDIUM-NEXT: fadd.s a0, a0, a1 315; RV64FINX-MEDIUM-NEXT: ret 316; 317; RV64FINX-LARGE-LABEL: lower_constantpool: 318; RV64FINX-LARGE: # %bb.0: 319; RV64FINX-LARGE-NEXT: lui a1, 260097 320; RV64FINX-LARGE-NEXT: addiw a1, a1, -2048 321; RV64FINX-LARGE-NEXT: fadd.s a0, a0, a1 322; RV64FINX-LARGE-NEXT: ret 323 %1 = fadd float %a, 1.000244140625 324 ret float %1 325} 326 327; Check lowering of extern_weaks 328@W = extern_weak global i32 329 330define i32 @lower_extern_weak(i32 %a) nounwind { 331; RV32I-SMALL-LABEL: lower_extern_weak: 332; RV32I-SMALL: # %bb.0: 333; RV32I-SMALL-NEXT: lui a0, %hi(W) 334; RV32I-SMALL-NEXT: lw a0, %lo(W)(a0) 335; RV32I-SMALL-NEXT: ret 336; 337; RV32F-MEDIUM-LABEL: lower_extern_weak: 338; RV32F-MEDIUM: # %bb.0: 339; RV32F-MEDIUM-NEXT: .Lpcrel_hi4: 340; RV32F-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W) 341; RV32F-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi4)(a0) 342; RV32F-MEDIUM-NEXT: lw a0, 0(a0) 343; RV32F-MEDIUM-NEXT: ret 344; 345; RV64I-SMALL-LABEL: lower_extern_weak: 346; RV64I-SMALL: # %bb.0: 347; RV64I-SMALL-NEXT: lui a0, %hi(W) 348; RV64I-SMALL-NEXT: lw a0, %lo(W)(a0) 349; RV64I-SMALL-NEXT: ret 350; 351; RV64F-MEDIUM-LABEL: lower_extern_weak: 352; RV64F-MEDIUM: # %bb.0: 353; RV64F-MEDIUM-NEXT: .Lpcrel_hi4: 354; RV64F-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W) 355; RV64F-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0) 356; RV64F-MEDIUM-NEXT: lw a0, 0(a0) 357; RV64F-MEDIUM-NEXT: ret 358; 359; RV64F-LARGE-LABEL: lower_extern_weak: 360; RV64F-LARGE: # %bb.0: 361; RV64F-LARGE-NEXT: .Lpcrel_hi4: 362; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI4_0) 363; RV64F-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0) 364; RV64F-LARGE-NEXT: lw a0, 0(a0) 365; RV64F-LARGE-NEXT: ret 366; 367; RV32FINX-MEDIUM-LABEL: lower_extern_weak: 368; RV32FINX-MEDIUM: # %bb.0: 369; RV32FINX-MEDIUM-NEXT: .Lpcrel_hi3: 370; RV32FINX-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W) 371; RV32FINX-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi3)(a0) 372; RV32FINX-MEDIUM-NEXT: lw a0, 0(a0) 373; RV32FINX-MEDIUM-NEXT: ret 374; 375; RV64FINX-MEDIUM-LABEL: lower_extern_weak: 376; RV64FINX-MEDIUM: # %bb.0: 377; RV64FINX-MEDIUM-NEXT: .Lpcrel_hi3: 378; RV64FINX-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W) 379; RV64FINX-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0) 380; RV64FINX-MEDIUM-NEXT: lw a0, 0(a0) 381; RV64FINX-MEDIUM-NEXT: ret 382; 383; RV64FINX-LARGE-LABEL: lower_extern_weak: 384; RV64FINX-LARGE: # %bb.0: 385; RV64FINX-LARGE-NEXT: .Lpcrel_hi3: 386; RV64FINX-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI4_0) 387; RV64FINX-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0) 388; RV64FINX-LARGE-NEXT: lw a0, 0(a0) 389; RV64FINX-LARGE-NEXT: ret 390 %1 = load volatile i32, ptr @W 391 ret i32 %1 392} 393 394@X = global half 1.5 395 396define half @lower_global_half(half %a) nounwind { 397; RV32F-SMALL-LABEL: lower_global_half: 398; RV32F-SMALL: # %bb.0: 399; RV32F-SMALL-NEXT: lui a0, %hi(X) 400; RV32F-SMALL-NEXT: flh fa5, %lo(X)(a0) 401; RV32F-SMALL-NEXT: fadd.h fa0, fa0, fa5 402; RV32F-SMALL-NEXT: ret 403; 404; RV32F-MEDIUM-LABEL: lower_global_half: 405; RV32F-MEDIUM: # %bb.0: 406; RV32F-MEDIUM-NEXT: .Lpcrel_hi5: 407; RV32F-MEDIUM-NEXT: auipc a0, %pcrel_hi(X) 408; RV32F-MEDIUM-NEXT: flh fa5, %pcrel_lo(.Lpcrel_hi5)(a0) 409; RV32F-MEDIUM-NEXT: fadd.h fa0, fa0, fa5 410; RV32F-MEDIUM-NEXT: ret 411; 412; RV64F-SMALL-LABEL: lower_global_half: 413; RV64F-SMALL: # %bb.0: 414; RV64F-SMALL-NEXT: lui a0, %hi(X) 415; RV64F-SMALL-NEXT: flh fa5, %lo(X)(a0) 416; RV64F-SMALL-NEXT: fadd.h fa0, fa0, fa5 417; RV64F-SMALL-NEXT: ret 418; 419; RV64F-MEDIUM-LABEL: lower_global_half: 420; RV64F-MEDIUM: # %bb.0: 421; RV64F-MEDIUM-NEXT: .Lpcrel_hi5: 422; RV64F-MEDIUM-NEXT: auipc a0, %pcrel_hi(X) 423; RV64F-MEDIUM-NEXT: flh fa5, %pcrel_lo(.Lpcrel_hi5)(a0) 424; RV64F-MEDIUM-NEXT: fadd.h fa0, fa0, fa5 425; RV64F-MEDIUM-NEXT: ret 426; 427; RV64F-LARGE-LABEL: lower_global_half: 428; RV64F-LARGE: # %bb.0: 429; RV64F-LARGE-NEXT: .Lpcrel_hi5: 430; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI5_0) 431; RV64F-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi5)(a0) 432; RV64F-LARGE-NEXT: flh fa5, 0(a0) 433; RV64F-LARGE-NEXT: fadd.h fa0, fa0, fa5 434; RV64F-LARGE-NEXT: ret 435; 436; RV32FINX-SMALL-LABEL: lower_global_half: 437; RV32FINX-SMALL: # %bb.0: 438; RV32FINX-SMALL-NEXT: lui a1, %hi(X) 439; RV32FINX-SMALL-NEXT: lh a1, %lo(X)(a1) 440; RV32FINX-SMALL-NEXT: fadd.h a0, a0, a1 441; RV32FINX-SMALL-NEXT: ret 442; 443; RV32FINX-MEDIUM-LABEL: lower_global_half: 444; RV32FINX-MEDIUM: # %bb.0: 445; RV32FINX-MEDIUM-NEXT: .Lpcrel_hi4: 446; RV32FINX-MEDIUM-NEXT: auipc a1, %pcrel_hi(X) 447; RV32FINX-MEDIUM-NEXT: lh a1, %pcrel_lo(.Lpcrel_hi4)(a1) 448; RV32FINX-MEDIUM-NEXT: fadd.h a0, a0, a1 449; RV32FINX-MEDIUM-NEXT: ret 450; 451; RV64FINX-SMALL-LABEL: lower_global_half: 452; RV64FINX-SMALL: # %bb.0: 453; RV64FINX-SMALL-NEXT: lui a1, %hi(X) 454; RV64FINX-SMALL-NEXT: lh a1, %lo(X)(a1) 455; RV64FINX-SMALL-NEXT: fadd.h a0, a0, a1 456; RV64FINX-SMALL-NEXT: ret 457; 458; RV64FINX-MEDIUM-LABEL: lower_global_half: 459; RV64FINX-MEDIUM: # %bb.0: 460; RV64FINX-MEDIUM-NEXT: .Lpcrel_hi4: 461; RV64FINX-MEDIUM-NEXT: auipc a1, %pcrel_hi(X) 462; RV64FINX-MEDIUM-NEXT: lh a1, %pcrel_lo(.Lpcrel_hi4)(a1) 463; RV64FINX-MEDIUM-NEXT: fadd.h a0, a0, a1 464; RV64FINX-MEDIUM-NEXT: ret 465; 466; RV64FINX-LARGE-LABEL: lower_global_half: 467; RV64FINX-LARGE: # %bb.0: 468; RV64FINX-LARGE-NEXT: .Lpcrel_hi4: 469; RV64FINX-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI5_0) 470; RV64FINX-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi4)(a1) 471; RV64FINX-LARGE-NEXT: lh a1, 0(a1) 472; RV64FINX-LARGE-NEXT: fadd.h a0, a0, a1 473; RV64FINX-LARGE-NEXT: ret 474 %b = load half, ptr @X 475 %1 = fadd half %a, %b 476 ret half %1 477} 478