xref: /llvm-project/llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll (revision 2967e5f8007d873a3e9d97870d2461d0827a3976)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV64 %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64LP64F %s
6
7define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {
8; RV64-LABEL: callee_v2f32:
9; RV64:       # %bb.0:
10; RV64-NEXT:    fmv.w.x fa5, a2
11; RV64-NEXT:    fmv.w.x fa4, a0
12; RV64-NEXT:    fmv.w.x fa3, a3
13; RV64-NEXT:    fmv.w.x fa2, a1
14; RV64-NEXT:    fadd.s fa3, fa2, fa3
15; RV64-NEXT:    fadd.s fa5, fa4, fa5
16; RV64-NEXT:    fmv.x.w a0, fa5
17; RV64-NEXT:    fmv.x.w a1, fa3
18; RV64-NEXT:    ret
19;
20; RV64LP64F-LABEL: callee_v2f32:
21; RV64LP64F:       # %bb.0:
22; RV64LP64F-NEXT:    fadd.s fa0, fa0, fa2
23; RV64LP64F-NEXT:    fadd.s fa1, fa1, fa3
24; RV64LP64F-NEXT:    ret
25  %z = fadd <2 x float> %x, %y
26  ret <2 x float> %z
27}
28
29define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {
30; RV64-LABEL: callee_v4f32:
31; RV64:       # %bb.0:
32; RV64-NEXT:    fmv.w.x fa5, a4
33; RV64-NEXT:    fmv.w.x fa4, a7
34; RV64-NEXT:    fmv.w.x fa3, a3
35; RV64-NEXT:    fmv.w.x fa2, a6
36; RV64-NEXT:    fmv.w.x fa1, a2
37; RV64-NEXT:    fmv.w.x fa0, a5
38; RV64-NEXT:    fmv.w.x ft0, a1
39; RV64-NEXT:    flw ft1, 0(sp)
40; RV64-NEXT:    fadd.s fa0, ft0, fa0
41; RV64-NEXT:    fadd.s fa2, fa1, fa2
42; RV64-NEXT:    fadd.s fa4, fa3, fa4
43; RV64-NEXT:    fadd.s fa5, fa5, ft1
44; RV64-NEXT:    fsw fa0, 0(a0)
45; RV64-NEXT:    fsw fa2, 4(a0)
46; RV64-NEXT:    fsw fa4, 8(a0)
47; RV64-NEXT:    fsw fa5, 12(a0)
48; RV64-NEXT:    ret
49;
50; RV64LP64F-LABEL: callee_v4f32:
51; RV64LP64F:       # %bb.0:
52; RV64LP64F-NEXT:    fadd.s fa4, fa0, fa4
53; RV64LP64F-NEXT:    fadd.s fa5, fa1, fa5
54; RV64LP64F-NEXT:    fadd.s fa2, fa2, fa6
55; RV64LP64F-NEXT:    fadd.s fa3, fa3, fa7
56; RV64LP64F-NEXT:    fsw fa4, 0(a0)
57; RV64LP64F-NEXT:    fsw fa5, 4(a0)
58; RV64LP64F-NEXT:    fsw fa2, 8(a0)
59; RV64LP64F-NEXT:    fsw fa3, 12(a0)
60; RV64LP64F-NEXT:    ret
61  %z = fadd <4 x float> %x, %y
62  ret <4 x float> %z
63}
64