xref: /llvm-project/llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll (revision 2967e5f8007d873a3e9d97870d2461d0827a3976) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV64I-LP64E-FPELIM %s
4; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs -frame-pointer=all < %s \
5; RUN:   | FileCheck -check-prefix=RV64I-LP64E-WITHFP %s
6
7; This file contains tests that will have differing output for the lp64e ABIs.
8
9define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
10; RV64I-LP64E-FPELIM-LABEL: callee_float_in_regs:
11; RV64I-LP64E-FPELIM:       # %bb.0:
12; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -16
13; RV64I-LP64E-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
14; RV64I-LP64E-FPELIM-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
15; RV64I-LP64E-FPELIM-NEXT:    mv s0, a0
16; RV64I-LP64E-FPELIM-NEXT:    sext.w a0, a1
17; RV64I-LP64E-FPELIM-NEXT:    call __fixsfdi
18; RV64I-LP64E-FPELIM-NEXT:    add a0, s0, a0
19; RV64I-LP64E-FPELIM-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
20; RV64I-LP64E-FPELIM-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
21; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 16
22; RV64I-LP64E-FPELIM-NEXT:    ret
23;
24; RV64I-LP64E-WITHFP-LABEL: callee_float_in_regs:
25; RV64I-LP64E-WITHFP:       # %bb.0:
26; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -24
27; RV64I-LP64E-WITHFP-NEXT:    sd ra, 16(sp) # 8-byte Folded Spill
28; RV64I-LP64E-WITHFP-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
29; RV64I-LP64E-WITHFP-NEXT:    sd s1, 0(sp) # 8-byte Folded Spill
30; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 24
31; RV64I-LP64E-WITHFP-NEXT:    mv s1, a0
32; RV64I-LP64E-WITHFP-NEXT:    sext.w a0, a1
33; RV64I-LP64E-WITHFP-NEXT:    call __fixsfdi
34; RV64I-LP64E-WITHFP-NEXT:    add a0, s1, a0
35; RV64I-LP64E-WITHFP-NEXT:    ld ra, 16(sp) # 8-byte Folded Reload
36; RV64I-LP64E-WITHFP-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
37; RV64I-LP64E-WITHFP-NEXT:    ld s1, 0(sp) # 8-byte Folded Reload
38; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 24
39; RV64I-LP64E-WITHFP-NEXT:    ret
40  %b_fptosi = fptosi float %b to i64
41  %1 = add i64 %a, %b_fptosi
42  ret i64 %1
43}
44
45define i64 @caller_float_in_regs() nounwind {
46; RV64I-LP64E-FPELIM-LABEL: caller_float_in_regs:
47; RV64I-LP64E-FPELIM:       # %bb.0:
48; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -8
49; RV64I-LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
50; RV64I-LP64E-FPELIM-NEXT:    li a0, 1
51; RV64I-LP64E-FPELIM-NEXT:    lui a1, 262144
52; RV64I-LP64E-FPELIM-NEXT:    call callee_float_in_regs
53; RV64I-LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
54; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 8
55; RV64I-LP64E-FPELIM-NEXT:    ret
56;
57; RV64I-LP64E-WITHFP-LABEL: caller_float_in_regs:
58; RV64I-LP64E-WITHFP:       # %bb.0:
59; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
60; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
61; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
62; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
63; RV64I-LP64E-WITHFP-NEXT:    li a0, 1
64; RV64I-LP64E-WITHFP-NEXT:    lui a1, 262144
65; RV64I-LP64E-WITHFP-NEXT:    call callee_float_in_regs
66; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
67; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
68; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
69; RV64I-LP64E-WITHFP-NEXT:    ret
70  %1 = call i64 @callee_float_in_regs(i64 1, float 2.0)
71  ret i64 %1
72}
73
74define i64 @callee_float_on_stack(i128 %a, i128 %b, i128 %c, i128 %d, float %e) nounwind {
75; RV64I-LP64E-FPELIM-LABEL: callee_float_on_stack:
76; RV64I-LP64E-FPELIM:       # %bb.0:
77; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -16
78; RV64I-LP64E-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
79; RV64I-LP64E-FPELIM-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
80; RV64I-LP64E-FPELIM-NEXT:    addi s0, sp, 16
81; RV64I-LP64E-FPELIM-NEXT:    andi sp, sp, -16
82; RV64I-LP64E-FPELIM-NEXT:    lw a0, 16(s0)
83; RV64I-LP64E-FPELIM-NEXT:    addi sp, s0, -16
84; RV64I-LP64E-FPELIM-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
85; RV64I-LP64E-FPELIM-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
86; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 16
87; RV64I-LP64E-FPELIM-NEXT:    ret
88;
89; RV64I-LP64E-WITHFP-LABEL: callee_float_on_stack:
90; RV64I-LP64E-WITHFP:       # %bb.0:
91; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
92; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
93; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
94; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
95; RV64I-LP64E-WITHFP-NEXT:    andi sp, sp, -16
96; RV64I-LP64E-WITHFP-NEXT:    lw a0, 16(s0)
97; RV64I-LP64E-WITHFP-NEXT:    addi sp, s0, -16
98; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
99; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
100; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
101; RV64I-LP64E-WITHFP-NEXT:    ret
102  %1 = trunc i128 %d to i64
103  %2 = bitcast float %e to i32
104  %3 = sext i32 %2 to i64
105  %4 = add i64 %1, %3
106  ret i64 %3
107}
108
109define i64 @caller_float_on_stack() nounwind {
110; RV64I-LP64E-FPELIM-LABEL: caller_float_on_stack:
111; RV64I-LP64E-FPELIM:       # %bb.0:
112; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -48
113; RV64I-LP64E-FPELIM-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
114; RV64I-LP64E-FPELIM-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
115; RV64I-LP64E-FPELIM-NEXT:    addi s0, sp, 48
116; RV64I-LP64E-FPELIM-NEXT:    andi sp, sp, -16
117; RV64I-LP64E-FPELIM-NEXT:    lui a1, 264704
118; RV64I-LP64E-FPELIM-NEXT:    li a3, 4
119; RV64I-LP64E-FPELIM-NEXT:    li a0, 1
120; RV64I-LP64E-FPELIM-NEXT:    li a2, 2
121; RV64I-LP64E-FPELIM-NEXT:    li a4, 3
122; RV64I-LP64E-FPELIM-NEXT:    sd a3, 0(sp)
123; RV64I-LP64E-FPELIM-NEXT:    sd zero, 8(sp)
124; RV64I-LP64E-FPELIM-NEXT:    sd a1, 16(sp)
125; RV64I-LP64E-FPELIM-NEXT:    li a1, 0
126; RV64I-LP64E-FPELIM-NEXT:    li a3, 0
127; RV64I-LP64E-FPELIM-NEXT:    li a5, 0
128; RV64I-LP64E-FPELIM-NEXT:    call callee_float_on_stack
129; RV64I-LP64E-FPELIM-NEXT:    addi sp, s0, -48
130; RV64I-LP64E-FPELIM-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
131; RV64I-LP64E-FPELIM-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
132; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 48
133; RV64I-LP64E-FPELIM-NEXT:    ret
134;
135; RV64I-LP64E-WITHFP-LABEL: caller_float_on_stack:
136; RV64I-LP64E-WITHFP:       # %bb.0:
137; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -48
138; RV64I-LP64E-WITHFP-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
139; RV64I-LP64E-WITHFP-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
140; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 48
141; RV64I-LP64E-WITHFP-NEXT:    andi sp, sp, -16
142; RV64I-LP64E-WITHFP-NEXT:    lui a1, 264704
143; RV64I-LP64E-WITHFP-NEXT:    li a3, 4
144; RV64I-LP64E-WITHFP-NEXT:    li a0, 1
145; RV64I-LP64E-WITHFP-NEXT:    li a2, 2
146; RV64I-LP64E-WITHFP-NEXT:    li a4, 3
147; RV64I-LP64E-WITHFP-NEXT:    sd a3, 0(sp)
148; RV64I-LP64E-WITHFP-NEXT:    sd zero, 8(sp)
149; RV64I-LP64E-WITHFP-NEXT:    sd a1, 16(sp)
150; RV64I-LP64E-WITHFP-NEXT:    li a1, 0
151; RV64I-LP64E-WITHFP-NEXT:    li a3, 0
152; RV64I-LP64E-WITHFP-NEXT:    li a5, 0
153; RV64I-LP64E-WITHFP-NEXT:    call callee_float_on_stack
154; RV64I-LP64E-WITHFP-NEXT:    addi sp, s0, -48
155; RV64I-LP64E-WITHFP-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
156; RV64I-LP64E-WITHFP-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
157; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 48
158; RV64I-LP64E-WITHFP-NEXT:    ret
159  %1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
160  ret i64 %1
161}
162
163define float @callee_tiny_scalar_ret() nounwind {
164; RV64I-LP64E-FPELIM-LABEL: callee_tiny_scalar_ret:
165; RV64I-LP64E-FPELIM:       # %bb.0:
166; RV64I-LP64E-FPELIM-NEXT:    lui a0, 260096
167; RV64I-LP64E-FPELIM-NEXT:    ret
168;
169; RV64I-LP64E-WITHFP-LABEL: callee_tiny_scalar_ret:
170; RV64I-LP64E-WITHFP:       # %bb.0:
171; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
172; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
173; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
174; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
175; RV64I-LP64E-WITHFP-NEXT:    lui a0, 260096
176; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
177; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
178; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
179; RV64I-LP64E-WITHFP-NEXT:    ret
180  ret float 1.0
181}
182
183; The sign extension of the float return is necessary, as softened floats are
184; passed anyext.
185
186define i64 @caller_tiny_scalar_ret() nounwind {
187; RV64I-LP64E-FPELIM-LABEL: caller_tiny_scalar_ret:
188; RV64I-LP64E-FPELIM:       # %bb.0:
189; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -8
190; RV64I-LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
191; RV64I-LP64E-FPELIM-NEXT:    call callee_tiny_scalar_ret
192; RV64I-LP64E-FPELIM-NEXT:    sext.w a0, a0
193; RV64I-LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
194; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 8
195; RV64I-LP64E-FPELIM-NEXT:    ret
196;
197; RV64I-LP64E-WITHFP-LABEL: caller_tiny_scalar_ret:
198; RV64I-LP64E-WITHFP:       # %bb.0:
199; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
200; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
201; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
202; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
203; RV64I-LP64E-WITHFP-NEXT:    call callee_tiny_scalar_ret
204; RV64I-LP64E-WITHFP-NEXT:    sext.w a0, a0
205; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
206; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
207; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
208; RV64I-LP64E-WITHFP-NEXT:    ret
209  %1 = call float @callee_tiny_scalar_ret()
210  %2 = bitcast float %1 to i32
211  %3 = sext i32 %2 to i64
212  ret i64 %3
213}
214