xref: /llvm-project/llvm/test/CodeGen/RISCV/bswap-shift.ll (revision 4477500533281c90c6ce70eb87271f61fd6a415f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefixes=RV32ZB
4; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefixes=RV64ZB
6; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefixes=RV32ZB
8; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
9; RUN:   | FileCheck %s -check-prefixes=RV64ZB
10
11; TODO: These tests can be optmised, with x%8 == 0
12;       fold (bswap(srl (bswap c), x)) -> (shl c, x)
13;       fold (bswap(shl (bswap c), x)) -> (srl c, x)
14
15declare i16 @llvm.bswap.i16(i16)
16declare i32 @llvm.bswap.i32(i32)
17declare i64 @llvm.bswap.i64(i64)
18
19define i16 @test_bswap_srli_7_bswap_i16(i16 %a) nounwind {
20; RV32ZB-LABEL: test_bswap_srli_7_bswap_i16:
21; RV32ZB:       # %bb.0:
22; RV32ZB-NEXT:    rev8 a0, a0
23; RV32ZB-NEXT:    srli a0, a0, 23
24; RV32ZB-NEXT:    rev8 a0, a0
25; RV32ZB-NEXT:    srli a0, a0, 16
26; RV32ZB-NEXT:    ret
27;
28; RV64ZB-LABEL: test_bswap_srli_7_bswap_i16:
29; RV64ZB:       # %bb.0:
30; RV64ZB-NEXT:    rev8 a0, a0
31; RV64ZB-NEXT:    srli a0, a0, 55
32; RV64ZB-NEXT:    rev8 a0, a0
33; RV64ZB-NEXT:    srli a0, a0, 48
34; RV64ZB-NEXT:    ret
35    %1 = call i16 @llvm.bswap.i16(i16 %a)
36    %2 = lshr i16 %1, 7
37    %3 = call i16 @llvm.bswap.i16(i16 %2)
38    ret i16 %3
39}
40
41define i16 @test_bswap_srli_8_bswap_i16(i16 %a) nounwind {
42; RV32ZB-LABEL: test_bswap_srli_8_bswap_i16:
43; RV32ZB:       # %bb.0:
44; RV32ZB-NEXT:    slli a0, a0, 8
45; RV32ZB-NEXT:    ret
46;
47; RV64ZB-LABEL: test_bswap_srli_8_bswap_i16:
48; RV64ZB:       # %bb.0:
49; RV64ZB-NEXT:    slli a0, a0, 8
50; RV64ZB-NEXT:    ret
51    %1 = call i16 @llvm.bswap.i16(i16 %a)
52    %2 = lshr i16 %1, 8
53    %3 = call i16 @llvm.bswap.i16(i16 %2)
54    ret i16 %3
55}
56
57define i32 @test_bswap_srli_8_bswap_i32(i32 %a) nounwind {
58; RV32ZB-LABEL: test_bswap_srli_8_bswap_i32:
59; RV32ZB:       # %bb.0:
60; RV32ZB-NEXT:    slli a0, a0, 8
61; RV32ZB-NEXT:    ret
62;
63; RV64ZB-LABEL: test_bswap_srli_8_bswap_i32:
64; RV64ZB:       # %bb.0:
65; RV64ZB-NEXT:    slliw a0, a0, 8
66; RV64ZB-NEXT:    ret
67    %1 = call i32 @llvm.bswap.i32(i32 %a)
68    %2 = lshr i32 %1, 8
69    %3 = call i32 @llvm.bswap.i32(i32 %2)
70    ret i32 %3
71}
72
73define i32 @test_bswap_srli_16_bswap_i32(i32 %a) nounwind {
74; RV32ZB-LABEL: test_bswap_srli_16_bswap_i32:
75; RV32ZB:       # %bb.0:
76; RV32ZB-NEXT:    slli a0, a0, 16
77; RV32ZB-NEXT:    ret
78;
79; RV64ZB-LABEL: test_bswap_srli_16_bswap_i32:
80; RV64ZB:       # %bb.0:
81; RV64ZB-NEXT:    slliw a0, a0, 16
82; RV64ZB-NEXT:    ret
83    %1 = call i32 @llvm.bswap.i32(i32 %a)
84    %2 = lshr i32 %1, 16
85    %3 = call i32 @llvm.bswap.i32(i32 %2)
86    ret i32 %3
87}
88
89define i32 @test_bswap_srli_24_bswap_i32(i32 %a) nounwind {
90; RV32ZB-LABEL: test_bswap_srli_24_bswap_i32:
91; RV32ZB:       # %bb.0:
92; RV32ZB-NEXT:    slli a0, a0, 24
93; RV32ZB-NEXT:    ret
94;
95; RV64ZB-LABEL: test_bswap_srli_24_bswap_i32:
96; RV64ZB:       # %bb.0:
97; RV64ZB-NEXT:    slliw a0, a0, 24
98; RV64ZB-NEXT:    ret
99    %1 = call i32 @llvm.bswap.i32(i32 %a)
100    %2 = lshr i32 %1, 24
101    %3 = call i32 @llvm.bswap.i32(i32 %2)
102    ret i32 %3
103}
104
105define i64 @test_bswap_srli_48_bswap_i64(i64 %a) nounwind {
106; RV32ZB-LABEL: test_bswap_srli_48_bswap_i64:
107; RV32ZB:       # %bb.0:
108; RV32ZB-NEXT:    slli a1, a0, 16
109; RV32ZB-NEXT:    li a0, 0
110; RV32ZB-NEXT:    ret
111;
112; RV64ZB-LABEL: test_bswap_srli_48_bswap_i64:
113; RV64ZB:       # %bb.0:
114; RV64ZB-NEXT:    slli a0, a0, 48
115; RV64ZB-NEXT:    ret
116    %1 = call i64 @llvm.bswap.i64(i64 %a)
117    %2 = lshr i64 %1, 48
118    %3 = call i64 @llvm.bswap.i64(i64 %2)
119    ret i64 %3
120}
121
122define i16 @test_bswap_shli_7_bswap_i16(i16 %a) nounwind {
123; RV32ZB-LABEL: test_bswap_shli_7_bswap_i16:
124; RV32ZB:       # %bb.0:
125; RV32ZB-NEXT:    rev8 a0, a0
126; RV32ZB-NEXT:    srli a0, a0, 16
127; RV32ZB-NEXT:    slli a0, a0, 7
128; RV32ZB-NEXT:    rev8 a0, a0
129; RV32ZB-NEXT:    srli a0, a0, 16
130; RV32ZB-NEXT:    ret
131;
132; RV64ZB-LABEL: test_bswap_shli_7_bswap_i16:
133; RV64ZB:       # %bb.0:
134; RV64ZB-NEXT:    rev8 a0, a0
135; RV64ZB-NEXT:    srli a0, a0, 48
136; RV64ZB-NEXT:    slli a0, a0, 7
137; RV64ZB-NEXT:    rev8 a0, a0
138; RV64ZB-NEXT:    srli a0, a0, 48
139; RV64ZB-NEXT:    ret
140    %1 = call i16 @llvm.bswap.i16(i16 %a)
141    %2 = shl i16 %1, 7
142    %3 = call i16 @llvm.bswap.i16(i16 %2)
143    ret i16 %3
144}
145
146define i16 @test_bswap_shli_8_bswap_i16(i16 %a) nounwind {
147; RV32ZB-LABEL: test_bswap_shli_8_bswap_i16:
148; RV32ZB:       # %bb.0:
149; RV32ZB-NEXT:    slli a0, a0, 16
150; RV32ZB-NEXT:    srli a0, a0, 24
151; RV32ZB-NEXT:    ret
152;
153; RV64ZB-LABEL: test_bswap_shli_8_bswap_i16:
154; RV64ZB:       # %bb.0:
155; RV64ZB-NEXT:    slli a0, a0, 48
156; RV64ZB-NEXT:    srli a0, a0, 56
157; RV64ZB-NEXT:    ret
158    %1 = call i16 @llvm.bswap.i16(i16 %a)
159    %2 = shl i16 %1, 8
160    %3 = call i16 @llvm.bswap.i16(i16 %2)
161    ret i16 %3
162}
163
164define i32 @test_bswap_shli_8_bswap_i32(i32 %a) nounwind {
165; RV32ZB-LABEL: test_bswap_shli_8_bswap_i32:
166; RV32ZB:       # %bb.0:
167; RV32ZB-NEXT:    srli a0, a0, 8
168; RV32ZB-NEXT:    ret
169;
170; RV64ZB-LABEL: test_bswap_shli_8_bswap_i32:
171; RV64ZB:       # %bb.0:
172; RV64ZB-NEXT:    srliw a0, a0, 8
173; RV64ZB-NEXT:    ret
174    %1 = call i32 @llvm.bswap.i32(i32 %a)
175    %2 = shl i32 %1, 8
176    %3 = call i32 @llvm.bswap.i32(i32 %2)
177    ret i32 %3
178}
179
180define i32 @test_bswap_shli_16_bswap_i32(i32 %a) nounwind {
181; RV32ZB-LABEL: test_bswap_shli_16_bswap_i32:
182; RV32ZB:       # %bb.0:
183; RV32ZB-NEXT:    srli a0, a0, 16
184; RV32ZB-NEXT:    ret
185;
186; RV64ZB-LABEL: test_bswap_shli_16_bswap_i32:
187; RV64ZB:       # %bb.0:
188; RV64ZB-NEXT:    srliw a0, a0, 16
189; RV64ZB-NEXT:    ret
190    %1 = call i32 @llvm.bswap.i32(i32 %a)
191    %2 = shl i32 %1, 16
192    %3 = call i32 @llvm.bswap.i32(i32 %2)
193    ret i32 %3
194}
195
196define i32 @test_bswap_shli_24_bswap_i32(i32 %a) nounwind {
197; RV32ZB-LABEL: test_bswap_shli_24_bswap_i32:
198; RV32ZB:       # %bb.0:
199; RV32ZB-NEXT:    srli a0, a0, 24
200; RV32ZB-NEXT:    ret
201;
202; RV64ZB-LABEL: test_bswap_shli_24_bswap_i32:
203; RV64ZB:       # %bb.0:
204; RV64ZB-NEXT:    srliw a0, a0, 24
205; RV64ZB-NEXT:    ret
206    %1 = call i32 @llvm.bswap.i32(i32 %a)
207    %2 = shl i32 %1, 24
208    %3 = call i32 @llvm.bswap.i32(i32 %2)
209    ret i32 %3
210}
211
212define i64 @test_bswap_shli_48_bswap_i64(i64 %a) nounwind {
213; RV32ZB-LABEL: test_bswap_shli_48_bswap_i64:
214; RV32ZB:       # %bb.0:
215; RV32ZB-NEXT:    srli a0, a1, 16
216; RV32ZB-NEXT:    li a1, 0
217; RV32ZB-NEXT:    ret
218;
219; RV64ZB-LABEL: test_bswap_shli_48_bswap_i64:
220; RV64ZB:       # %bb.0:
221; RV64ZB-NEXT:    srli a0, a0, 48
222; RV64ZB-NEXT:    ret
223    %1 = call i64 @llvm.bswap.i64(i64 %a)
224    %2 = shl i64 %1, 48
225    %3 = call i64 @llvm.bswap.i64(i64 %2)
226    ret i64 %3
227}
228