xref: /llvm-project/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll (revision 1c874bbbd67c5795113fa307512ea514f06dac29)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck %s
6
7define bfloat @select_icmp_eq(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
8; CHECK-LABEL: select_icmp_eq:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    beq a0, a1, .LBB0_2
11; CHECK-NEXT:  # %bb.1:
12; CHECK-NEXT:    fmv.s fa0, fa1
13; CHECK-NEXT:  .LBB0_2:
14; CHECK-NEXT:    ret
15  %1 = icmp eq i32 %a, %b
16  %2 = select i1 %1, bfloat %c, bfloat %d
17  ret bfloat %2
18}
19
20define bfloat @select_icmp_ne(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
21; CHECK-LABEL: select_icmp_ne:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    bne a0, a1, .LBB1_2
24; CHECK-NEXT:  # %bb.1:
25; CHECK-NEXT:    fmv.s fa0, fa1
26; CHECK-NEXT:  .LBB1_2:
27; CHECK-NEXT:    ret
28  %1 = icmp ne i32 %a, %b
29  %2 = select i1 %1, bfloat %c, bfloat %d
30  ret bfloat %2
31}
32
33define bfloat @select_icmp_ugt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
34; CHECK-LABEL: select_icmp_ugt:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    bltu a1, a0, .LBB2_2
37; CHECK-NEXT:  # %bb.1:
38; CHECK-NEXT:    fmv.s fa0, fa1
39; CHECK-NEXT:  .LBB2_2:
40; CHECK-NEXT:    ret
41  %1 = icmp ugt i32 %a, %b
42  %2 = select i1 %1, bfloat %c, bfloat %d
43  ret bfloat %2
44}
45
46define bfloat @select_icmp_uge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
47; CHECK-LABEL: select_icmp_uge:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    bgeu a0, a1, .LBB3_2
50; CHECK-NEXT:  # %bb.1:
51; CHECK-NEXT:    fmv.s fa0, fa1
52; CHECK-NEXT:  .LBB3_2:
53; CHECK-NEXT:    ret
54  %1 = icmp uge i32 %a, %b
55  %2 = select i1 %1, bfloat %c, bfloat %d
56  ret bfloat %2
57}
58
59define bfloat @select_icmp_ult(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
60; CHECK-LABEL: select_icmp_ult:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    bltu a0, a1, .LBB4_2
63; CHECK-NEXT:  # %bb.1:
64; CHECK-NEXT:    fmv.s fa0, fa1
65; CHECK-NEXT:  .LBB4_2:
66; CHECK-NEXT:    ret
67  %1 = icmp ult i32 %a, %b
68  %2 = select i1 %1, bfloat %c, bfloat %d
69  ret bfloat %2
70}
71
72define bfloat @select_icmp_ule(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
73; CHECK-LABEL: select_icmp_ule:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    bgeu a1, a0, .LBB5_2
76; CHECK-NEXT:  # %bb.1:
77; CHECK-NEXT:    fmv.s fa0, fa1
78; CHECK-NEXT:  .LBB5_2:
79; CHECK-NEXT:    ret
80  %1 = icmp ule i32 %a, %b
81  %2 = select i1 %1, bfloat %c, bfloat %d
82  ret bfloat %2
83}
84
85define bfloat @select_icmp_sgt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
86; CHECK-LABEL: select_icmp_sgt:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    blt a1, a0, .LBB6_2
89; CHECK-NEXT:  # %bb.1:
90; CHECK-NEXT:    fmv.s fa0, fa1
91; CHECK-NEXT:  .LBB6_2:
92; CHECK-NEXT:    ret
93  %1 = icmp sgt i32 %a, %b
94  %2 = select i1 %1, bfloat %c, bfloat %d
95  ret bfloat %2
96}
97
98define bfloat @select_icmp_sge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
99; CHECK-LABEL: select_icmp_sge:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    bge a0, a1, .LBB7_2
102; CHECK-NEXT:  # %bb.1:
103; CHECK-NEXT:    fmv.s fa0, fa1
104; CHECK-NEXT:  .LBB7_2:
105; CHECK-NEXT:    ret
106  %1 = icmp sge i32 %a, %b
107  %2 = select i1 %1, bfloat %c, bfloat %d
108  ret bfloat %2
109}
110
111define bfloat @select_icmp_slt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
112; CHECK-LABEL: select_icmp_slt:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    blt a0, a1, .LBB8_2
115; CHECK-NEXT:  # %bb.1:
116; CHECK-NEXT:    fmv.s fa0, fa1
117; CHECK-NEXT:  .LBB8_2:
118; CHECK-NEXT:    ret
119  %1 = icmp slt i32 %a, %b
120  %2 = select i1 %1, bfloat %c, bfloat %d
121  ret bfloat %2
122}
123
124define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
125; CHECK-LABEL: select_icmp_sle:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    bge a1, a0, .LBB9_2
128; CHECK-NEXT:  # %bb.1:
129; CHECK-NEXT:    fmv.s fa0, fa1
130; CHECK-NEXT:  .LBB9_2:
131; CHECK-NEXT:    ret
132  %1 = icmp sle i32 %a, %b
133  %2 = select i1 %1, bfloat %c, bfloat %d
134  ret bfloat %2
135}
136
137define bfloat @select_icmp_slt_one(i32 signext %a) {
138; CHECK-LABEL: select_icmp_slt_one:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    slti a0, a0, 1
141; CHECK-NEXT:    fcvt.s.w fa5, a0
142; CHECK-NEXT:    fcvt.bf16.s fa0, fa5
143; CHECK-NEXT:    ret
144  %1 = icmp slt i32 %a, 1
145  %2 = select i1 %1, bfloat 1.000000e+00, bfloat 0.000000e+00
146  ret bfloat %2
147}
148
149define bfloat @select_icmp_sgt_zero(i32 signext %a) {
150; CHECK-LABEL: select_icmp_sgt_zero:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    slti a0, a0, 1
153; CHECK-NEXT:    fcvt.s.w fa5, a0
154; CHECK-NEXT:    fcvt.bf16.s fa0, fa5
155; CHECK-NEXT:    ret
156  %1 = icmp sgt i32 %a, 0
157  %2 = select i1 %1, bfloat 0.000000e+00, bfloat 1.000000e+00
158  ret bfloat %2
159}
160