1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \ 3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFBFMIN %s 4; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \ 5; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFBFMIN %s 6 7define bfloat @frem_bf16(bfloat %a, bfloat %b) nounwind { 8; RV32IZFBFMIN-LABEL: frem_bf16: 9; RV32IZFBFMIN: # %bb.0: 10; RV32IZFBFMIN-NEXT: addi sp, sp, -16 11; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 12; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 13; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa1, fa1 14; RV32IZFBFMIN-NEXT: call fmodf 15; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0 16; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 17; RV32IZFBFMIN-NEXT: addi sp, sp, 16 18; RV32IZFBFMIN-NEXT: ret 19; 20; RV64IZFBFMIN-LABEL: frem_bf16: 21; RV64IZFBFMIN: # %bb.0: 22; RV64IZFBFMIN-NEXT: addi sp, sp, -16 23; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 24; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0 25; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa1, fa1 26; RV64IZFBFMIN-NEXT: call fmodf 27; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0 28; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 29; RV64IZFBFMIN-NEXT: addi sp, sp, 16 30; RV64IZFBFMIN-NEXT: ret 31 %1 = frem bfloat %a, %b 32 ret bfloat %1 33} 34