xref: /llvm-project/llvm/test/CodeGen/RISCV/bfloat-fcmp.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck %s
6
7define i32 @fcmp_false(bfloat %a, bfloat %b) nounwind {
8; CHECK-LABEL: fcmp_false:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    li a0, 0
11; CHECK-NEXT:    ret
12  %1 = fcmp false bfloat %a, %b
13  %2 = zext i1 %1 to i32
14  ret i32 %2
15}
16
17define i32 @fcmp_oeq(bfloat %a, bfloat %b) nounwind {
18; CHECK-LABEL: fcmp_oeq:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
21; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
22; CHECK-NEXT:    feq.s a0, fa4, fa5
23; CHECK-NEXT:    ret
24  %1 = fcmp oeq bfloat %a, %b
25  %2 = zext i1 %1 to i32
26  ret i32 %2
27}
28
29define i32 @fcmp_ogt(bfloat %a, bfloat %b) nounwind {
30; CHECK-LABEL: fcmp_ogt:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    fcvt.s.bf16 fa5, fa0
33; CHECK-NEXT:    fcvt.s.bf16 fa4, fa1
34; CHECK-NEXT:    flt.s a0, fa4, fa5
35; CHECK-NEXT:    ret
36  %1 = fcmp ogt bfloat %a, %b
37  %2 = zext i1 %1 to i32
38  ret i32 %2
39}
40
41define i32 @fcmp_oge(bfloat %a, bfloat %b) nounwind {
42; CHECK-LABEL: fcmp_oge:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    fcvt.s.bf16 fa5, fa0
45; CHECK-NEXT:    fcvt.s.bf16 fa4, fa1
46; CHECK-NEXT:    fle.s a0, fa4, fa5
47; CHECK-NEXT:    ret
48  %1 = fcmp oge bfloat %a, %b
49  %2 = zext i1 %1 to i32
50  ret i32 %2
51}
52
53define i32 @fcmp_olt(bfloat %a, bfloat %b) nounwind {
54; CHECK-LABEL: fcmp_olt:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
57; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
58; CHECK-NEXT:    flt.s a0, fa4, fa5
59; CHECK-NEXT:    ret
60  %1 = fcmp olt bfloat %a, %b
61  %2 = zext i1 %1 to i32
62  ret i32 %2
63}
64
65define i32 @fcmp_ole(bfloat %a, bfloat %b) nounwind {
66; CHECK-LABEL: fcmp_ole:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
69; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
70; CHECK-NEXT:    fle.s a0, fa4, fa5
71; CHECK-NEXT:    ret
72  %1 = fcmp ole bfloat %a, %b
73  %2 = zext i1 %1 to i32
74  ret i32 %2
75}
76
77define i32 @fcmp_one(bfloat %a, bfloat %b) nounwind {
78; CHECK-LABEL: fcmp_one:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
81; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
82; CHECK-NEXT:    flt.s a0, fa4, fa5
83; CHECK-NEXT:    flt.s a1, fa5, fa4
84; CHECK-NEXT:    or a0, a1, a0
85; CHECK-NEXT:    ret
86  %1 = fcmp one bfloat %a, %b
87  %2 = zext i1 %1 to i32
88  ret i32 %2
89}
90
91define i32 @fcmp_ord(bfloat %a, bfloat %b) nounwind {
92; CHECK-LABEL: fcmp_ord:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
95; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
96; CHECK-NEXT:    feq.s a0, fa5, fa5
97; CHECK-NEXT:    feq.s a1, fa4, fa4
98; CHECK-NEXT:    and a0, a1, a0
99; CHECK-NEXT:    ret
100  %1 = fcmp ord bfloat %a, %b
101  %2 = zext i1 %1 to i32
102  ret i32 %2
103}
104
105define i32 @fcmp_ueq(bfloat %a, bfloat %b) nounwind {
106; CHECK-LABEL: fcmp_ueq:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
109; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
110; CHECK-NEXT:    flt.s a0, fa4, fa5
111; CHECK-NEXT:    flt.s a1, fa5, fa4
112; CHECK-NEXT:    or a0, a1, a0
113; CHECK-NEXT:    xori a0, a0, 1
114; CHECK-NEXT:    ret
115  %1 = fcmp ueq bfloat %a, %b
116  %2 = zext i1 %1 to i32
117  ret i32 %2
118}
119
120define i32 @fcmp_ugt(bfloat %a, bfloat %b) nounwind {
121; CHECK-LABEL: fcmp_ugt:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
124; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
125; CHECK-NEXT:    fle.s a0, fa4, fa5
126; CHECK-NEXT:    xori a0, a0, 1
127; CHECK-NEXT:    ret
128  %1 = fcmp ugt bfloat %a, %b
129  %2 = zext i1 %1 to i32
130  ret i32 %2
131}
132
133define i32 @fcmp_uge(bfloat %a, bfloat %b) nounwind {
134; CHECK-LABEL: fcmp_uge:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
137; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
138; CHECK-NEXT:    flt.s a0, fa4, fa5
139; CHECK-NEXT:    xori a0, a0, 1
140; CHECK-NEXT:    ret
141  %1 = fcmp uge bfloat %a, %b
142  %2 = zext i1 %1 to i32
143  ret i32 %2
144}
145
146define i32 @fcmp_ult(bfloat %a, bfloat %b) nounwind {
147; CHECK-LABEL: fcmp_ult:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    fcvt.s.bf16 fa5, fa0
150; CHECK-NEXT:    fcvt.s.bf16 fa4, fa1
151; CHECK-NEXT:    fle.s a0, fa4, fa5
152; CHECK-NEXT:    xori a0, a0, 1
153; CHECK-NEXT:    ret
154  %1 = fcmp ult bfloat %a, %b
155  %2 = zext i1 %1 to i32
156  ret i32 %2
157}
158
159define i32 @fcmp_ule(bfloat %a, bfloat %b) nounwind {
160; CHECK-LABEL: fcmp_ule:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    fcvt.s.bf16 fa5, fa0
163; CHECK-NEXT:    fcvt.s.bf16 fa4, fa1
164; CHECK-NEXT:    flt.s a0, fa4, fa5
165; CHECK-NEXT:    xori a0, a0, 1
166; CHECK-NEXT:    ret
167  %1 = fcmp ule bfloat %a, %b
168  %2 = zext i1 %1 to i32
169  ret i32 %2
170}
171
172define i32 @fcmp_une(bfloat %a, bfloat %b) nounwind {
173; CHECK-LABEL: fcmp_une:
174; CHECK:       # %bb.0:
175; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
176; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
177; CHECK-NEXT:    feq.s a0, fa4, fa5
178; CHECK-NEXT:    xori a0, a0, 1
179; CHECK-NEXT:    ret
180  %1 = fcmp une bfloat %a, %b
181  %2 = zext i1 %1 to i32
182  ret i32 %2
183}
184
185define i32 @fcmp_uno(bfloat %a, bfloat %b) nounwind {
186; CHECK-LABEL: fcmp_uno:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
189; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
190; CHECK-NEXT:    feq.s a0, fa5, fa5
191; CHECK-NEXT:    feq.s a1, fa4, fa4
192; CHECK-NEXT:    and a0, a1, a0
193; CHECK-NEXT:    xori a0, a0, 1
194; CHECK-NEXT:    ret
195  %1 = fcmp uno bfloat %a, %b
196  %2 = zext i1 %1 to i32
197  ret i32 %2
198}
199
200define i32 @fcmp_true(bfloat %a, bfloat %b) nounwind {
201; CHECK-LABEL: fcmp_true:
202; CHECK:       # %bb.0:
203; CHECK-NEXT:    li a0, 1
204; CHECK-NEXT:    ret
205  %1 = fcmp true bfloat %a, %b
206  %2 = zext i1 %1 to i32
207  ret i32 %2
208}
209