1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64I 6 7; Test for handling of AND with constant. If this constant exceeds simm12 and 8; also is a non-empty sequence of ones starting at the least significant bit 9; with the remainder zero, we can replace it with SLLI + SLRI 10 11define i32 @and32_0x7ff(i32 %x) { 12; RV32I-LABEL: and32_0x7ff: 13; RV32I: # %bb.0: 14; RV32I-NEXT: andi a0, a0, 2047 15; RV32I-NEXT: ret 16; 17; RV64I-LABEL: and32_0x7ff: 18; RV64I: # %bb.0: 19; RV64I-NEXT: andi a0, a0, 2047 20; RV64I-NEXT: ret 21 %a = and i32 %x, 2047 22 ret i32 %a 23} 24 25define i32 @and32_0xfff(i32 %x) { 26; RV32I-LABEL: and32_0xfff: 27; RV32I: # %bb.0: 28; RV32I-NEXT: slli a0, a0, 20 29; RV32I-NEXT: srli a0, a0, 20 30; RV32I-NEXT: ret 31; 32; RV64I-LABEL: and32_0xfff: 33; RV64I: # %bb.0: 34; RV64I-NEXT: slli a0, a0, 52 35; RV64I-NEXT: srli a0, a0, 52 36; RV64I-NEXT: ret 37 %a = and i32 %x, 4095 38 ret i32 %a 39} 40 41define i64 @and64_0x7ff(i64 %x) { 42; RV32I-LABEL: and64_0x7ff: 43; RV32I: # %bb.0: 44; RV32I-NEXT: andi a0, a0, 2047 45; RV32I-NEXT: li a1, 0 46; RV32I-NEXT: ret 47; 48; RV64I-LABEL: and64_0x7ff: 49; RV64I: # %bb.0: 50; RV64I-NEXT: andi a0, a0, 2047 51; RV64I-NEXT: ret 52 %a = and i64 %x, 2047 53 ret i64 %a 54} 55 56define i64 @and64_0xfff(i64 %x) { 57; RV32I-LABEL: and64_0xfff: 58; RV32I: # %bb.0: 59; RV32I-NEXT: slli a0, a0, 20 60; RV32I-NEXT: srli a0, a0, 20 61; RV32I-NEXT: li a1, 0 62; RV32I-NEXT: ret 63; 64; RV64I-LABEL: and64_0xfff: 65; RV64I: # %bb.0: 66; RV64I-NEXT: slli a0, a0, 52 67; RV64I-NEXT: srli a0, a0, 52 68; RV64I-NEXT: ret 69 %a = and i64 %x, 4095 70 ret i64 %a 71} 72 73; Test for handling of AND with constant. If this constant exceeds simm32 and 74; also is a non-empty sequence of ones starting at the most significant bit 75; with the remainder zero, we can replace it with SRLI + SLLI. 76 77define i32 @and32_0x7ffff000(i32 %x) { 78; RV32I-LABEL: and32_0x7ffff000: 79; RV32I: # %bb.0: 80; RV32I-NEXT: lui a1, 524287 81; RV32I-NEXT: and a0, a0, a1 82; RV32I-NEXT: ret 83; 84; RV64I-LABEL: and32_0x7ffff000: 85; RV64I: # %bb.0: 86; RV64I-NEXT: lui a1, 524287 87; RV64I-NEXT: and a0, a0, a1 88; RV64I-NEXT: ret 89 %a = and i32 %x, 2147479552 90 ret i32 %a 91} 92 93define i32 @and32_0xfffff000(i32 %x) { 94; RV32I-LABEL: and32_0xfffff000: 95; RV32I: # %bb.0: 96; RV32I-NEXT: lui a1, 1048575 97; RV32I-NEXT: and a0, a0, a1 98; RV32I-NEXT: ret 99; 100; RV64I-LABEL: and32_0xfffff000: 101; RV64I: # %bb.0: 102; RV64I-NEXT: lui a1, 1048575 103; RV64I-NEXT: and a0, a0, a1 104; RV64I-NEXT: ret 105 %a = and i32 %x, -4096 106 ret i32 %a 107} 108 109define i32 @and32_0xfffffa00(i32 %x) { 110; RV32I-LABEL: and32_0xfffffa00: 111; RV32I: # %bb.0: 112; RV32I-NEXT: andi a0, a0, -1536 113; RV32I-NEXT: ret 114; 115; RV64I-LABEL: and32_0xfffffa00: 116; RV64I: # %bb.0: 117; RV64I-NEXT: andi a0, a0, -1536 118; RV64I-NEXT: ret 119 %a = and i32 %x, -1536 120 ret i32 %a 121} 122 123define i64 @and64_0x7ffffffffffff000(i64 %x) { 124; RV32I-LABEL: and64_0x7ffffffffffff000: 125; RV32I: # %bb.0: 126; RV32I-NEXT: lui a2, 1048575 127; RV32I-NEXT: slli a1, a1, 1 128; RV32I-NEXT: and a0, a0, a2 129; RV32I-NEXT: srli a1, a1, 1 130; RV32I-NEXT: ret 131; 132; RV64I-LABEL: and64_0x7ffffffffffff000: 133; RV64I: # %bb.0: 134; RV64I-NEXT: lui a1, 1048574 135; RV64I-NEXT: srli a1, a1, 1 136; RV64I-NEXT: and a0, a0, a1 137; RV64I-NEXT: ret 138 %a = and i64 %x, 9223372036854771712 139 ret i64 %a 140} 141 142define i64 @and64_0xfffffffffffff000(i64 %x) { 143; RV32I-LABEL: and64_0xfffffffffffff000: 144; RV32I: # %bb.0: 145; RV32I-NEXT: lui a2, 1048575 146; RV32I-NEXT: and a0, a0, a2 147; RV32I-NEXT: ret 148; 149; RV64I-LABEL: and64_0xfffffffffffff000: 150; RV64I: # %bb.0: 151; RV64I-NEXT: lui a1, 1048575 152; RV64I-NEXT: and a0, a0, a1 153; RV64I-NEXT: ret 154 %a = and i64 %x, -4096 155 ret i64 %a 156} 157 158define i64 @and64_0xfffffffffffffa00(i64 %x) { 159; RV32I-LABEL: and64_0xfffffffffffffa00: 160; RV32I: # %bb.0: 161; RV32I-NEXT: andi a0, a0, -1536 162; RV32I-NEXT: ret 163; 164; RV64I-LABEL: and64_0xfffffffffffffa00: 165; RV64I: # %bb.0: 166; RV64I-NEXT: andi a0, a0, -1536 167; RV64I-NEXT: ret 168 %a = and i64 %x, -1536 169 ret i64 %a 170} 171 172define i64 @and64_0xffffffff00000000(i64 %x) { 173; RV32I-LABEL: and64_0xffffffff00000000: 174; RV32I: # %bb.0: 175; RV32I-NEXT: li a0, 0 176; RV32I-NEXT: ret 177; 178; RV64I-LABEL: and64_0xffffffff00000000: 179; RV64I: # %bb.0: 180; RV64I-NEXT: srli a0, a0, 32 181; RV64I-NEXT: slli a0, a0, 32 182; RV64I-NEXT: ret 183 %a = and i64 %x, -4294967296 184 ret i64 %a 185} 186 187define i64 @and64_0x7fffffff00000000(i64 %x) { 188; RV32I-LABEL: and64_0x7fffffff00000000: 189; RV32I: # %bb.0: 190; RV32I-NEXT: slli a1, a1, 1 191; RV32I-NEXT: srli a1, a1, 1 192; RV32I-NEXT: li a0, 0 193; RV32I-NEXT: ret 194; 195; RV64I-LABEL: and64_0x7fffffff00000000: 196; RV64I: # %bb.0: 197; RV64I-NEXT: lui a1, 524288 198; RV64I-NEXT: addi a1, a1, -1 199; RV64I-NEXT: slli a1, a1, 32 200; RV64I-NEXT: and a0, a0, a1 201; RV64I-NEXT: ret 202 %a = and i64 %x, 9223372032559808512 203 ret i64 %a 204} 205 206define i64 @and64_0xffffffff80000000(i64 %x) { 207; RV32I-LABEL: and64_0xffffffff80000000: 208; RV32I: # %bb.0: 209; RV32I-NEXT: lui a2, 524288 210; RV32I-NEXT: and a0, a0, a2 211; RV32I-NEXT: ret 212; 213; RV64I-LABEL: and64_0xffffffff80000000: 214; RV64I: # %bb.0: 215; RV64I-NEXT: lui a1, 524288 216; RV64I-NEXT: and a0, a0, a1 217; RV64I-NEXT: ret 218 %a = and i64 %x, -2147483648 219 ret i64 %a 220} 221 222define i64 @and64_0x00000000fffffff8(i64 %x) { 223; RV32I-LABEL: and64_0x00000000fffffff8: 224; RV32I: # %bb.0: 225; RV32I-NEXT: andi a0, a0, -8 226; RV32I-NEXT: li a1, 0 227; RV32I-NEXT: ret 228; 229; RV64I-LABEL: and64_0x00000000fffffff8: 230; RV64I: # %bb.0: 231; RV64I-NEXT: srliw a0, a0, 3 232; RV64I-NEXT: slli a0, a0, 3 233; RV64I-NEXT: ret 234 %a = and i64 %x, 4294967288 235 ret i64 %a 236} 237