xref: /llvm-project/llvm/test/CodeGen/RISCV/and-shl.ll (revision 22d26ae3040095c7bfe4e2f1678b9738bf81fd4a)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7define i32 @and_0xfff_shl_2(i32 %x) {
8; RV32I-LABEL: and_0xfff_shl_2:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    slli a0, a0, 20
11; RV32I-NEXT:    srli a0, a0, 18
12; RV32I-NEXT:    ret
13;
14; RV64I-LABEL: and_0xfff_shl_2:
15; RV64I:       # %bb.0:
16; RV64I-NEXT:    slli a0, a0, 52
17; RV64I-NEXT:    srli a0, a0, 50
18; RV64I-NEXT:    ret
19  %a = and i32 %x, 4095
20  %s = shl i32 %a, 2
21  ret i32 %s
22}
23
24define i32 @and_0x7ff_shl_2(i32 %x) {
25; RV32I-LABEL: and_0x7ff_shl_2:
26; RV32I:       # %bb.0:
27; RV32I-NEXT:    andi a0, a0, 2047
28; RV32I-NEXT:    slli a0, a0, 2
29; RV32I-NEXT:    ret
30;
31; RV64I-LABEL: and_0x7ff_shl_2:
32; RV64I:       # %bb.0:
33; RV64I-NEXT:    andi a0, a0, 2047
34; RV64I-NEXT:    slli a0, a0, 2
35; RV64I-NEXT:    ret
36  %a = and i32 %x, 2047
37  %s = shl i32 %a, 2
38  ret i32 %s
39}
40
41define i64 @and_0xffffffff_shl_2(i64 %x) {
42; RV32I-LABEL: and_0xffffffff_shl_2:
43; RV32I:       # %bb.0:
44; RV32I-NEXT:    slli a2, a0, 2
45; RV32I-NEXT:    srli a1, a0, 30
46; RV32I-NEXT:    mv a0, a2
47; RV32I-NEXT:    ret
48;
49; RV64I-LABEL: and_0xffffffff_shl_2:
50; RV64I:       # %bb.0:
51; RV64I-NEXT:    slli a0, a0, 32
52; RV64I-NEXT:    srli a0, a0, 30
53; RV64I-NEXT:    ret
54  %a = and i64 %x, 4294967295
55  %s = shl i64 %a, 2
56  ret i64 %s
57}
58
59define i32 @and_0xfff_shl_2_multi_use(i32 %x) {
60; RV32I-LABEL: and_0xfff_shl_2_multi_use:
61; RV32I:       # %bb.0:
62; RV32I-NEXT:    slli a0, a0, 20
63; RV32I-NEXT:    srli a0, a0, 20
64; RV32I-NEXT:    slli a1, a0, 2
65; RV32I-NEXT:    add a0, a0, a1
66; RV32I-NEXT:    ret
67;
68; RV64I-LABEL: and_0xfff_shl_2_multi_use:
69; RV64I:       # %bb.0:
70; RV64I-NEXT:    slli a0, a0, 52
71; RV64I-NEXT:    srli a0, a0, 52
72; RV64I-NEXT:    slli a1, a0, 2
73; RV64I-NEXT:    add a0, a0, a1
74; RV64I-NEXT:    ret
75  %a = and i32 %x, 4095
76  %s = shl i32 %a, 2
77  %r = add i32 %a, %s
78  ret i32 %r
79}
80