1*f48dab52SShao-Ce SUN; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*f48dab52SShao-Ce SUN; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3*f48dab52SShao-Ce SUN; RUN: | FileCheck -check-prefix=RV32I %s 4*f48dab52SShao-Ce SUN; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5*f48dab52SShao-Ce SUN; RUN: | FileCheck -check-prefix=RV64I %s 6*f48dab52SShao-Ce SUN 7*f48dab52SShao-Ce SUNdefine i24 @aext(i32 %0) { 8*f48dab52SShao-Ce SUN; RV32I-LABEL: aext: 9*f48dab52SShao-Ce SUN; RV32I: # %bb.0: 10*f48dab52SShao-Ce SUN; RV32I-NEXT: srli a0, a0, 8 11*f48dab52SShao-Ce SUN; RV32I-NEXT: ret 12*f48dab52SShao-Ce SUN; 13*f48dab52SShao-Ce SUN; RV64I-LABEL: aext: 14*f48dab52SShao-Ce SUN; RV64I: # %bb.0: 15*f48dab52SShao-Ce SUN; RV64I-NEXT: srliw a0, a0, 8 16*f48dab52SShao-Ce SUN; RV64I-NEXT: ret 17*f48dab52SShao-Ce SUN %2 = and i32 %0, -256 18*f48dab52SShao-Ce SUN %3 = lshr exact i32 %2, 8 19*f48dab52SShao-Ce SUN %4 = trunc i32 %3 to i24 20*f48dab52SShao-Ce SUN ret i24 %4 21*f48dab52SShao-Ce SUN} 22