xref: /llvm-project/llvm/test/CodeGen/RISCV/aext.ll (revision f48dab523784252448dbd42e72f0048ee0463368)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64I %s
6
7define i24 @aext(i32 %0) {
8; RV32I-LABEL: aext:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    srli a0, a0, 8
11; RV32I-NEXT:    ret
12;
13; RV64I-LABEL: aext:
14; RV64I:       # %bb.0:
15; RV64I-NEXT:    srliw a0, a0, 8
16; RV64I-NEXT:    ret
17  %2 = and i32 %0, -256
18  %3 = lshr exact i32 %2, 8
19  %4 = trunc i32 %3 to i24
20  ret i24 %4
21}
22