xref: /llvm-project/llvm/test/CodeGen/RISCV/addimm-mulimm.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;; Test that (mul (add x, c1), c2) can be transformed to
3;; (add (mul x, c2), c1*c2) if profitable.
4
5; RUN: llc -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs < %s \
6; RUN:   | FileCheck -check-prefix=RV32IMB %s
7; RUN: llc -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs < %s \
8; RUN:   | FileCheck -check-prefix=RV64IMB %s
9
10define i32 @add_mul_combine_accept_a1(i32 %x) {
11; RV32IMB-LABEL: add_mul_combine_accept_a1:
12; RV32IMB:       # %bb.0:
13; RV32IMB-NEXT:    sh1add a1, a0, a0
14; RV32IMB-NEXT:    slli a0, a0, 5
15; RV32IMB-NEXT:    sub a0, a0, a1
16; RV32IMB-NEXT:    addi a0, a0, 1073
17; RV32IMB-NEXT:    ret
18;
19; RV64IMB-LABEL: add_mul_combine_accept_a1:
20; RV64IMB:       # %bb.0:
21; RV64IMB-NEXT:    sh1add a1, a0, a0
22; RV64IMB-NEXT:    slli a0, a0, 5
23; RV64IMB-NEXT:    subw a0, a0, a1
24; RV64IMB-NEXT:    addiw a0, a0, 1073
25; RV64IMB-NEXT:    ret
26  %tmp0 = add i32 %x, 37
27  %tmp1 = mul i32 %tmp0, 29
28  ret i32 %tmp1
29}
30
31define signext i32 @add_mul_combine_accept_a2(i32 signext %x) {
32; RV32IMB-LABEL: add_mul_combine_accept_a2:
33; RV32IMB:       # %bb.0:
34; RV32IMB-NEXT:    sh1add a1, a0, a0
35; RV32IMB-NEXT:    slli a0, a0, 5
36; RV32IMB-NEXT:    sub a0, a0, a1
37; RV32IMB-NEXT:    addi a0, a0, 1073
38; RV32IMB-NEXT:    ret
39;
40; RV64IMB-LABEL: add_mul_combine_accept_a2:
41; RV64IMB:       # %bb.0:
42; RV64IMB-NEXT:    sh1add a1, a0, a0
43; RV64IMB-NEXT:    slli a0, a0, 5
44; RV64IMB-NEXT:    subw a0, a0, a1
45; RV64IMB-NEXT:    addiw a0, a0, 1073
46; RV64IMB-NEXT:    ret
47  %tmp0 = add i32 %x, 37
48  %tmp1 = mul i32 %tmp0, 29
49  ret i32 %tmp1
50}
51
52define i64 @add_mul_combine_accept_a3(i64 %x) {
53; RV32IMB-LABEL: add_mul_combine_accept_a3:
54; RV32IMB:       # %bb.0:
55; RV32IMB-NEXT:    li a2, 29
56; RV32IMB-NEXT:    sh1add a3, a1, a1
57; RV32IMB-NEXT:    slli a1, a1, 5
58; RV32IMB-NEXT:    sub a1, a1, a3
59; RV32IMB-NEXT:    sh1add a3, a0, a0
60; RV32IMB-NEXT:    mulhu a2, a0, a2
61; RV32IMB-NEXT:    slli a0, a0, 5
62; RV32IMB-NEXT:    sub a3, a0, a3
63; RV32IMB-NEXT:    add a1, a2, a1
64; RV32IMB-NEXT:    addi a0, a3, 1073
65; RV32IMB-NEXT:    sltu a2, a0, a3
66; RV32IMB-NEXT:    add a1, a1, a2
67; RV32IMB-NEXT:    ret
68;
69; RV64IMB-LABEL: add_mul_combine_accept_a3:
70; RV64IMB:       # %bb.0:
71; RV64IMB-NEXT:    sh1add a1, a0, a0
72; RV64IMB-NEXT:    slli a0, a0, 5
73; RV64IMB-NEXT:    sub a0, a0, a1
74; RV64IMB-NEXT:    addi a0, a0, 1073
75; RV64IMB-NEXT:    ret
76  %tmp0 = add i64 %x, 37
77  %tmp1 = mul i64 %tmp0, 29
78  ret i64 %tmp1
79}
80
81define i32 @add_mul_combine_accept_b1(i32 %x) {
82; RV32IMB-LABEL: add_mul_combine_accept_b1:
83; RV32IMB:       # %bb.0:
84; RV32IMB-NEXT:    sh3add a1, a0, a0
85; RV32IMB-NEXT:    slli a0, a0, 5
86; RV32IMB-NEXT:    sub a0, a0, a1
87; RV32IMB-NEXT:    lui a1, 50
88; RV32IMB-NEXT:    addi a1, a1, 1119
89; RV32IMB-NEXT:    add a0, a0, a1
90; RV32IMB-NEXT:    ret
91;
92; RV64IMB-LABEL: add_mul_combine_accept_b1:
93; RV64IMB:       # %bb.0:
94; RV64IMB-NEXT:    sh3add a1, a0, a0
95; RV64IMB-NEXT:    slli a0, a0, 5
96; RV64IMB-NEXT:    subw a0, a0, a1
97; RV64IMB-NEXT:    lui a1, 50
98; RV64IMB-NEXT:    addi a1, a1, 1119
99; RV64IMB-NEXT:    addw a0, a0, a1
100; RV64IMB-NEXT:    ret
101  %tmp0 = add i32 %x, 8953
102  %tmp1 = mul i32 %tmp0, 23
103  ret i32 %tmp1
104}
105
106define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
107; RV32IMB-LABEL: add_mul_combine_accept_b2:
108; RV32IMB:       # %bb.0:
109; RV32IMB-NEXT:    sh3add a1, a0, a0
110; RV32IMB-NEXT:    slli a0, a0, 5
111; RV32IMB-NEXT:    sub a0, a0, a1
112; RV32IMB-NEXT:    lui a1, 50
113; RV32IMB-NEXT:    addi a1, a1, 1119
114; RV32IMB-NEXT:    add a0, a0, a1
115; RV32IMB-NEXT:    ret
116;
117; RV64IMB-LABEL: add_mul_combine_accept_b2:
118; RV64IMB:       # %bb.0:
119; RV64IMB-NEXT:    sh3add a1, a0, a0
120; RV64IMB-NEXT:    slli a0, a0, 5
121; RV64IMB-NEXT:    subw a0, a0, a1
122; RV64IMB-NEXT:    lui a1, 50
123; RV64IMB-NEXT:    addi a1, a1, 1119
124; RV64IMB-NEXT:    addw a0, a0, a1
125; RV64IMB-NEXT:    ret
126  %tmp0 = add i32 %x, 8953
127  %tmp1 = mul i32 %tmp0, 23
128  ret i32 %tmp1
129}
130
131define i64 @add_mul_combine_accept_b3(i64 %x) {
132; RV32IMB-LABEL: add_mul_combine_accept_b3:
133; RV32IMB:       # %bb.0:
134; RV32IMB-NEXT:    li a2, 23
135; RV32IMB-NEXT:    sh3add a3, a1, a1
136; RV32IMB-NEXT:    slli a1, a1, 5
137; RV32IMB-NEXT:    sub a1, a1, a3
138; RV32IMB-NEXT:    sh3add a3, a0, a0
139; RV32IMB-NEXT:    mulhu a2, a0, a2
140; RV32IMB-NEXT:    slli a0, a0, 5
141; RV32IMB-NEXT:    sub a3, a0, a3
142; RV32IMB-NEXT:    lui a0, 50
143; RV32IMB-NEXT:    addi a0, a0, 1119
144; RV32IMB-NEXT:    add a1, a2, a1
145; RV32IMB-NEXT:    add a0, a3, a0
146; RV32IMB-NEXT:    sltu a2, a0, a3
147; RV32IMB-NEXT:    add a1, a1, a2
148; RV32IMB-NEXT:    ret
149;
150; RV64IMB-LABEL: add_mul_combine_accept_b3:
151; RV64IMB:       # %bb.0:
152; RV64IMB-NEXT:    sh3add a1, a0, a0
153; RV64IMB-NEXT:    slli a0, a0, 5
154; RV64IMB-NEXT:    sub a0, a0, a1
155; RV64IMB-NEXT:    lui a1, 50
156; RV64IMB-NEXT:    addiw a1, a1, 1119
157; RV64IMB-NEXT:    add a0, a0, a1
158; RV64IMB-NEXT:    ret
159  %tmp0 = add i64 %x, 8953
160  %tmp1 = mul i64 %tmp0, 23
161  ret i64 %tmp1
162}
163
164define i32 @add_mul_combine_reject_a1(i32 %x) {
165; RV32IMB-LABEL: add_mul_combine_reject_a1:
166; RV32IMB:       # %bb.0:
167; RV32IMB-NEXT:    addi a0, a0, 1971
168; RV32IMB-NEXT:    sh1add a1, a0, a0
169; RV32IMB-NEXT:    slli a0, a0, 5
170; RV32IMB-NEXT:    sub a0, a0, a1
171; RV32IMB-NEXT:    ret
172;
173; RV64IMB-LABEL: add_mul_combine_reject_a1:
174; RV64IMB:       # %bb.0:
175; RV64IMB-NEXT:    addi a0, a0, 1971
176; RV64IMB-NEXT:    sh1add a1, a0, a0
177; RV64IMB-NEXT:    slli a0, a0, 5
178; RV64IMB-NEXT:    subw a0, a0, a1
179; RV64IMB-NEXT:    ret
180  %tmp0 = add i32 %x, 1971
181  %tmp1 = mul i32 %tmp0, 29
182  ret i32 %tmp1
183}
184
185define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
186; RV32IMB-LABEL: add_mul_combine_reject_a2:
187; RV32IMB:       # %bb.0:
188; RV32IMB-NEXT:    addi a0, a0, 1971
189; RV32IMB-NEXT:    sh1add a1, a0, a0
190; RV32IMB-NEXT:    slli a0, a0, 5
191; RV32IMB-NEXT:    sub a0, a0, a1
192; RV32IMB-NEXT:    ret
193;
194; RV64IMB-LABEL: add_mul_combine_reject_a2:
195; RV64IMB:       # %bb.0:
196; RV64IMB-NEXT:    addi a0, a0, 1971
197; RV64IMB-NEXT:    sh1add a1, a0, a0
198; RV64IMB-NEXT:    slli a0, a0, 5
199; RV64IMB-NEXT:    subw a0, a0, a1
200; RV64IMB-NEXT:    ret
201  %tmp0 = add i32 %x, 1971
202  %tmp1 = mul i32 %tmp0, 29
203  ret i32 %tmp1
204}
205
206define i64 @add_mul_combine_reject_a3(i64 %x) {
207; RV32IMB-LABEL: add_mul_combine_reject_a3:
208; RV32IMB:       # %bb.0:
209; RV32IMB-NEXT:    li a2, 29
210; RV32IMB-NEXT:    sh1add a3, a1, a1
211; RV32IMB-NEXT:    slli a1, a1, 5
212; RV32IMB-NEXT:    sub a1, a1, a3
213; RV32IMB-NEXT:    sh1add a3, a0, a0
214; RV32IMB-NEXT:    mulhu a2, a0, a2
215; RV32IMB-NEXT:    slli a0, a0, 5
216; RV32IMB-NEXT:    sub a3, a0, a3
217; RV32IMB-NEXT:    lui a0, 14
218; RV32IMB-NEXT:    addi a0, a0, -185
219; RV32IMB-NEXT:    add a1, a2, a1
220; RV32IMB-NEXT:    add a0, a3, a0
221; RV32IMB-NEXT:    sltu a2, a0, a3
222; RV32IMB-NEXT:    add a1, a1, a2
223; RV32IMB-NEXT:    ret
224;
225; RV64IMB-LABEL: add_mul_combine_reject_a3:
226; RV64IMB:       # %bb.0:
227; RV64IMB-NEXT:    addi a0, a0, 1971
228; RV64IMB-NEXT:    sh1add a1, a0, a0
229; RV64IMB-NEXT:    slli a0, a0, 5
230; RV64IMB-NEXT:    sub a0, a0, a1
231; RV64IMB-NEXT:    ret
232  %tmp0 = add i64 %x, 1971
233  %tmp1 = mul i64 %tmp0, 29
234  ret i64 %tmp1
235}
236
237define i32 @add_mul_combine_reject_c1(i32 %x) {
238; RV32IMB-LABEL: add_mul_combine_reject_c1:
239; RV32IMB:       # %bb.0:
240; RV32IMB-NEXT:    addi a0, a0, 1000
241; RV32IMB-NEXT:    sh3add a1, a0, a0
242; RV32IMB-NEXT:    sh3add a0, a1, a0
243; RV32IMB-NEXT:    ret
244;
245; RV64IMB-LABEL: add_mul_combine_reject_c1:
246; RV64IMB:       # %bb.0:
247; RV64IMB-NEXT:    addi a0, a0, 1000
248; RV64IMB-NEXT:    sh3add a1, a0, a0
249; RV64IMB-NEXT:    sh3add a0, a1, a0
250; RV64IMB-NEXT:    sext.w a0, a0
251; RV64IMB-NEXT:    ret
252  %tmp0 = add i32 %x, 1000
253  %tmp1 = mul i32 %tmp0, 73
254  ret i32 %tmp1
255}
256
257define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
258; RV32IMB-LABEL: add_mul_combine_reject_c2:
259; RV32IMB:       # %bb.0:
260; RV32IMB-NEXT:    addi a0, a0, 1000
261; RV32IMB-NEXT:    sh3add a1, a0, a0
262; RV32IMB-NEXT:    sh3add a0, a1, a0
263; RV32IMB-NEXT:    ret
264;
265; RV64IMB-LABEL: add_mul_combine_reject_c2:
266; RV64IMB:       # %bb.0:
267; RV64IMB-NEXT:    addi a0, a0, 1000
268; RV64IMB-NEXT:    sh3add a1, a0, a0
269; RV64IMB-NEXT:    sh3add a0, a1, a0
270; RV64IMB-NEXT:    sext.w a0, a0
271; RV64IMB-NEXT:    ret
272  %tmp0 = add i32 %x, 1000
273  %tmp1 = mul i32 %tmp0, 73
274  ret i32 %tmp1
275}
276
277define i64 @add_mul_combine_reject_c3(i64 %x) {
278; RV32IMB-LABEL: add_mul_combine_reject_c3:
279; RV32IMB:       # %bb.0:
280; RV32IMB-NEXT:    li a2, 73
281; RV32IMB-NEXT:    sh3add a3, a1, a1
282; RV32IMB-NEXT:    sh3add a1, a3, a1
283; RV32IMB-NEXT:    sh3add a3, a0, a0
284; RV32IMB-NEXT:    mulhu a2, a0, a2
285; RV32IMB-NEXT:    sh3add a3, a3, a0
286; RV32IMB-NEXT:    lui a0, 18
287; RV32IMB-NEXT:    addi a0, a0, -728
288; RV32IMB-NEXT:    add a1, a2, a1
289; RV32IMB-NEXT:    add a0, a3, a0
290; RV32IMB-NEXT:    sltu a2, a0, a3
291; RV32IMB-NEXT:    add a1, a1, a2
292; RV32IMB-NEXT:    ret
293;
294; RV64IMB-LABEL: add_mul_combine_reject_c3:
295; RV64IMB:       # %bb.0:
296; RV64IMB-NEXT:    addi a0, a0, 1000
297; RV64IMB-NEXT:    sh3add a1, a0, a0
298; RV64IMB-NEXT:    sh3add a0, a1, a0
299; RV64IMB-NEXT:    ret
300  %tmp0 = add i64 %x, 1000
301  %tmp1 = mul i64 %tmp0, 73
302  ret i64 %tmp1
303}
304
305define i32 @add_mul_combine_reject_d1(i32 %x) {
306; RV32IMB-LABEL: add_mul_combine_reject_d1:
307; RV32IMB:       # %bb.0:
308; RV32IMB-NEXT:    addi a0, a0, 1000
309; RV32IMB-NEXT:    sh1add a0, a0, a0
310; RV32IMB-NEXT:    slli a0, a0, 6
311; RV32IMB-NEXT:    ret
312;
313; RV64IMB-LABEL: add_mul_combine_reject_d1:
314; RV64IMB:       # %bb.0:
315; RV64IMB-NEXT:    addi a0, a0, 1000
316; RV64IMB-NEXT:    sh1add a0, a0, a0
317; RV64IMB-NEXT:    slliw a0, a0, 6
318; RV64IMB-NEXT:    ret
319  %tmp0 = add i32 %x, 1000
320  %tmp1 = mul i32 %tmp0, 192
321  ret i32 %tmp1
322}
323
324define signext i32 @add_mul_combine_reject_d2(i32 signext %x) {
325; RV32IMB-LABEL: add_mul_combine_reject_d2:
326; RV32IMB:       # %bb.0:
327; RV32IMB-NEXT:    addi a0, a0, 1000
328; RV32IMB-NEXT:    sh1add a0, a0, a0
329; RV32IMB-NEXT:    slli a0, a0, 6
330; RV32IMB-NEXT:    ret
331;
332; RV64IMB-LABEL: add_mul_combine_reject_d2:
333; RV64IMB:       # %bb.0:
334; RV64IMB-NEXT:    addi a0, a0, 1000
335; RV64IMB-NEXT:    sh1add a0, a0, a0
336; RV64IMB-NEXT:    slliw a0, a0, 6
337; RV64IMB-NEXT:    ret
338  %tmp0 = add i32 %x, 1000
339  %tmp1 = mul i32 %tmp0, 192
340  ret i32 %tmp1
341}
342
343define i64 @add_mul_combine_reject_d3(i64 %x) {
344; RV32IMB-LABEL: add_mul_combine_reject_d3:
345; RV32IMB:       # %bb.0:
346; RV32IMB-NEXT:    li a2, 192
347; RV32IMB-NEXT:    sh1add a1, a1, a1
348; RV32IMB-NEXT:    mulhu a2, a0, a2
349; RV32IMB-NEXT:    sh1add a0, a0, a0
350; RV32IMB-NEXT:    slli a1, a1, 6
351; RV32IMB-NEXT:    add a1, a2, a1
352; RV32IMB-NEXT:    lui a2, 47
353; RV32IMB-NEXT:    slli a3, a0, 6
354; RV32IMB-NEXT:    addi a0, a2, -512
355; RV32IMB-NEXT:    add a0, a3, a0
356; RV32IMB-NEXT:    sltu a2, a0, a3
357; RV32IMB-NEXT:    add a1, a1, a2
358; RV32IMB-NEXT:    ret
359;
360; RV64IMB-LABEL: add_mul_combine_reject_d3:
361; RV64IMB:       # %bb.0:
362; RV64IMB-NEXT:    addi a0, a0, 1000
363; RV64IMB-NEXT:    sh1add a0, a0, a0
364; RV64IMB-NEXT:    slli a0, a0, 6
365; RV64IMB-NEXT:    ret
366  %tmp0 = add i64 %x, 1000
367  %tmp1 = mul i64 %tmp0, 192
368  ret i64 %tmp1
369}
370
371define i32 @add_mul_combine_reject_e1(i32 %x) {
372; RV32IMB-LABEL: add_mul_combine_reject_e1:
373; RV32IMB:       # %bb.0:
374; RV32IMB-NEXT:    addi a0, a0, 1971
375; RV32IMB-NEXT:    sh1add a1, a0, a0
376; RV32IMB-NEXT:    slli a0, a0, 5
377; RV32IMB-NEXT:    sub a0, a0, a1
378; RV32IMB-NEXT:    ret
379;
380; RV64IMB-LABEL: add_mul_combine_reject_e1:
381; RV64IMB:       # %bb.0:
382; RV64IMB-NEXT:    addi a0, a0, 1971
383; RV64IMB-NEXT:    sh1add a1, a0, a0
384; RV64IMB-NEXT:    slli a0, a0, 5
385; RV64IMB-NEXT:    subw a0, a0, a1
386; RV64IMB-NEXT:    ret
387  %tmp0 = mul i32 %x, 29
388  %tmp1 = add i32 %tmp0, 57159
389  ret i32 %tmp1
390}
391
392define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
393; RV32IMB-LABEL: add_mul_combine_reject_e2:
394; RV32IMB:       # %bb.0:
395; RV32IMB-NEXT:    addi a0, a0, 1971
396; RV32IMB-NEXT:    sh1add a1, a0, a0
397; RV32IMB-NEXT:    slli a0, a0, 5
398; RV32IMB-NEXT:    sub a0, a0, a1
399; RV32IMB-NEXT:    ret
400;
401; RV64IMB-LABEL: add_mul_combine_reject_e2:
402; RV64IMB:       # %bb.0:
403; RV64IMB-NEXT:    addi a0, a0, 1971
404; RV64IMB-NEXT:    sh1add a1, a0, a0
405; RV64IMB-NEXT:    slli a0, a0, 5
406; RV64IMB-NEXT:    subw a0, a0, a1
407; RV64IMB-NEXT:    ret
408  %tmp0 = mul i32 %x, 29
409  %tmp1 = add i32 %tmp0, 57159
410  ret i32 %tmp1
411}
412
413define i64 @add_mul_combine_reject_e3(i64 %x) {
414; RV32IMB-LABEL: add_mul_combine_reject_e3:
415; RV32IMB:       # %bb.0:
416; RV32IMB-NEXT:    li a2, 29
417; RV32IMB-NEXT:    sh1add a3, a1, a1
418; RV32IMB-NEXT:    slli a1, a1, 5
419; RV32IMB-NEXT:    sub a1, a1, a3
420; RV32IMB-NEXT:    sh1add a3, a0, a0
421; RV32IMB-NEXT:    mulhu a2, a0, a2
422; RV32IMB-NEXT:    slli a0, a0, 5
423; RV32IMB-NEXT:    sub a3, a0, a3
424; RV32IMB-NEXT:    lui a0, 14
425; RV32IMB-NEXT:    addi a0, a0, -185
426; RV32IMB-NEXT:    add a1, a2, a1
427; RV32IMB-NEXT:    add a0, a3, a0
428; RV32IMB-NEXT:    sltu a2, a0, a3
429; RV32IMB-NEXT:    add a1, a1, a2
430; RV32IMB-NEXT:    ret
431;
432; RV64IMB-LABEL: add_mul_combine_reject_e3:
433; RV64IMB:       # %bb.0:
434; RV64IMB-NEXT:    addi a0, a0, 1971
435; RV64IMB-NEXT:    sh1add a1, a0, a0
436; RV64IMB-NEXT:    slli a0, a0, 5
437; RV64IMB-NEXT:    sub a0, a0, a1
438; RV64IMB-NEXT:    ret
439  %tmp0 = mul i64 %x, 29
440  %tmp1 = add i64 %tmp0, 57159
441  ret i64 %tmp1
442}
443
444define i32 @add_mul_combine_reject_f1(i32 %x) {
445; RV32IMB-LABEL: add_mul_combine_reject_f1:
446; RV32IMB:       # %bb.0:
447; RV32IMB-NEXT:    addi a0, a0, 1972
448; RV32IMB-NEXT:    sh1add a1, a0, a0
449; RV32IMB-NEXT:    slli a0, a0, 5
450; RV32IMB-NEXT:    sub a0, a0, a1
451; RV32IMB-NEXT:    addi a0, a0, 11
452; RV32IMB-NEXT:    ret
453;
454; RV64IMB-LABEL: add_mul_combine_reject_f1:
455; RV64IMB:       # %bb.0:
456; RV64IMB-NEXT:    addi a0, a0, 1972
457; RV64IMB-NEXT:    sh1add a1, a0, a0
458; RV64IMB-NEXT:    slli a0, a0, 5
459; RV64IMB-NEXT:    subw a0, a0, a1
460; RV64IMB-NEXT:    addiw a0, a0, 11
461; RV64IMB-NEXT:    ret
462  %tmp0 = mul i32 %x, 29
463  %tmp1 = add i32 %tmp0, 57199
464  ret i32 %tmp1
465}
466
467define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
468; RV32IMB-LABEL: add_mul_combine_reject_f2:
469; RV32IMB:       # %bb.0:
470; RV32IMB-NEXT:    addi a0, a0, 1972
471; RV32IMB-NEXT:    sh1add a1, a0, a0
472; RV32IMB-NEXT:    slli a0, a0, 5
473; RV32IMB-NEXT:    sub a0, a0, a1
474; RV32IMB-NEXT:    addi a0, a0, 11
475; RV32IMB-NEXT:    ret
476;
477; RV64IMB-LABEL: add_mul_combine_reject_f2:
478; RV64IMB:       # %bb.0:
479; RV64IMB-NEXT:    addi a0, a0, 1972
480; RV64IMB-NEXT:    sh1add a1, a0, a0
481; RV64IMB-NEXT:    slli a0, a0, 5
482; RV64IMB-NEXT:    subw a0, a0, a1
483; RV64IMB-NEXT:    addiw a0, a0, 11
484; RV64IMB-NEXT:    ret
485  %tmp0 = mul i32 %x, 29
486  %tmp1 = add i32 %tmp0, 57199
487  ret i32 %tmp1
488}
489
490define i64 @add_mul_combine_reject_f3(i64 %x) {
491; RV32IMB-LABEL: add_mul_combine_reject_f3:
492; RV32IMB:       # %bb.0:
493; RV32IMB-NEXT:    li a2, 29
494; RV32IMB-NEXT:    sh1add a3, a1, a1
495; RV32IMB-NEXT:    slli a1, a1, 5
496; RV32IMB-NEXT:    sub a1, a1, a3
497; RV32IMB-NEXT:    sh1add a3, a0, a0
498; RV32IMB-NEXT:    mulhu a2, a0, a2
499; RV32IMB-NEXT:    slli a0, a0, 5
500; RV32IMB-NEXT:    sub a3, a0, a3
501; RV32IMB-NEXT:    lui a0, 14
502; RV32IMB-NEXT:    addi a0, a0, -145
503; RV32IMB-NEXT:    add a1, a2, a1
504; RV32IMB-NEXT:    add a0, a3, a0
505; RV32IMB-NEXT:    sltu a2, a0, a3
506; RV32IMB-NEXT:    add a1, a1, a2
507; RV32IMB-NEXT:    ret
508;
509; RV64IMB-LABEL: add_mul_combine_reject_f3:
510; RV64IMB:       # %bb.0:
511; RV64IMB-NEXT:    addi a0, a0, 1972
512; RV64IMB-NEXT:    sh1add a1, a0, a0
513; RV64IMB-NEXT:    slli a0, a0, 5
514; RV64IMB-NEXT:    sub a0, a0, a1
515; RV64IMB-NEXT:    addi a0, a0, 11
516; RV64IMB-NEXT:    ret
517  %tmp0 = mul i64 %x, 29
518  %tmp1 = add i64 %tmp0, 57199
519  ret i64 %tmp1
520}
521
522define i32 @add_mul_combine_reject_g1(i32 %x) {
523; RV32IMB-LABEL: add_mul_combine_reject_g1:
524; RV32IMB:       # %bb.0:
525; RV32IMB-NEXT:    addi a0, a0, 100
526; RV32IMB-NEXT:    sh3add a1, a0, a0
527; RV32IMB-NEXT:    sh3add a0, a1, a0
528; RV32IMB-NEXT:    addi a0, a0, 10
529; RV32IMB-NEXT:    ret
530;
531; RV64IMB-LABEL: add_mul_combine_reject_g1:
532; RV64IMB:       # %bb.0:
533; RV64IMB-NEXT:    addi a0, a0, 100
534; RV64IMB-NEXT:    sh3add a1, a0, a0
535; RV64IMB-NEXT:    sh3add a0, a1, a0
536; RV64IMB-NEXT:    addiw a0, a0, 10
537; RV64IMB-NEXT:    ret
538  %tmp0 = mul i32 %x, 73
539  %tmp1 = add i32 %tmp0, 7310
540  ret i32 %tmp1
541}
542
543define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
544; RV32IMB-LABEL: add_mul_combine_reject_g2:
545; RV32IMB:       # %bb.0:
546; RV32IMB-NEXT:    addi a0, a0, 100
547; RV32IMB-NEXT:    sh3add a1, a0, a0
548; RV32IMB-NEXT:    sh3add a0, a1, a0
549; RV32IMB-NEXT:    addi a0, a0, 10
550; RV32IMB-NEXT:    ret
551;
552; RV64IMB-LABEL: add_mul_combine_reject_g2:
553; RV64IMB:       # %bb.0:
554; RV64IMB-NEXT:    addi a0, a0, 100
555; RV64IMB-NEXT:    sh3add a1, a0, a0
556; RV64IMB-NEXT:    sh3add a0, a1, a0
557; RV64IMB-NEXT:    addiw a0, a0, 10
558; RV64IMB-NEXT:    ret
559  %tmp0 = mul i32 %x, 73
560  %tmp1 = add i32 %tmp0, 7310
561  ret i32 %tmp1
562}
563
564define i64 @add_mul_combine_reject_g3(i64 %x) {
565; RV32IMB-LABEL: add_mul_combine_reject_g3:
566; RV32IMB:       # %bb.0:
567; RV32IMB-NEXT:    li a2, 73
568; RV32IMB-NEXT:    sh3add a3, a1, a1
569; RV32IMB-NEXT:    sh3add a1, a3, a1
570; RV32IMB-NEXT:    sh3add a3, a0, a0
571; RV32IMB-NEXT:    mulhu a2, a0, a2
572; RV32IMB-NEXT:    sh3add a3, a3, a0
573; RV32IMB-NEXT:    lui a0, 2
574; RV32IMB-NEXT:    addi a0, a0, -882
575; RV32IMB-NEXT:    add a1, a2, a1
576; RV32IMB-NEXT:    add a0, a3, a0
577; RV32IMB-NEXT:    sltu a2, a0, a3
578; RV32IMB-NEXT:    add a1, a1, a2
579; RV32IMB-NEXT:    ret
580;
581; RV64IMB-LABEL: add_mul_combine_reject_g3:
582; RV64IMB:       # %bb.0:
583; RV64IMB-NEXT:    addi a0, a0, 100
584; RV64IMB-NEXT:    sh3add a1, a0, a0
585; RV64IMB-NEXT:    sh3add a0, a1, a0
586; RV64IMB-NEXT:    addi a0, a0, 10
587; RV64IMB-NEXT:    ret
588  %tmp0 = mul i64 %x, 73
589  %tmp1 = add i64 %tmp0, 7310
590  ret i64 %tmp1
591}
592
593; This test previously infinite looped in DAG combine.
594define i64 @add_mul_combine_infinite_loop(i64 %x) {
595; RV32IMB-LABEL: add_mul_combine_infinite_loop:
596; RV32IMB:       # %bb.0:
597; RV32IMB-NEXT:    li a2, 24
598; RV32IMB-NEXT:    sh1add a1, a1, a1
599; RV32IMB-NEXT:    sh1add a3, a0, a0
600; RV32IMB-NEXT:    mulhu a0, a0, a2
601; RV32IMB-NEXT:    li a2, 1
602; RV32IMB-NEXT:    sh3add a1, a1, a0
603; RV32IMB-NEXT:    slli a4, a3, 3
604; RV32IMB-NEXT:    slli a2, a2, 11
605; RV32IMB-NEXT:    sh3add a0, a3, a2
606; RV32IMB-NEXT:    sltu a2, a0, a4
607; RV32IMB-NEXT:    add a1, a1, a2
608; RV32IMB-NEXT:    ret
609;
610; RV64IMB-LABEL: add_mul_combine_infinite_loop:
611; RV64IMB:       # %bb.0:
612; RV64IMB-NEXT:    addi a0, a0, 86
613; RV64IMB-NEXT:    sh1add a0, a0, a0
614; RV64IMB-NEXT:    slli a0, a0, 3
615; RV64IMB-NEXT:    addi a0, a0, -16
616; RV64IMB-NEXT:    ret
617  %tmp0 = mul i64 %x, 24
618  %tmp1 = add i64 %tmp0, 2048
619  ret i64 %tmp1
620}
621
622define i32 @mul3000_add8990_a(i32 %x) {
623; RV32IMB-LABEL: mul3000_add8990_a:
624; RV32IMB:       # %bb.0:
625; RV32IMB-NEXT:    addi a0, a0, 3
626; RV32IMB-NEXT:    lui a1, 1
627; RV32IMB-NEXT:    addi a1, a1, -1096
628; RV32IMB-NEXT:    mul a0, a0, a1
629; RV32IMB-NEXT:    addi a0, a0, -10
630; RV32IMB-NEXT:    ret
631;
632; RV64IMB-LABEL: mul3000_add8990_a:
633; RV64IMB:       # %bb.0:
634; RV64IMB-NEXT:    addi a0, a0, 3
635; RV64IMB-NEXT:    lui a1, 1
636; RV64IMB-NEXT:    addi a1, a1, -1096
637; RV64IMB-NEXT:    mul a0, a0, a1
638; RV64IMB-NEXT:    addiw a0, a0, -10
639; RV64IMB-NEXT:    ret
640  %tmp0 = mul i32 %x, 3000
641  %tmp1 = add i32 %tmp0, 8990
642  ret i32 %tmp1
643}
644
645define signext i32 @mul3000_add8990_b(i32 signext %x) {
646; RV32IMB-LABEL: mul3000_add8990_b:
647; RV32IMB:       # %bb.0:
648; RV32IMB-NEXT:    addi a0, a0, 3
649; RV32IMB-NEXT:    lui a1, 1
650; RV32IMB-NEXT:    addi a1, a1, -1096
651; RV32IMB-NEXT:    mul a0, a0, a1
652; RV32IMB-NEXT:    addi a0, a0, -10
653; RV32IMB-NEXT:    ret
654;
655; RV64IMB-LABEL: mul3000_add8990_b:
656; RV64IMB:       # %bb.0:
657; RV64IMB-NEXT:    addi a0, a0, 3
658; RV64IMB-NEXT:    lui a1, 1
659; RV64IMB-NEXT:    addi a1, a1, -1096
660; RV64IMB-NEXT:    mul a0, a0, a1
661; RV64IMB-NEXT:    addiw a0, a0, -10
662; RV64IMB-NEXT:    ret
663  %tmp0 = mul i32 %x, 3000
664  %tmp1 = add i32 %tmp0, 8990
665  ret i32 %tmp1
666}
667
668define i64 @mul3000_add8990_c(i64 %x) {
669; RV32IMB-LABEL: mul3000_add8990_c:
670; RV32IMB:       # %bb.0:
671; RV32IMB-NEXT:    lui a2, 1
672; RV32IMB-NEXT:    addi a2, a2, -1096
673; RV32IMB-NEXT:    mul a1, a1, a2
674; RV32IMB-NEXT:    mulhu a3, a0, a2
675; RV32IMB-NEXT:    mul a2, a0, a2
676; RV32IMB-NEXT:    lui a0, 2
677; RV32IMB-NEXT:    addi a0, a0, 798
678; RV32IMB-NEXT:    add a1, a3, a1
679; RV32IMB-NEXT:    add a0, a2, a0
680; RV32IMB-NEXT:    sltu a2, a0, a2
681; RV32IMB-NEXT:    add a1, a1, a2
682; RV32IMB-NEXT:    ret
683;
684; RV64IMB-LABEL: mul3000_add8990_c:
685; RV64IMB:       # %bb.0:
686; RV64IMB-NEXT:    addi a0, a0, 3
687; RV64IMB-NEXT:    lui a1, 1
688; RV64IMB-NEXT:    addiw a1, a1, -1096
689; RV64IMB-NEXT:    mul a0, a0, a1
690; RV64IMB-NEXT:    addi a0, a0, -10
691; RV64IMB-NEXT:    ret
692  %tmp0 = mul i64 %x, 3000
693  %tmp1 = add i64 %tmp0, 8990
694  ret i64 %tmp1
695}
696
697define i32 @mul3000_sub8990_a(i32 %x) {
698; RV32IMB-LABEL: mul3000_sub8990_a:
699; RV32IMB:       # %bb.0:
700; RV32IMB-NEXT:    addi a0, a0, -3
701; RV32IMB-NEXT:    lui a1, 1
702; RV32IMB-NEXT:    addi a1, a1, -1096
703; RV32IMB-NEXT:    mul a0, a0, a1
704; RV32IMB-NEXT:    addi a0, a0, 10
705; RV32IMB-NEXT:    ret
706;
707; RV64IMB-LABEL: mul3000_sub8990_a:
708; RV64IMB:       # %bb.0:
709; RV64IMB-NEXT:    addi a0, a0, -3
710; RV64IMB-NEXT:    lui a1, 1
711; RV64IMB-NEXT:    addi a1, a1, -1096
712; RV64IMB-NEXT:    mul a0, a0, a1
713; RV64IMB-NEXT:    addiw a0, a0, 10
714; RV64IMB-NEXT:    ret
715  %tmp0 = mul i32 %x, 3000
716  %tmp1 = add i32 %tmp0, -8990
717  ret i32 %tmp1
718}
719
720define signext i32 @mul3000_sub8990_b(i32 signext %x) {
721; RV32IMB-LABEL: mul3000_sub8990_b:
722; RV32IMB:       # %bb.0:
723; RV32IMB-NEXT:    addi a0, a0, -3
724; RV32IMB-NEXT:    lui a1, 1
725; RV32IMB-NEXT:    addi a1, a1, -1096
726; RV32IMB-NEXT:    mul a0, a0, a1
727; RV32IMB-NEXT:    addi a0, a0, 10
728; RV32IMB-NEXT:    ret
729;
730; RV64IMB-LABEL: mul3000_sub8990_b:
731; RV64IMB:       # %bb.0:
732; RV64IMB-NEXT:    addi a0, a0, -3
733; RV64IMB-NEXT:    lui a1, 1
734; RV64IMB-NEXT:    addi a1, a1, -1096
735; RV64IMB-NEXT:    mul a0, a0, a1
736; RV64IMB-NEXT:    addiw a0, a0, 10
737; RV64IMB-NEXT:    ret
738  %tmp0 = mul i32 %x, 3000
739  %tmp1 = add i32 %tmp0, -8990
740  ret i32 %tmp1
741}
742
743define i64 @mul3000_sub8990_c(i64 %x) {
744; RV32IMB-LABEL: mul3000_sub8990_c:
745; RV32IMB:       # %bb.0:
746; RV32IMB-NEXT:    lui a2, 1
747; RV32IMB-NEXT:    addi a2, a2, -1096
748; RV32IMB-NEXT:    mul a1, a1, a2
749; RV32IMB-NEXT:    mulhu a3, a0, a2
750; RV32IMB-NEXT:    mul a2, a0, a2
751; RV32IMB-NEXT:    lui a0, 1048574
752; RV32IMB-NEXT:    addi a0, a0, -798
753; RV32IMB-NEXT:    add a1, a3, a1
754; RV32IMB-NEXT:    add a0, a2, a0
755; RV32IMB-NEXT:    sltu a2, a0, a2
756; RV32IMB-NEXT:    add a1, a1, a2
757; RV32IMB-NEXT:    addi a1, a1, -1
758; RV32IMB-NEXT:    ret
759;
760; RV64IMB-LABEL: mul3000_sub8990_c:
761; RV64IMB:       # %bb.0:
762; RV64IMB-NEXT:    addi a0, a0, -3
763; RV64IMB-NEXT:    lui a1, 1
764; RV64IMB-NEXT:    addiw a1, a1, -1096
765; RV64IMB-NEXT:    mul a0, a0, a1
766; RV64IMB-NEXT:    addi a0, a0, 10
767; RV64IMB-NEXT:    ret
768  %tmp0 = mul i64 %x, 3000
769  %tmp1 = add i64 %tmp0, -8990
770  ret i64 %tmp1
771}
772
773define i32 @mulneg3000_add8990_a(i32 %x) {
774; RV32IMB-LABEL: mulneg3000_add8990_a:
775; RV32IMB:       # %bb.0:
776; RV32IMB-NEXT:    addi a0, a0, -3
777; RV32IMB-NEXT:    lui a1, 1048575
778; RV32IMB-NEXT:    addi a1, a1, 1096
779; RV32IMB-NEXT:    mul a0, a0, a1
780; RV32IMB-NEXT:    addi a0, a0, -10
781; RV32IMB-NEXT:    ret
782;
783; RV64IMB-LABEL: mulneg3000_add8990_a:
784; RV64IMB:       # %bb.0:
785; RV64IMB-NEXT:    addi a0, a0, -3
786; RV64IMB-NEXT:    lui a1, 1048575
787; RV64IMB-NEXT:    addi a1, a1, 1096
788; RV64IMB-NEXT:    mul a0, a0, a1
789; RV64IMB-NEXT:    addiw a0, a0, -10
790; RV64IMB-NEXT:    ret
791  %tmp0 = mul i32 %x, -3000
792  %tmp1 = add i32 %tmp0, 8990
793  ret i32 %tmp1
794}
795
796define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
797; RV32IMB-LABEL: mulneg3000_add8990_b:
798; RV32IMB:       # %bb.0:
799; RV32IMB-NEXT:    addi a0, a0, -3
800; RV32IMB-NEXT:    lui a1, 1048575
801; RV32IMB-NEXT:    addi a1, a1, 1096
802; RV32IMB-NEXT:    mul a0, a0, a1
803; RV32IMB-NEXT:    addi a0, a0, -10
804; RV32IMB-NEXT:    ret
805;
806; RV64IMB-LABEL: mulneg3000_add8990_b:
807; RV64IMB:       # %bb.0:
808; RV64IMB-NEXT:    addi a0, a0, -3
809; RV64IMB-NEXT:    lui a1, 1048575
810; RV64IMB-NEXT:    addi a1, a1, 1096
811; RV64IMB-NEXT:    mul a0, a0, a1
812; RV64IMB-NEXT:    addiw a0, a0, -10
813; RV64IMB-NEXT:    ret
814  %tmp0 = mul i32 %x, -3000
815  %tmp1 = add i32 %tmp0, 8990
816  ret i32 %tmp1
817}
818
819define i64 @mulneg3000_add8990_c(i64 %x) {
820; RV32IMB-LABEL: mulneg3000_add8990_c:
821; RV32IMB:       # %bb.0:
822; RV32IMB-NEXT:    lui a2, 1048575
823; RV32IMB-NEXT:    addi a2, a2, 1096
824; RV32IMB-NEXT:    mul a1, a1, a2
825; RV32IMB-NEXT:    mulhu a3, a0, a2
826; RV32IMB-NEXT:    mul a2, a0, a2
827; RV32IMB-NEXT:    sub a3, a3, a0
828; RV32IMB-NEXT:    lui a0, 2
829; RV32IMB-NEXT:    addi a0, a0, 798
830; RV32IMB-NEXT:    add a0, a2, a0
831; RV32IMB-NEXT:    add a1, a3, a1
832; RV32IMB-NEXT:    sltu a2, a0, a2
833; RV32IMB-NEXT:    add a1, a1, a2
834; RV32IMB-NEXT:    ret
835;
836; RV64IMB-LABEL: mulneg3000_add8990_c:
837; RV64IMB:       # %bb.0:
838; RV64IMB-NEXT:    addi a0, a0, -3
839; RV64IMB-NEXT:    lui a1, 1048575
840; RV64IMB-NEXT:    addiw a1, a1, 1096
841; RV64IMB-NEXT:    mul a0, a0, a1
842; RV64IMB-NEXT:    addi a0, a0, -10
843; RV64IMB-NEXT:    ret
844  %tmp0 = mul i64 %x, -3000
845  %tmp1 = add i64 %tmp0, 8990
846  ret i64 %tmp1
847}
848
849define i32 @mulneg3000_sub8990_a(i32 %x) {
850; RV32IMB-LABEL: mulneg3000_sub8990_a:
851; RV32IMB:       # %bb.0:
852; RV32IMB-NEXT:    addi a0, a0, 3
853; RV32IMB-NEXT:    lui a1, 1048575
854; RV32IMB-NEXT:    addi a1, a1, 1096
855; RV32IMB-NEXT:    mul a0, a0, a1
856; RV32IMB-NEXT:    addi a0, a0, 10
857; RV32IMB-NEXT:    ret
858;
859; RV64IMB-LABEL: mulneg3000_sub8990_a:
860; RV64IMB:       # %bb.0:
861; RV64IMB-NEXT:    addi a0, a0, 3
862; RV64IMB-NEXT:    lui a1, 1048575
863; RV64IMB-NEXT:    addi a1, a1, 1096
864; RV64IMB-NEXT:    mul a0, a0, a1
865; RV64IMB-NEXT:    addiw a0, a0, 10
866; RV64IMB-NEXT:    ret
867  %tmp0 = mul i32 %x, -3000
868  %tmp1 = add i32 %tmp0, -8990
869  ret i32 %tmp1
870}
871
872define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
873; RV32IMB-LABEL: mulneg3000_sub8990_b:
874; RV32IMB:       # %bb.0:
875; RV32IMB-NEXT:    addi a0, a0, 3
876; RV32IMB-NEXT:    lui a1, 1048575
877; RV32IMB-NEXT:    addi a1, a1, 1096
878; RV32IMB-NEXT:    mul a0, a0, a1
879; RV32IMB-NEXT:    addi a0, a0, 10
880; RV32IMB-NEXT:    ret
881;
882; RV64IMB-LABEL: mulneg3000_sub8990_b:
883; RV64IMB:       # %bb.0:
884; RV64IMB-NEXT:    addi a0, a0, 3
885; RV64IMB-NEXT:    lui a1, 1048575
886; RV64IMB-NEXT:    addi a1, a1, 1096
887; RV64IMB-NEXT:    mul a0, a0, a1
888; RV64IMB-NEXT:    addiw a0, a0, 10
889; RV64IMB-NEXT:    ret
890  %tmp0 = mul i32 %x, -3000
891  %tmp1 = add i32 %tmp0, -8990
892  ret i32 %tmp1
893}
894
895define i64 @mulneg3000_sub8990_c(i64 %x) {
896; RV32IMB-LABEL: mulneg3000_sub8990_c:
897; RV32IMB:       # %bb.0:
898; RV32IMB-NEXT:    lui a2, 1048575
899; RV32IMB-NEXT:    addi a2, a2, 1096
900; RV32IMB-NEXT:    mul a1, a1, a2
901; RV32IMB-NEXT:    mulhu a3, a0, a2
902; RV32IMB-NEXT:    mul a2, a0, a2
903; RV32IMB-NEXT:    sub a3, a3, a0
904; RV32IMB-NEXT:    lui a0, 1048574
905; RV32IMB-NEXT:    addi a0, a0, -798
906; RV32IMB-NEXT:    add a0, a2, a0
907; RV32IMB-NEXT:    add a1, a3, a1
908; RV32IMB-NEXT:    sltu a2, a0, a2
909; RV32IMB-NEXT:    add a1, a1, a2
910; RV32IMB-NEXT:    addi a1, a1, -1
911; RV32IMB-NEXT:    ret
912;
913; RV64IMB-LABEL: mulneg3000_sub8990_c:
914; RV64IMB:       # %bb.0:
915; RV64IMB-NEXT:    addi a0, a0, 3
916; RV64IMB-NEXT:    lui a1, 1048575
917; RV64IMB-NEXT:    addiw a1, a1, 1096
918; RV64IMB-NEXT:    mul a0, a0, a1
919; RV64IMB-NEXT:    addi a0, a0, 10
920; RV64IMB-NEXT:    ret
921  %tmp0 = mul i64 %x, -3000
922  %tmp1 = add i64 %tmp0, -8990
923  ret i64 %tmp1
924}
925
926; This test case previously caused an infinite loop between transformations
927; performed in RISCVISelLowering;:transformAddImmMulImm and
928; DAGCombiner::visitMUL.
929define i1 @pr53831(i32 %x) {
930; RV32IMB-LABEL: pr53831:
931; RV32IMB:       # %bb.0:
932; RV32IMB-NEXT:    li a0, 0
933; RV32IMB-NEXT:    ret
934;
935; RV64IMB-LABEL: pr53831:
936; RV64IMB:       # %bb.0:
937; RV64IMB-NEXT:    li a0, 0
938; RV64IMB-NEXT:    ret
939  %tmp0 = add i32 %x, 1
940  %tmp1 = mul i32 %tmp0, 24
941  %tmp2 = add i32 %tmp1, 1
942  %tmp3 = mul i32 %x, 24
943  %tmp4 = add i32 %tmp3, 2048
944  %tmp5 = icmp eq i32 %tmp4, %tmp2
945  ret i1 %tmp5
946}
947
948define i64 @sh2add_uw(i64 signext %0, i32 signext %1) {
949; RV32IMB-LABEL: sh2add_uw:
950; RV32IMB:       # %bb.0: # %entry
951; RV32IMB-NEXT:    srli a3, a2, 27
952; RV32IMB-NEXT:    slli a2, a2, 5
953; RV32IMB-NEXT:    srli a4, a0, 29
954; RV32IMB-NEXT:    sh3add a1, a1, a4
955; RV32IMB-NEXT:    sh3add a0, a0, a2
956; RV32IMB-NEXT:    sltu a2, a0, a2
957; RV32IMB-NEXT:    add a1, a3, a1
958; RV32IMB-NEXT:    add a1, a1, a2
959; RV32IMB-NEXT:    ret
960;
961; RV64IMB-LABEL: sh2add_uw:
962; RV64IMB:       # %bb.0: # %entry
963; RV64IMB-NEXT:    sh2add.uw a0, a1, a0
964; RV64IMB-NEXT:    slli a0, a0, 3
965; RV64IMB-NEXT:    ret
966entry:
967  %2 = zext i32 %1 to i64
968  %3 = shl i64 %2, 5
969  %4 = shl i64 %0, 3
970  %5 = add i64 %3, %4
971  ret i64 %5
972}
973