xref: /llvm-project/llvm/test/CodeGen/RISCV/add-before-shl.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs --riscv-no-aliases < %s \
3; RUN:   | FileCheck -check-prefixes=RV32I %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs --riscv-no-aliases < %s \
5; RUN:   | FileCheck -check-prefixes=RV64I %s
6; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
7; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
8; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
9; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
10; RUN: llc -mtriple=riscv32 -mattr=+zca -verify-machineinstrs --riscv-no-aliases \
11; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
12; RUN: llc -mtriple=riscv64 -mattr=+zca -verify-machineinstrs --riscv-no-aliases \
13; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
14
15; These test that constant adds are not moved after shifts by DAGCombine,
16; if the constant is cheaper to materialise before it has been shifted.
17
18define signext i32 @add_small_const(i32 signext %a) nounwind {
19; RV32I-LABEL: add_small_const:
20; RV32I:       # %bb.0:
21; RV32I-NEXT:    addi a0, a0, 1
22; RV32I-NEXT:    slli a0, a0, 24
23; RV32I-NEXT:    srai a0, a0, 24
24; RV32I-NEXT:    jalr zero, 0(ra)
25;
26; RV64I-LABEL: add_small_const:
27; RV64I:       # %bb.0:
28; RV64I-NEXT:    addi a0, a0, 1
29; RV64I-NEXT:    slli a0, a0, 56
30; RV64I-NEXT:    srai a0, a0, 56
31; RV64I-NEXT:    jalr zero, 0(ra)
32;
33; RV32C-LABEL: add_small_const:
34; RV32C:       # %bb.0:
35; RV32C-NEXT:    c.addi a0, 1
36; RV32C-NEXT:    c.slli a0, 24
37; RV32C-NEXT:    c.srai a0, 24
38; RV32C-NEXT:    c.jr ra
39;
40; RV64C-LABEL: add_small_const:
41; RV64C:       # %bb.0:
42; RV64C-NEXT:    c.addi a0, 1
43; RV64C-NEXT:    c.slli a0, 56
44; RV64C-NEXT:    c.srai a0, 56
45; RV64C-NEXT:    c.jr ra
46  %1 = add i32 %a, 1
47  %2 = shl i32 %1, 24
48  %3 = ashr i32 %2, 24
49  ret i32 %3
50}
51
52define signext i32 @add_large_const(i32 signext %a) nounwind {
53; RV32I-LABEL: add_large_const:
54; RV32I:       # %bb.0:
55; RV32I-NEXT:    slli a0, a0, 16
56; RV32I-NEXT:    lui a1, 65520
57; RV32I-NEXT:    add a0, a0, a1
58; RV32I-NEXT:    srai a0, a0, 16
59; RV32I-NEXT:    jalr zero, 0(ra)
60;
61; RV64I-LABEL: add_large_const:
62; RV64I:       # %bb.0:
63; RV64I-NEXT:    slli a0, a0, 48
64; RV64I-NEXT:    lui a1, 4095
65; RV64I-NEXT:    slli a1, a1, 36
66; RV64I-NEXT:    add a0, a0, a1
67; RV64I-NEXT:    srai a0, a0, 48
68; RV64I-NEXT:    jalr zero, 0(ra)
69;
70; RV32C-LABEL: add_large_const:
71; RV32C:       # %bb.0:
72; RV32C-NEXT:    c.slli a0, 16
73; RV32C-NEXT:    lui a1, 65520
74; RV32C-NEXT:    c.add a0, a1
75; RV32C-NEXT:    c.srai a0, 16
76; RV32C-NEXT:    c.jr ra
77;
78; RV64C-LABEL: add_large_const:
79; RV64C:       # %bb.0:
80; RV64C-NEXT:    c.lui a1, 1
81; RV64C-NEXT:    c.addi a1, -1
82; RV64C-NEXT:    c.add a0, a1
83; RV64C-NEXT:    c.slli a0, 48
84; RV64C-NEXT:    c.srai a0, 48
85; RV64C-NEXT:    c.jr ra
86  %1 = add i32 %a, 4095
87  %2 = shl i32 %1, 16
88  %3 = ashr i32 %2, 16
89  ret i32 %3
90}
91
92define signext i32 @add_huge_const(i32 signext %a) nounwind {
93; RV32I-LABEL: add_huge_const:
94; RV32I:       # %bb.0:
95; RV32I-NEXT:    slli a0, a0, 16
96; RV32I-NEXT:    lui a1, 524272
97; RV32I-NEXT:    add a0, a0, a1
98; RV32I-NEXT:    srai a0, a0, 16
99; RV32I-NEXT:    jalr zero, 0(ra)
100;
101; RV64I-LABEL: add_huge_const:
102; RV64I:       # %bb.0:
103; RV64I-NEXT:    slli a0, a0, 48
104; RV64I-NEXT:    lui a1, 32767
105; RV64I-NEXT:    slli a1, a1, 36
106; RV64I-NEXT:    add a0, a0, a1
107; RV64I-NEXT:    srai a0, a0, 48
108; RV64I-NEXT:    jalr zero, 0(ra)
109;
110; RV32C-LABEL: add_huge_const:
111; RV32C:       # %bb.0:
112; RV32C-NEXT:    c.slli a0, 16
113; RV32C-NEXT:    lui a1, 524272
114; RV32C-NEXT:    c.add a0, a1
115; RV32C-NEXT:    c.srai a0, 16
116; RV32C-NEXT:    c.jr ra
117;
118; RV64C-LABEL: add_huge_const:
119; RV64C:       # %bb.0:
120; RV64C-NEXT:    c.lui a1, 8
121; RV64C-NEXT:    c.addi a1, -1
122; RV64C-NEXT:    c.add a0, a1
123; RV64C-NEXT:    c.slli a0, 48
124; RV64C-NEXT:    c.srai a0, 48
125; RV64C-NEXT:    c.jr ra
126  %1 = add i32 %a, 32767
127  %2 = shl i32 %1, 16
128  %3 = ashr i32 %2, 16
129  ret i32 %3
130}
131
132define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
133; RV32I-LABEL: add_non_machine_type:
134; RV32I:       # %bb.0:
135; RV32I-NEXT:    addi a0, a0, 256
136; RV32I-NEXT:    slli a0, a0, 20
137; RV32I-NEXT:    srai a0, a0, 8
138; RV32I-NEXT:    jalr zero, 0(ra)
139;
140; RV64I-LABEL: add_non_machine_type:
141; RV64I:       # %bb.0:
142; RV64I-NEXT:    addi a0, a0, 256
143; RV64I-NEXT:    slli a0, a0, 52
144; RV64I-NEXT:    srai a0, a0, 40
145; RV64I-NEXT:    jalr zero, 0(ra)
146;
147; RV32C-LABEL: add_non_machine_type:
148; RV32C:       # %bb.0:
149; RV32C-NEXT:    addi a0, a0, 256
150; RV32C-NEXT:    c.slli a0, 20
151; RV32C-NEXT:    c.srai a0, 8
152; RV32C-NEXT:    c.jr ra
153;
154; RV64C-LABEL: add_non_machine_type:
155; RV64C:       # %bb.0:
156; RV64C-NEXT:    addi a0, a0, 256
157; RV64C-NEXT:    c.slli a0, 52
158; RV64C-NEXT:    c.srai a0, 40
159; RV64C-NEXT:    c.jr ra
160  %1 = add i24 %a, 256
161  %2 = shl i24 %1, 12
162  ret i24 %2
163}
164
165define i128 @add_wide_operand(i128 %a) nounwind {
166; RV32I-LABEL: add_wide_operand:
167; RV32I:       # %bb.0:
168; RV32I-NEXT:    lw a2, 0(a1)
169; RV32I-NEXT:    lw a3, 4(a1)
170; RV32I-NEXT:    lw a4, 8(a1)
171; RV32I-NEXT:    lw a1, 12(a1)
172; RV32I-NEXT:    srli a5, a2, 29
173; RV32I-NEXT:    slli a6, a3, 3
174; RV32I-NEXT:    srli a3, a3, 29
175; RV32I-NEXT:    or a5, a6, a5
176; RV32I-NEXT:    slli a6, a4, 3
177; RV32I-NEXT:    or a3, a6, a3
178; RV32I-NEXT:    lui a6, 128
179; RV32I-NEXT:    srli a4, a4, 29
180; RV32I-NEXT:    slli a1, a1, 3
181; RV32I-NEXT:    slli a2, a2, 3
182; RV32I-NEXT:    or a1, a1, a4
183; RV32I-NEXT:    add a1, a1, a6
184; RV32I-NEXT:    sw a2, 0(a0)
185; RV32I-NEXT:    sw a5, 4(a0)
186; RV32I-NEXT:    sw a3, 8(a0)
187; RV32I-NEXT:    sw a1, 12(a0)
188; RV32I-NEXT:    jalr zero, 0(ra)
189;
190; RV64I-LABEL: add_wide_operand:
191; RV64I:       # %bb.0:
192; RV64I-NEXT:    srli a2, a0, 61
193; RV64I-NEXT:    slli a1, a1, 3
194; RV64I-NEXT:    slli a0, a0, 3
195; RV64I-NEXT:    or a1, a1, a2
196; RV64I-NEXT:    addi a2, zero, 1
197; RV64I-NEXT:    slli a2, a2, 51
198; RV64I-NEXT:    add a1, a1, a2
199; RV64I-NEXT:    jalr zero, 0(ra)
200;
201; RV32C-LABEL: add_wide_operand:
202; RV32C:       # %bb.0:
203; RV32C-NEXT:    c.lw a4, 12(a1)
204; RV32C-NEXT:    c.lw a3, 0(a1)
205; RV32C-NEXT:    c.lw a2, 4(a1)
206; RV32C-NEXT:    c.lw a1, 8(a1)
207; RV32C-NEXT:    c.lui a5, 16
208; RV32C-NEXT:    add a6, a4, a5
209; RV32C-NEXT:    srli a5, a3, 29
210; RV32C-NEXT:    slli a4, a2, 3
211; RV32C-NEXT:    c.or a4, a5
212; RV32C-NEXT:    srli a5, a1, 29
213; RV32C-NEXT:    c.srli a2, 29
214; RV32C-NEXT:    c.slli a1, 3
215; RV32C-NEXT:    c.slli a3, 3
216; RV32C-NEXT:    c.slli a6, 3
217; RV32C-NEXT:    c.or a1, a2
218; RV32C-NEXT:    or a2, a6, a5
219; RV32C-NEXT:    c.sw a3, 0(a0)
220; RV32C-NEXT:    c.sw a4, 4(a0)
221; RV32C-NEXT:    c.sw a1, 8(a0)
222; RV32C-NEXT:    c.sw a2, 12(a0)
223; RV32C-NEXT:    c.jr ra
224;
225; RV64C-LABEL: add_wide_operand:
226; RV64C:       # %bb.0:
227; RV64C-NEXT:    srli a2, a0, 61
228; RV64C-NEXT:    c.slli a1, 3
229; RV64C-NEXT:    c.slli a0, 3
230; RV64C-NEXT:    c.or a1, a2
231; RV64C-NEXT:    c.li a2, 1
232; RV64C-NEXT:    c.slli a2, 51
233; RV64C-NEXT:    c.add a1, a2
234; RV64C-NEXT:    c.jr ra
235  %1 = add i128 %a, 5192296858534827628530496329220096
236  %2 = shl i128 %1, 3
237  ret i128 %2
238}
239