xref: /llvm-project/llvm/test/CodeGen/RISCV/abdu.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,NOZBB,RV32I
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,NOZBB,RV64I
4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK,ZBB,RV32ZBB
5; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK,ZBB,RV64ZBB
6
7;
8; trunc(abs(sub(zext(a),zext(b)))) -> abdu(a,b)
9;
10
11define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
12; RV32I-LABEL: abd_ext_i8:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    andi a1, a1, 255
15; RV32I-NEXT:    andi a0, a0, 255
16; RV32I-NEXT:    sub a0, a0, a1
17; RV32I-NEXT:    srai a1, a0, 31
18; RV32I-NEXT:    xor a0, a0, a1
19; RV32I-NEXT:    sub a0, a0, a1
20; RV32I-NEXT:    ret
21;
22; RV64I-LABEL: abd_ext_i8:
23; RV64I:       # %bb.0:
24; RV64I-NEXT:    andi a1, a1, 255
25; RV64I-NEXT:    andi a0, a0, 255
26; RV64I-NEXT:    sub a0, a0, a1
27; RV64I-NEXT:    srai a1, a0, 63
28; RV64I-NEXT:    xor a0, a0, a1
29; RV64I-NEXT:    sub a0, a0, a1
30; RV64I-NEXT:    ret
31;
32; ZBB-LABEL: abd_ext_i8:
33; ZBB:       # %bb.0:
34; ZBB-NEXT:    andi a1, a1, 255
35; ZBB-NEXT:    andi a0, a0, 255
36; ZBB-NEXT:    minu a2, a0, a1
37; ZBB-NEXT:    maxu a0, a0, a1
38; ZBB-NEXT:    sub a0, a0, a2
39; ZBB-NEXT:    ret
40  %aext = zext i8 %a to i64
41  %bext = zext i8 %b to i64
42  %sub = sub i64 %aext, %bext
43  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
44  %trunc = trunc i64 %abs to i8
45  ret i8 %trunc
46}
47
48define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
49; RV32I-LABEL: abd_ext_i8_i16:
50; RV32I:       # %bb.0:
51; RV32I-NEXT:    slli a1, a1, 16
52; RV32I-NEXT:    srli a1, a1, 16
53; RV32I-NEXT:    andi a0, a0, 255
54; RV32I-NEXT:    sub a0, a0, a1
55; RV32I-NEXT:    srai a1, a0, 31
56; RV32I-NEXT:    xor a0, a0, a1
57; RV32I-NEXT:    sub a0, a0, a1
58; RV32I-NEXT:    ret
59;
60; RV64I-LABEL: abd_ext_i8_i16:
61; RV64I:       # %bb.0:
62; RV64I-NEXT:    slli a1, a1, 48
63; RV64I-NEXT:    srli a1, a1, 48
64; RV64I-NEXT:    andi a0, a0, 255
65; RV64I-NEXT:    sub a0, a0, a1
66; RV64I-NEXT:    srai a1, a0, 63
67; RV64I-NEXT:    xor a0, a0, a1
68; RV64I-NEXT:    sub a0, a0, a1
69; RV64I-NEXT:    ret
70;
71; ZBB-LABEL: abd_ext_i8_i16:
72; ZBB:       # %bb.0:
73; ZBB-NEXT:    zext.h a1, a1
74; ZBB-NEXT:    andi a0, a0, 255
75; ZBB-NEXT:    minu a2, a0, a1
76; ZBB-NEXT:    maxu a0, a0, a1
77; ZBB-NEXT:    sub a0, a0, a2
78; ZBB-NEXT:    ret
79  %aext = zext i8 %a to i64
80  %bext = zext i16 %b to i64
81  %sub = sub i64 %aext, %bext
82  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
83  %trunc = trunc i64 %abs to i8
84  ret i8 %trunc
85}
86
87define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
88; RV32I-LABEL: abd_ext_i8_undef:
89; RV32I:       # %bb.0:
90; RV32I-NEXT:    andi a1, a1, 255
91; RV32I-NEXT:    andi a0, a0, 255
92; RV32I-NEXT:    sub a0, a0, a1
93; RV32I-NEXT:    srai a1, a0, 31
94; RV32I-NEXT:    xor a0, a0, a1
95; RV32I-NEXT:    sub a0, a0, a1
96; RV32I-NEXT:    ret
97;
98; RV64I-LABEL: abd_ext_i8_undef:
99; RV64I:       # %bb.0:
100; RV64I-NEXT:    andi a1, a1, 255
101; RV64I-NEXT:    andi a0, a0, 255
102; RV64I-NEXT:    sub a0, a0, a1
103; RV64I-NEXT:    srai a1, a0, 63
104; RV64I-NEXT:    xor a0, a0, a1
105; RV64I-NEXT:    sub a0, a0, a1
106; RV64I-NEXT:    ret
107;
108; ZBB-LABEL: abd_ext_i8_undef:
109; ZBB:       # %bb.0:
110; ZBB-NEXT:    andi a1, a1, 255
111; ZBB-NEXT:    andi a0, a0, 255
112; ZBB-NEXT:    minu a2, a0, a1
113; ZBB-NEXT:    maxu a0, a0, a1
114; ZBB-NEXT:    sub a0, a0, a2
115; ZBB-NEXT:    ret
116  %aext = zext i8 %a to i64
117  %bext = zext i8 %b to i64
118  %sub = sub i64 %aext, %bext
119  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
120  %trunc = trunc i64 %abs to i8
121  ret i8 %trunc
122}
123
124define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
125; RV32I-LABEL: abd_ext_i16:
126; RV32I:       # %bb.0:
127; RV32I-NEXT:    lui a2, 16
128; RV32I-NEXT:    addi a2, a2, -1
129; RV32I-NEXT:    and a1, a1, a2
130; RV32I-NEXT:    and a0, a0, a2
131; RV32I-NEXT:    sub a0, a0, a1
132; RV32I-NEXT:    srai a1, a0, 31
133; RV32I-NEXT:    xor a0, a0, a1
134; RV32I-NEXT:    sub a0, a0, a1
135; RV32I-NEXT:    ret
136;
137; RV64I-LABEL: abd_ext_i16:
138; RV64I:       # %bb.0:
139; RV64I-NEXT:    lui a2, 16
140; RV64I-NEXT:    addiw a2, a2, -1
141; RV64I-NEXT:    and a1, a1, a2
142; RV64I-NEXT:    and a0, a0, a2
143; RV64I-NEXT:    sub a0, a0, a1
144; RV64I-NEXT:    srai a1, a0, 63
145; RV64I-NEXT:    xor a0, a0, a1
146; RV64I-NEXT:    sub a0, a0, a1
147; RV64I-NEXT:    ret
148;
149; ZBB-LABEL: abd_ext_i16:
150; ZBB:       # %bb.0:
151; ZBB-NEXT:    zext.h a1, a1
152; ZBB-NEXT:    zext.h a0, a0
153; ZBB-NEXT:    minu a2, a0, a1
154; ZBB-NEXT:    maxu a0, a0, a1
155; ZBB-NEXT:    sub a0, a0, a2
156; ZBB-NEXT:    ret
157  %aext = zext i16 %a to i64
158  %bext = zext i16 %b to i64
159  %sub = sub i64 %aext, %bext
160  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
161  %trunc = trunc i64 %abs to i16
162  ret i16 %trunc
163}
164
165define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
166; RV32I-LABEL: abd_ext_i16_i32:
167; RV32I:       # %bb.0:
168; RV32I-NEXT:    slli a0, a0, 16
169; RV32I-NEXT:    srli a0, a0, 16
170; RV32I-NEXT:    bltu a1, a0, .LBB4_2
171; RV32I-NEXT:  # %bb.1:
172; RV32I-NEXT:    sub a0, a1, a0
173; RV32I-NEXT:    ret
174; RV32I-NEXT:  .LBB4_2:
175; RV32I-NEXT:    sub a0, a0, a1
176; RV32I-NEXT:    ret
177;
178; RV64I-LABEL: abd_ext_i16_i32:
179; RV64I:       # %bb.0:
180; RV64I-NEXT:    slli a1, a1, 32
181; RV64I-NEXT:    slli a0, a0, 48
182; RV64I-NEXT:    srli a1, a1, 32
183; RV64I-NEXT:    srli a0, a0, 48
184; RV64I-NEXT:    sub a0, a0, a1
185; RV64I-NEXT:    srai a1, a0, 63
186; RV64I-NEXT:    xor a0, a0, a1
187; RV64I-NEXT:    sub a0, a0, a1
188; RV64I-NEXT:    ret
189;
190; RV32ZBB-LABEL: abd_ext_i16_i32:
191; RV32ZBB:       # %bb.0:
192; RV32ZBB-NEXT:    zext.h a0, a0
193; RV32ZBB-NEXT:    minu a2, a0, a1
194; RV32ZBB-NEXT:    maxu a0, a0, a1
195; RV32ZBB-NEXT:    sub a0, a0, a2
196; RV32ZBB-NEXT:    ret
197;
198; RV64ZBB-LABEL: abd_ext_i16_i32:
199; RV64ZBB:       # %bb.0:
200; RV64ZBB-NEXT:    slli a1, a1, 32
201; RV64ZBB-NEXT:    zext.h a0, a0
202; RV64ZBB-NEXT:    srli a1, a1, 32
203; RV64ZBB-NEXT:    minu a2, a0, a1
204; RV64ZBB-NEXT:    maxu a0, a0, a1
205; RV64ZBB-NEXT:    sub a0, a0, a2
206; RV64ZBB-NEXT:    ret
207  %aext = zext i16 %a to i64
208  %bext = zext i32 %b to i64
209  %sub = sub i64 %aext, %bext
210  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
211  %trunc = trunc i64 %abs to i16
212  ret i16 %trunc
213}
214
215define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
216; RV32I-LABEL: abd_ext_i16_undef:
217; RV32I:       # %bb.0:
218; RV32I-NEXT:    lui a2, 16
219; RV32I-NEXT:    addi a2, a2, -1
220; RV32I-NEXT:    and a1, a1, a2
221; RV32I-NEXT:    and a0, a0, a2
222; RV32I-NEXT:    sub a0, a0, a1
223; RV32I-NEXT:    srai a1, a0, 31
224; RV32I-NEXT:    xor a0, a0, a1
225; RV32I-NEXT:    sub a0, a0, a1
226; RV32I-NEXT:    ret
227;
228; RV64I-LABEL: abd_ext_i16_undef:
229; RV64I:       # %bb.0:
230; RV64I-NEXT:    lui a2, 16
231; RV64I-NEXT:    addiw a2, a2, -1
232; RV64I-NEXT:    and a1, a1, a2
233; RV64I-NEXT:    and a0, a0, a2
234; RV64I-NEXT:    sub a0, a0, a1
235; RV64I-NEXT:    srai a1, a0, 63
236; RV64I-NEXT:    xor a0, a0, a1
237; RV64I-NEXT:    sub a0, a0, a1
238; RV64I-NEXT:    ret
239;
240; ZBB-LABEL: abd_ext_i16_undef:
241; ZBB:       # %bb.0:
242; ZBB-NEXT:    zext.h a1, a1
243; ZBB-NEXT:    zext.h a0, a0
244; ZBB-NEXT:    minu a2, a0, a1
245; ZBB-NEXT:    maxu a0, a0, a1
246; ZBB-NEXT:    sub a0, a0, a2
247; ZBB-NEXT:    ret
248  %aext = zext i16 %a to i64
249  %bext = zext i16 %b to i64
250  %sub = sub i64 %aext, %bext
251  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
252  %trunc = trunc i64 %abs to i16
253  ret i16 %trunc
254}
255
256define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
257; RV32I-LABEL: abd_ext_i32:
258; RV32I:       # %bb.0:
259; RV32I-NEXT:    bltu a1, a0, .LBB6_2
260; RV32I-NEXT:  # %bb.1:
261; RV32I-NEXT:    sub a0, a1, a0
262; RV32I-NEXT:    ret
263; RV32I-NEXT:  .LBB6_2:
264; RV32I-NEXT:    sub a0, a0, a1
265; RV32I-NEXT:    ret
266;
267; RV64I-LABEL: abd_ext_i32:
268; RV64I:       # %bb.0:
269; RV64I-NEXT:    slli a1, a1, 32
270; RV64I-NEXT:    slli a0, a0, 32
271; RV64I-NEXT:    srli a1, a1, 32
272; RV64I-NEXT:    srli a0, a0, 32
273; RV64I-NEXT:    sub a0, a0, a1
274; RV64I-NEXT:    srai a1, a0, 63
275; RV64I-NEXT:    xor a0, a0, a1
276; RV64I-NEXT:    sub a0, a0, a1
277; RV64I-NEXT:    ret
278;
279; RV32ZBB-LABEL: abd_ext_i32:
280; RV32ZBB:       # %bb.0:
281; RV32ZBB-NEXT:    minu a2, a0, a1
282; RV32ZBB-NEXT:    maxu a0, a0, a1
283; RV32ZBB-NEXT:    sub a0, a0, a2
284; RV32ZBB-NEXT:    ret
285;
286; RV64ZBB-LABEL: abd_ext_i32:
287; RV64ZBB:       # %bb.0:
288; RV64ZBB-NEXT:    slli a1, a1, 32
289; RV64ZBB-NEXT:    slli a0, a0, 32
290; RV64ZBB-NEXT:    srli a1, a1, 32
291; RV64ZBB-NEXT:    srli a0, a0, 32
292; RV64ZBB-NEXT:    minu a2, a0, a1
293; RV64ZBB-NEXT:    maxu a0, a0, a1
294; RV64ZBB-NEXT:    sub a0, a0, a2
295; RV64ZBB-NEXT:    ret
296  %aext = zext i32 %a to i64
297  %bext = zext i32 %b to i64
298  %sub = sub i64 %aext, %bext
299  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
300  %trunc = trunc i64 %abs to i32
301  ret i32 %trunc
302}
303
304define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
305; RV32I-LABEL: abd_ext_i32_i16:
306; RV32I:       # %bb.0:
307; RV32I-NEXT:    slli a1, a1, 16
308; RV32I-NEXT:    srli a1, a1, 16
309; RV32I-NEXT:    bltu a1, a0, .LBB7_2
310; RV32I-NEXT:  # %bb.1:
311; RV32I-NEXT:    sub a0, a1, a0
312; RV32I-NEXT:    ret
313; RV32I-NEXT:  .LBB7_2:
314; RV32I-NEXT:    sub a0, a0, a1
315; RV32I-NEXT:    ret
316;
317; RV64I-LABEL: abd_ext_i32_i16:
318; RV64I:       # %bb.0:
319; RV64I-NEXT:    slli a0, a0, 32
320; RV64I-NEXT:    slli a1, a1, 48
321; RV64I-NEXT:    srli a0, a0, 32
322; RV64I-NEXT:    srli a1, a1, 48
323; RV64I-NEXT:    sub a0, a0, a1
324; RV64I-NEXT:    srai a1, a0, 63
325; RV64I-NEXT:    xor a0, a0, a1
326; RV64I-NEXT:    sub a0, a0, a1
327; RV64I-NEXT:    ret
328;
329; RV32ZBB-LABEL: abd_ext_i32_i16:
330; RV32ZBB:       # %bb.0:
331; RV32ZBB-NEXT:    zext.h a1, a1
332; RV32ZBB-NEXT:    minu a2, a0, a1
333; RV32ZBB-NEXT:    maxu a0, a0, a1
334; RV32ZBB-NEXT:    sub a0, a0, a2
335; RV32ZBB-NEXT:    ret
336;
337; RV64ZBB-LABEL: abd_ext_i32_i16:
338; RV64ZBB:       # %bb.0:
339; RV64ZBB-NEXT:    slli a0, a0, 32
340; RV64ZBB-NEXT:    zext.h a1, a1
341; RV64ZBB-NEXT:    srli a0, a0, 32
342; RV64ZBB-NEXT:    minu a2, a0, a1
343; RV64ZBB-NEXT:    maxu a0, a0, a1
344; RV64ZBB-NEXT:    sub a0, a0, a2
345; RV64ZBB-NEXT:    ret
346  %aext = zext i32 %a to i64
347  %bext = zext i16 %b to i64
348  %sub = sub i64 %aext, %bext
349  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
350  %trunc = trunc i64 %abs to i32
351  ret i32 %trunc
352}
353
354define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
355; RV32I-LABEL: abd_ext_i32_undef:
356; RV32I:       # %bb.0:
357; RV32I-NEXT:    bltu a1, a0, .LBB8_2
358; RV32I-NEXT:  # %bb.1:
359; RV32I-NEXT:    sub a0, a1, a0
360; RV32I-NEXT:    ret
361; RV32I-NEXT:  .LBB8_2:
362; RV32I-NEXT:    sub a0, a0, a1
363; RV32I-NEXT:    ret
364;
365; RV64I-LABEL: abd_ext_i32_undef:
366; RV64I:       # %bb.0:
367; RV64I-NEXT:    slli a1, a1, 32
368; RV64I-NEXT:    slli a0, a0, 32
369; RV64I-NEXT:    srli a1, a1, 32
370; RV64I-NEXT:    srli a0, a0, 32
371; RV64I-NEXT:    sub a0, a0, a1
372; RV64I-NEXT:    srai a1, a0, 63
373; RV64I-NEXT:    xor a0, a0, a1
374; RV64I-NEXT:    sub a0, a0, a1
375; RV64I-NEXT:    ret
376;
377; RV32ZBB-LABEL: abd_ext_i32_undef:
378; RV32ZBB:       # %bb.0:
379; RV32ZBB-NEXT:    minu a2, a0, a1
380; RV32ZBB-NEXT:    maxu a0, a0, a1
381; RV32ZBB-NEXT:    sub a0, a0, a2
382; RV32ZBB-NEXT:    ret
383;
384; RV64ZBB-LABEL: abd_ext_i32_undef:
385; RV64ZBB:       # %bb.0:
386; RV64ZBB-NEXT:    slli a1, a1, 32
387; RV64ZBB-NEXT:    slli a0, a0, 32
388; RV64ZBB-NEXT:    srli a1, a1, 32
389; RV64ZBB-NEXT:    srli a0, a0, 32
390; RV64ZBB-NEXT:    minu a2, a0, a1
391; RV64ZBB-NEXT:    maxu a0, a0, a1
392; RV64ZBB-NEXT:    sub a0, a0, a2
393; RV64ZBB-NEXT:    ret
394  %aext = zext i32 %a to i64
395  %bext = zext i32 %b to i64
396  %sub = sub i64 %aext, %bext
397  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
398  %trunc = trunc i64 %abs to i32
399  ret i32 %trunc
400}
401
402define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
403; RV32I-LABEL: abd_ext_i64:
404; RV32I:       # %bb.0:
405; RV32I-NEXT:    sltu a4, a0, a2
406; RV32I-NEXT:    sub a3, a1, a3
407; RV32I-NEXT:    sub a3, a3, a4
408; RV32I-NEXT:    sub a2, a0, a2
409; RV32I-NEXT:    beq a3, a1, .LBB9_2
410; RV32I-NEXT:  # %bb.1:
411; RV32I-NEXT:    sltu a0, a1, a3
412; RV32I-NEXT:    j .LBB9_3
413; RV32I-NEXT:  .LBB9_2:
414; RV32I-NEXT:    sltu a0, a0, a2
415; RV32I-NEXT:  .LBB9_3:
416; RV32I-NEXT:    neg a1, a0
417; RV32I-NEXT:    xor a2, a2, a1
418; RV32I-NEXT:    xor a3, a3, a1
419; RV32I-NEXT:    sltu a1, a2, a1
420; RV32I-NEXT:    add a3, a3, a0
421; RV32I-NEXT:    sub a1, a3, a1
422; RV32I-NEXT:    add a0, a2, a0
423; RV32I-NEXT:    ret
424;
425; RV64I-LABEL: abd_ext_i64:
426; RV64I:       # %bb.0:
427; RV64I-NEXT:    bltu a1, a0, .LBB9_2
428; RV64I-NEXT:  # %bb.1:
429; RV64I-NEXT:    sub a0, a1, a0
430; RV64I-NEXT:    ret
431; RV64I-NEXT:  .LBB9_2:
432; RV64I-NEXT:    sub a0, a0, a1
433; RV64I-NEXT:    ret
434;
435; RV32ZBB-LABEL: abd_ext_i64:
436; RV32ZBB:       # %bb.0:
437; RV32ZBB-NEXT:    sltu a4, a0, a2
438; RV32ZBB-NEXT:    sub a3, a1, a3
439; RV32ZBB-NEXT:    sub a3, a3, a4
440; RV32ZBB-NEXT:    sub a2, a0, a2
441; RV32ZBB-NEXT:    beq a3, a1, .LBB9_2
442; RV32ZBB-NEXT:  # %bb.1:
443; RV32ZBB-NEXT:    sltu a0, a1, a3
444; RV32ZBB-NEXT:    j .LBB9_3
445; RV32ZBB-NEXT:  .LBB9_2:
446; RV32ZBB-NEXT:    sltu a0, a0, a2
447; RV32ZBB-NEXT:  .LBB9_3:
448; RV32ZBB-NEXT:    neg a1, a0
449; RV32ZBB-NEXT:    xor a2, a2, a1
450; RV32ZBB-NEXT:    xor a3, a3, a1
451; RV32ZBB-NEXT:    sltu a1, a2, a1
452; RV32ZBB-NEXT:    add a3, a3, a0
453; RV32ZBB-NEXT:    sub a1, a3, a1
454; RV32ZBB-NEXT:    add a0, a2, a0
455; RV32ZBB-NEXT:    ret
456;
457; RV64ZBB-LABEL: abd_ext_i64:
458; RV64ZBB:       # %bb.0:
459; RV64ZBB-NEXT:    minu a2, a0, a1
460; RV64ZBB-NEXT:    maxu a0, a0, a1
461; RV64ZBB-NEXT:    sub a0, a0, a2
462; RV64ZBB-NEXT:    ret
463  %aext = zext i64 %a to i128
464  %bext = zext i64 %b to i128
465  %sub = sub i128 %aext, %bext
466  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
467  %trunc = trunc i128 %abs to i64
468  ret i64 %trunc
469}
470
471define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
472; RV32I-LABEL: abd_ext_i64_undef:
473; RV32I:       # %bb.0:
474; RV32I-NEXT:    sltu a4, a0, a2
475; RV32I-NEXT:    sub a3, a1, a3
476; RV32I-NEXT:    sub a3, a3, a4
477; RV32I-NEXT:    sub a2, a0, a2
478; RV32I-NEXT:    beq a3, a1, .LBB10_2
479; RV32I-NEXT:  # %bb.1:
480; RV32I-NEXT:    sltu a0, a1, a3
481; RV32I-NEXT:    j .LBB10_3
482; RV32I-NEXT:  .LBB10_2:
483; RV32I-NEXT:    sltu a0, a0, a2
484; RV32I-NEXT:  .LBB10_3:
485; RV32I-NEXT:    neg a1, a0
486; RV32I-NEXT:    xor a2, a2, a1
487; RV32I-NEXT:    xor a3, a3, a1
488; RV32I-NEXT:    sltu a1, a2, a1
489; RV32I-NEXT:    add a3, a3, a0
490; RV32I-NEXT:    sub a1, a3, a1
491; RV32I-NEXT:    add a0, a2, a0
492; RV32I-NEXT:    ret
493;
494; RV64I-LABEL: abd_ext_i64_undef:
495; RV64I:       # %bb.0:
496; RV64I-NEXT:    bltu a1, a0, .LBB10_2
497; RV64I-NEXT:  # %bb.1:
498; RV64I-NEXT:    sub a0, a1, a0
499; RV64I-NEXT:    ret
500; RV64I-NEXT:  .LBB10_2:
501; RV64I-NEXT:    sub a0, a0, a1
502; RV64I-NEXT:    ret
503;
504; RV32ZBB-LABEL: abd_ext_i64_undef:
505; RV32ZBB:       # %bb.0:
506; RV32ZBB-NEXT:    sltu a4, a0, a2
507; RV32ZBB-NEXT:    sub a3, a1, a3
508; RV32ZBB-NEXT:    sub a3, a3, a4
509; RV32ZBB-NEXT:    sub a2, a0, a2
510; RV32ZBB-NEXT:    beq a3, a1, .LBB10_2
511; RV32ZBB-NEXT:  # %bb.1:
512; RV32ZBB-NEXT:    sltu a0, a1, a3
513; RV32ZBB-NEXT:    j .LBB10_3
514; RV32ZBB-NEXT:  .LBB10_2:
515; RV32ZBB-NEXT:    sltu a0, a0, a2
516; RV32ZBB-NEXT:  .LBB10_3:
517; RV32ZBB-NEXT:    neg a1, a0
518; RV32ZBB-NEXT:    xor a2, a2, a1
519; RV32ZBB-NEXT:    xor a3, a3, a1
520; RV32ZBB-NEXT:    sltu a1, a2, a1
521; RV32ZBB-NEXT:    add a3, a3, a0
522; RV32ZBB-NEXT:    sub a1, a3, a1
523; RV32ZBB-NEXT:    add a0, a2, a0
524; RV32ZBB-NEXT:    ret
525;
526; RV64ZBB-LABEL: abd_ext_i64_undef:
527; RV64ZBB:       # %bb.0:
528; RV64ZBB-NEXT:    minu a2, a0, a1
529; RV64ZBB-NEXT:    maxu a0, a0, a1
530; RV64ZBB-NEXT:    sub a0, a0, a2
531; RV64ZBB-NEXT:    ret
532  %aext = zext i64 %a to i128
533  %bext = zext i64 %b to i128
534  %sub = sub i128 %aext, %bext
535  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
536  %trunc = trunc i128 %abs to i64
537  ret i64 %trunc
538}
539
540define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
541; RV32I-LABEL: abd_ext_i128:
542; RV32I:       # %bb.0:
543; RV32I-NEXT:    lw a3, 0(a2)
544; RV32I-NEXT:    lw a5, 4(a2)
545; RV32I-NEXT:    lw a6, 8(a2)
546; RV32I-NEXT:    lw a7, 12(a2)
547; RV32I-NEXT:    lw a2, 8(a1)
548; RV32I-NEXT:    lw a4, 12(a1)
549; RV32I-NEXT:    lw t0, 0(a1)
550; RV32I-NEXT:    lw a1, 4(a1)
551; RV32I-NEXT:    sltu t1, a2, a6
552; RV32I-NEXT:    sub a7, a4, a7
553; RV32I-NEXT:    sltu t2, t0, a3
554; RV32I-NEXT:    sub a7, a7, t1
555; RV32I-NEXT:    mv t1, t2
556; RV32I-NEXT:    beq a1, a5, .LBB11_2
557; RV32I-NEXT:  # %bb.1:
558; RV32I-NEXT:    sltu t1, a1, a5
559; RV32I-NEXT:  .LBB11_2:
560; RV32I-NEXT:    sub t3, a2, a6
561; RV32I-NEXT:    sltu a6, t3, t1
562; RV32I-NEXT:    sub a6, a7, a6
563; RV32I-NEXT:    sub a7, t3, t1
564; RV32I-NEXT:    beq a6, a4, .LBB11_4
565; RV32I-NEXT:  # %bb.3:
566; RV32I-NEXT:    sltu t1, a4, a6
567; RV32I-NEXT:    j .LBB11_5
568; RV32I-NEXT:  .LBB11_4:
569; RV32I-NEXT:    sltu t1, a2, a7
570; RV32I-NEXT:  .LBB11_5:
571; RV32I-NEXT:    sub a5, a1, a5
572; RV32I-NEXT:    sub a5, a5, t2
573; RV32I-NEXT:    sub a3, t0, a3
574; RV32I-NEXT:    beq a5, a1, .LBB11_7
575; RV32I-NEXT:  # %bb.6:
576; RV32I-NEXT:    sltu a1, a1, a5
577; RV32I-NEXT:    j .LBB11_8
578; RV32I-NEXT:  .LBB11_7:
579; RV32I-NEXT:    sltu a1, t0, a3
580; RV32I-NEXT:  .LBB11_8:
581; RV32I-NEXT:    xor a4, a6, a4
582; RV32I-NEXT:    xor a2, a7, a2
583; RV32I-NEXT:    or a2, a2, a4
584; RV32I-NEXT:    beqz a2, .LBB11_10
585; RV32I-NEXT:  # %bb.9:
586; RV32I-NEXT:    mv a1, t1
587; RV32I-NEXT:  .LBB11_10:
588; RV32I-NEXT:    neg t0, a1
589; RV32I-NEXT:    xor a2, a7, t0
590; RV32I-NEXT:    xor a6, a6, t0
591; RV32I-NEXT:    xor a4, a3, t0
592; RV32I-NEXT:    sltu a3, a2, t0
593; RV32I-NEXT:    add a7, a6, a1
594; RV32I-NEXT:    sltu a6, a4, t0
595; RV32I-NEXT:    sub a3, a7, a3
596; RV32I-NEXT:    xor t1, a5, t0
597; RV32I-NEXT:    mv a7, a6
598; RV32I-NEXT:    beqz a5, .LBB11_12
599; RV32I-NEXT:  # %bb.11:
600; RV32I-NEXT:    sltu a7, t1, t0
601; RV32I-NEXT:  .LBB11_12:
602; RV32I-NEXT:    add a2, a2, a1
603; RV32I-NEXT:    add t1, t1, a1
604; RV32I-NEXT:    add a1, a4, a1
605; RV32I-NEXT:    sltu a4, a2, a7
606; RV32I-NEXT:    sub a2, a2, a7
607; RV32I-NEXT:    sub a5, t1, a6
608; RV32I-NEXT:    sub a3, a3, a4
609; RV32I-NEXT:    sw a1, 0(a0)
610; RV32I-NEXT:    sw a5, 4(a0)
611; RV32I-NEXT:    sw a2, 8(a0)
612; RV32I-NEXT:    sw a3, 12(a0)
613; RV32I-NEXT:    ret
614;
615; RV64I-LABEL: abd_ext_i128:
616; RV64I:       # %bb.0:
617; RV64I-NEXT:    sltu a4, a0, a2
618; RV64I-NEXT:    sub a3, a1, a3
619; RV64I-NEXT:    sub a3, a3, a4
620; RV64I-NEXT:    sub a2, a0, a2
621; RV64I-NEXT:    beq a3, a1, .LBB11_2
622; RV64I-NEXT:  # %bb.1:
623; RV64I-NEXT:    sltu a0, a1, a3
624; RV64I-NEXT:    j .LBB11_3
625; RV64I-NEXT:  .LBB11_2:
626; RV64I-NEXT:    sltu a0, a0, a2
627; RV64I-NEXT:  .LBB11_3:
628; RV64I-NEXT:    neg a1, a0
629; RV64I-NEXT:    xor a2, a2, a1
630; RV64I-NEXT:    xor a3, a3, a1
631; RV64I-NEXT:    sltu a1, a2, a1
632; RV64I-NEXT:    add a3, a3, a0
633; RV64I-NEXT:    sub a1, a3, a1
634; RV64I-NEXT:    add a0, a2, a0
635; RV64I-NEXT:    ret
636;
637; RV32ZBB-LABEL: abd_ext_i128:
638; RV32ZBB:       # %bb.0:
639; RV32ZBB-NEXT:    lw a3, 0(a2)
640; RV32ZBB-NEXT:    lw a5, 4(a2)
641; RV32ZBB-NEXT:    lw a6, 8(a2)
642; RV32ZBB-NEXT:    lw a7, 12(a2)
643; RV32ZBB-NEXT:    lw a2, 8(a1)
644; RV32ZBB-NEXT:    lw a4, 12(a1)
645; RV32ZBB-NEXT:    lw t0, 0(a1)
646; RV32ZBB-NEXT:    lw a1, 4(a1)
647; RV32ZBB-NEXT:    sltu t1, a2, a6
648; RV32ZBB-NEXT:    sub a7, a4, a7
649; RV32ZBB-NEXT:    sltu t2, t0, a3
650; RV32ZBB-NEXT:    sub a7, a7, t1
651; RV32ZBB-NEXT:    mv t1, t2
652; RV32ZBB-NEXT:    beq a1, a5, .LBB11_2
653; RV32ZBB-NEXT:  # %bb.1:
654; RV32ZBB-NEXT:    sltu t1, a1, a5
655; RV32ZBB-NEXT:  .LBB11_2:
656; RV32ZBB-NEXT:    sub t3, a2, a6
657; RV32ZBB-NEXT:    sltu a6, t3, t1
658; RV32ZBB-NEXT:    sub a6, a7, a6
659; RV32ZBB-NEXT:    sub a7, t3, t1
660; RV32ZBB-NEXT:    beq a6, a4, .LBB11_4
661; RV32ZBB-NEXT:  # %bb.3:
662; RV32ZBB-NEXT:    sltu t1, a4, a6
663; RV32ZBB-NEXT:    j .LBB11_5
664; RV32ZBB-NEXT:  .LBB11_4:
665; RV32ZBB-NEXT:    sltu t1, a2, a7
666; RV32ZBB-NEXT:  .LBB11_5:
667; RV32ZBB-NEXT:    sub a5, a1, a5
668; RV32ZBB-NEXT:    sub a5, a5, t2
669; RV32ZBB-NEXT:    sub a3, t0, a3
670; RV32ZBB-NEXT:    beq a5, a1, .LBB11_7
671; RV32ZBB-NEXT:  # %bb.6:
672; RV32ZBB-NEXT:    sltu a1, a1, a5
673; RV32ZBB-NEXT:    j .LBB11_8
674; RV32ZBB-NEXT:  .LBB11_7:
675; RV32ZBB-NEXT:    sltu a1, t0, a3
676; RV32ZBB-NEXT:  .LBB11_8:
677; RV32ZBB-NEXT:    xor a4, a6, a4
678; RV32ZBB-NEXT:    xor a2, a7, a2
679; RV32ZBB-NEXT:    or a2, a2, a4
680; RV32ZBB-NEXT:    beqz a2, .LBB11_10
681; RV32ZBB-NEXT:  # %bb.9:
682; RV32ZBB-NEXT:    mv a1, t1
683; RV32ZBB-NEXT:  .LBB11_10:
684; RV32ZBB-NEXT:    neg t0, a1
685; RV32ZBB-NEXT:    xor a2, a7, t0
686; RV32ZBB-NEXT:    xor a6, a6, t0
687; RV32ZBB-NEXT:    xor a4, a3, t0
688; RV32ZBB-NEXT:    sltu a3, a2, t0
689; RV32ZBB-NEXT:    add a7, a6, a1
690; RV32ZBB-NEXT:    sltu a6, a4, t0
691; RV32ZBB-NEXT:    sub a3, a7, a3
692; RV32ZBB-NEXT:    xor t1, a5, t0
693; RV32ZBB-NEXT:    mv a7, a6
694; RV32ZBB-NEXT:    beqz a5, .LBB11_12
695; RV32ZBB-NEXT:  # %bb.11:
696; RV32ZBB-NEXT:    sltu a7, t1, t0
697; RV32ZBB-NEXT:  .LBB11_12:
698; RV32ZBB-NEXT:    add a2, a2, a1
699; RV32ZBB-NEXT:    add t1, t1, a1
700; RV32ZBB-NEXT:    add a1, a4, a1
701; RV32ZBB-NEXT:    sltu a4, a2, a7
702; RV32ZBB-NEXT:    sub a2, a2, a7
703; RV32ZBB-NEXT:    sub a5, t1, a6
704; RV32ZBB-NEXT:    sub a3, a3, a4
705; RV32ZBB-NEXT:    sw a1, 0(a0)
706; RV32ZBB-NEXT:    sw a5, 4(a0)
707; RV32ZBB-NEXT:    sw a2, 8(a0)
708; RV32ZBB-NEXT:    sw a3, 12(a0)
709; RV32ZBB-NEXT:    ret
710;
711; RV64ZBB-LABEL: abd_ext_i128:
712; RV64ZBB:       # %bb.0:
713; RV64ZBB-NEXT:    sltu a4, a0, a2
714; RV64ZBB-NEXT:    sub a3, a1, a3
715; RV64ZBB-NEXT:    sub a3, a3, a4
716; RV64ZBB-NEXT:    sub a2, a0, a2
717; RV64ZBB-NEXT:    beq a3, a1, .LBB11_2
718; RV64ZBB-NEXT:  # %bb.1:
719; RV64ZBB-NEXT:    sltu a0, a1, a3
720; RV64ZBB-NEXT:    j .LBB11_3
721; RV64ZBB-NEXT:  .LBB11_2:
722; RV64ZBB-NEXT:    sltu a0, a0, a2
723; RV64ZBB-NEXT:  .LBB11_3:
724; RV64ZBB-NEXT:    neg a1, a0
725; RV64ZBB-NEXT:    xor a2, a2, a1
726; RV64ZBB-NEXT:    xor a3, a3, a1
727; RV64ZBB-NEXT:    sltu a1, a2, a1
728; RV64ZBB-NEXT:    add a3, a3, a0
729; RV64ZBB-NEXT:    sub a1, a3, a1
730; RV64ZBB-NEXT:    add a0, a2, a0
731; RV64ZBB-NEXT:    ret
732  %aext = zext i128 %a to i256
733  %bext = zext i128 %b to i256
734  %sub = sub i256 %aext, %bext
735  %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
736  %trunc = trunc i256 %abs to i128
737  ret i128 %trunc
738}
739
740define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
741; RV32I-LABEL: abd_ext_i128_undef:
742; RV32I:       # %bb.0:
743; RV32I-NEXT:    lw a3, 0(a2)
744; RV32I-NEXT:    lw a5, 4(a2)
745; RV32I-NEXT:    lw a6, 8(a2)
746; RV32I-NEXT:    lw a7, 12(a2)
747; RV32I-NEXT:    lw a2, 8(a1)
748; RV32I-NEXT:    lw a4, 12(a1)
749; RV32I-NEXT:    lw t0, 0(a1)
750; RV32I-NEXT:    lw a1, 4(a1)
751; RV32I-NEXT:    sltu t1, a2, a6
752; RV32I-NEXT:    sub a7, a4, a7
753; RV32I-NEXT:    sltu t2, t0, a3
754; RV32I-NEXT:    sub a7, a7, t1
755; RV32I-NEXT:    mv t1, t2
756; RV32I-NEXT:    beq a1, a5, .LBB12_2
757; RV32I-NEXT:  # %bb.1:
758; RV32I-NEXT:    sltu t1, a1, a5
759; RV32I-NEXT:  .LBB12_2:
760; RV32I-NEXT:    sub t3, a2, a6
761; RV32I-NEXT:    sltu a6, t3, t1
762; RV32I-NEXT:    sub a6, a7, a6
763; RV32I-NEXT:    sub a7, t3, t1
764; RV32I-NEXT:    beq a6, a4, .LBB12_4
765; RV32I-NEXT:  # %bb.3:
766; RV32I-NEXT:    sltu t1, a4, a6
767; RV32I-NEXT:    j .LBB12_5
768; RV32I-NEXT:  .LBB12_4:
769; RV32I-NEXT:    sltu t1, a2, a7
770; RV32I-NEXT:  .LBB12_5:
771; RV32I-NEXT:    sub a5, a1, a5
772; RV32I-NEXT:    sub a5, a5, t2
773; RV32I-NEXT:    sub a3, t0, a3
774; RV32I-NEXT:    beq a5, a1, .LBB12_7
775; RV32I-NEXT:  # %bb.6:
776; RV32I-NEXT:    sltu a1, a1, a5
777; RV32I-NEXT:    j .LBB12_8
778; RV32I-NEXT:  .LBB12_7:
779; RV32I-NEXT:    sltu a1, t0, a3
780; RV32I-NEXT:  .LBB12_8:
781; RV32I-NEXT:    xor a4, a6, a4
782; RV32I-NEXT:    xor a2, a7, a2
783; RV32I-NEXT:    or a2, a2, a4
784; RV32I-NEXT:    beqz a2, .LBB12_10
785; RV32I-NEXT:  # %bb.9:
786; RV32I-NEXT:    mv a1, t1
787; RV32I-NEXT:  .LBB12_10:
788; RV32I-NEXT:    neg t0, a1
789; RV32I-NEXT:    xor a2, a7, t0
790; RV32I-NEXT:    xor a6, a6, t0
791; RV32I-NEXT:    xor a4, a3, t0
792; RV32I-NEXT:    sltu a3, a2, t0
793; RV32I-NEXT:    add a7, a6, a1
794; RV32I-NEXT:    sltu a6, a4, t0
795; RV32I-NEXT:    sub a3, a7, a3
796; RV32I-NEXT:    xor t1, a5, t0
797; RV32I-NEXT:    mv a7, a6
798; RV32I-NEXT:    beqz a5, .LBB12_12
799; RV32I-NEXT:  # %bb.11:
800; RV32I-NEXT:    sltu a7, t1, t0
801; RV32I-NEXT:  .LBB12_12:
802; RV32I-NEXT:    add a2, a2, a1
803; RV32I-NEXT:    add t1, t1, a1
804; RV32I-NEXT:    add a1, a4, a1
805; RV32I-NEXT:    sltu a4, a2, a7
806; RV32I-NEXT:    sub a2, a2, a7
807; RV32I-NEXT:    sub a5, t1, a6
808; RV32I-NEXT:    sub a3, a3, a4
809; RV32I-NEXT:    sw a1, 0(a0)
810; RV32I-NEXT:    sw a5, 4(a0)
811; RV32I-NEXT:    sw a2, 8(a0)
812; RV32I-NEXT:    sw a3, 12(a0)
813; RV32I-NEXT:    ret
814;
815; RV64I-LABEL: abd_ext_i128_undef:
816; RV64I:       # %bb.0:
817; RV64I-NEXT:    sltu a4, a0, a2
818; RV64I-NEXT:    sub a3, a1, a3
819; RV64I-NEXT:    sub a3, a3, a4
820; RV64I-NEXT:    sub a2, a0, a2
821; RV64I-NEXT:    beq a3, a1, .LBB12_2
822; RV64I-NEXT:  # %bb.1:
823; RV64I-NEXT:    sltu a0, a1, a3
824; RV64I-NEXT:    j .LBB12_3
825; RV64I-NEXT:  .LBB12_2:
826; RV64I-NEXT:    sltu a0, a0, a2
827; RV64I-NEXT:  .LBB12_3:
828; RV64I-NEXT:    neg a1, a0
829; RV64I-NEXT:    xor a2, a2, a1
830; RV64I-NEXT:    xor a3, a3, a1
831; RV64I-NEXT:    sltu a1, a2, a1
832; RV64I-NEXT:    add a3, a3, a0
833; RV64I-NEXT:    sub a1, a3, a1
834; RV64I-NEXT:    add a0, a2, a0
835; RV64I-NEXT:    ret
836;
837; RV32ZBB-LABEL: abd_ext_i128_undef:
838; RV32ZBB:       # %bb.0:
839; RV32ZBB-NEXT:    lw a3, 0(a2)
840; RV32ZBB-NEXT:    lw a5, 4(a2)
841; RV32ZBB-NEXT:    lw a6, 8(a2)
842; RV32ZBB-NEXT:    lw a7, 12(a2)
843; RV32ZBB-NEXT:    lw a2, 8(a1)
844; RV32ZBB-NEXT:    lw a4, 12(a1)
845; RV32ZBB-NEXT:    lw t0, 0(a1)
846; RV32ZBB-NEXT:    lw a1, 4(a1)
847; RV32ZBB-NEXT:    sltu t1, a2, a6
848; RV32ZBB-NEXT:    sub a7, a4, a7
849; RV32ZBB-NEXT:    sltu t2, t0, a3
850; RV32ZBB-NEXT:    sub a7, a7, t1
851; RV32ZBB-NEXT:    mv t1, t2
852; RV32ZBB-NEXT:    beq a1, a5, .LBB12_2
853; RV32ZBB-NEXT:  # %bb.1:
854; RV32ZBB-NEXT:    sltu t1, a1, a5
855; RV32ZBB-NEXT:  .LBB12_2:
856; RV32ZBB-NEXT:    sub t3, a2, a6
857; RV32ZBB-NEXT:    sltu a6, t3, t1
858; RV32ZBB-NEXT:    sub a6, a7, a6
859; RV32ZBB-NEXT:    sub a7, t3, t1
860; RV32ZBB-NEXT:    beq a6, a4, .LBB12_4
861; RV32ZBB-NEXT:  # %bb.3:
862; RV32ZBB-NEXT:    sltu t1, a4, a6
863; RV32ZBB-NEXT:    j .LBB12_5
864; RV32ZBB-NEXT:  .LBB12_4:
865; RV32ZBB-NEXT:    sltu t1, a2, a7
866; RV32ZBB-NEXT:  .LBB12_5:
867; RV32ZBB-NEXT:    sub a5, a1, a5
868; RV32ZBB-NEXT:    sub a5, a5, t2
869; RV32ZBB-NEXT:    sub a3, t0, a3
870; RV32ZBB-NEXT:    beq a5, a1, .LBB12_7
871; RV32ZBB-NEXT:  # %bb.6:
872; RV32ZBB-NEXT:    sltu a1, a1, a5
873; RV32ZBB-NEXT:    j .LBB12_8
874; RV32ZBB-NEXT:  .LBB12_7:
875; RV32ZBB-NEXT:    sltu a1, t0, a3
876; RV32ZBB-NEXT:  .LBB12_8:
877; RV32ZBB-NEXT:    xor a4, a6, a4
878; RV32ZBB-NEXT:    xor a2, a7, a2
879; RV32ZBB-NEXT:    or a2, a2, a4
880; RV32ZBB-NEXT:    beqz a2, .LBB12_10
881; RV32ZBB-NEXT:  # %bb.9:
882; RV32ZBB-NEXT:    mv a1, t1
883; RV32ZBB-NEXT:  .LBB12_10:
884; RV32ZBB-NEXT:    neg t0, a1
885; RV32ZBB-NEXT:    xor a2, a7, t0
886; RV32ZBB-NEXT:    xor a6, a6, t0
887; RV32ZBB-NEXT:    xor a4, a3, t0
888; RV32ZBB-NEXT:    sltu a3, a2, t0
889; RV32ZBB-NEXT:    add a7, a6, a1
890; RV32ZBB-NEXT:    sltu a6, a4, t0
891; RV32ZBB-NEXT:    sub a3, a7, a3
892; RV32ZBB-NEXT:    xor t1, a5, t0
893; RV32ZBB-NEXT:    mv a7, a6
894; RV32ZBB-NEXT:    beqz a5, .LBB12_12
895; RV32ZBB-NEXT:  # %bb.11:
896; RV32ZBB-NEXT:    sltu a7, t1, t0
897; RV32ZBB-NEXT:  .LBB12_12:
898; RV32ZBB-NEXT:    add a2, a2, a1
899; RV32ZBB-NEXT:    add t1, t1, a1
900; RV32ZBB-NEXT:    add a1, a4, a1
901; RV32ZBB-NEXT:    sltu a4, a2, a7
902; RV32ZBB-NEXT:    sub a2, a2, a7
903; RV32ZBB-NEXT:    sub a5, t1, a6
904; RV32ZBB-NEXT:    sub a3, a3, a4
905; RV32ZBB-NEXT:    sw a1, 0(a0)
906; RV32ZBB-NEXT:    sw a5, 4(a0)
907; RV32ZBB-NEXT:    sw a2, 8(a0)
908; RV32ZBB-NEXT:    sw a3, 12(a0)
909; RV32ZBB-NEXT:    ret
910;
911; RV64ZBB-LABEL: abd_ext_i128_undef:
912; RV64ZBB:       # %bb.0:
913; RV64ZBB-NEXT:    sltu a4, a0, a2
914; RV64ZBB-NEXT:    sub a3, a1, a3
915; RV64ZBB-NEXT:    sub a3, a3, a4
916; RV64ZBB-NEXT:    sub a2, a0, a2
917; RV64ZBB-NEXT:    beq a3, a1, .LBB12_2
918; RV64ZBB-NEXT:  # %bb.1:
919; RV64ZBB-NEXT:    sltu a0, a1, a3
920; RV64ZBB-NEXT:    j .LBB12_3
921; RV64ZBB-NEXT:  .LBB12_2:
922; RV64ZBB-NEXT:    sltu a0, a0, a2
923; RV64ZBB-NEXT:  .LBB12_3:
924; RV64ZBB-NEXT:    neg a1, a0
925; RV64ZBB-NEXT:    xor a2, a2, a1
926; RV64ZBB-NEXT:    xor a3, a3, a1
927; RV64ZBB-NEXT:    sltu a1, a2, a1
928; RV64ZBB-NEXT:    add a3, a3, a0
929; RV64ZBB-NEXT:    sub a1, a3, a1
930; RV64ZBB-NEXT:    add a0, a2, a0
931; RV64ZBB-NEXT:    ret
932  %aext = zext i128 %a to i256
933  %bext = zext i128 %b to i256
934  %sub = sub i256 %aext, %bext
935  %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
936  %trunc = trunc i256 %abs to i128
937  ret i128 %trunc
938}
939
940;
941; sub(umax(a,b),umin(a,b)) -> abdu(a,b)
942;
943
944define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
945; RV32I-LABEL: abd_minmax_i8:
946; RV32I:       # %bb.0:
947; RV32I-NEXT:    andi a1, a1, 255
948; RV32I-NEXT:    andi a0, a0, 255
949; RV32I-NEXT:    sub a0, a0, a1
950; RV32I-NEXT:    srai a1, a0, 31
951; RV32I-NEXT:    xor a0, a0, a1
952; RV32I-NEXT:    sub a0, a0, a1
953; RV32I-NEXT:    ret
954;
955; RV64I-LABEL: abd_minmax_i8:
956; RV64I:       # %bb.0:
957; RV64I-NEXT:    andi a1, a1, 255
958; RV64I-NEXT:    andi a0, a0, 255
959; RV64I-NEXT:    sub a0, a0, a1
960; RV64I-NEXT:    srai a1, a0, 63
961; RV64I-NEXT:    xor a0, a0, a1
962; RV64I-NEXT:    sub a0, a0, a1
963; RV64I-NEXT:    ret
964;
965; ZBB-LABEL: abd_minmax_i8:
966; ZBB:       # %bb.0:
967; ZBB-NEXT:    andi a1, a1, 255
968; ZBB-NEXT:    andi a0, a0, 255
969; ZBB-NEXT:    minu a2, a0, a1
970; ZBB-NEXT:    maxu a0, a0, a1
971; ZBB-NEXT:    sub a0, a0, a2
972; ZBB-NEXT:    ret
973  %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
974  %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
975  %sub = sub i8 %max, %min
976  ret i8 %sub
977}
978
979define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
980; RV32I-LABEL: abd_minmax_i16:
981; RV32I:       # %bb.0:
982; RV32I-NEXT:    lui a2, 16
983; RV32I-NEXT:    addi a2, a2, -1
984; RV32I-NEXT:    and a1, a1, a2
985; RV32I-NEXT:    and a0, a0, a2
986; RV32I-NEXT:    sub a0, a0, a1
987; RV32I-NEXT:    srai a1, a0, 31
988; RV32I-NEXT:    xor a0, a0, a1
989; RV32I-NEXT:    sub a0, a0, a1
990; RV32I-NEXT:    ret
991;
992; RV64I-LABEL: abd_minmax_i16:
993; RV64I:       # %bb.0:
994; RV64I-NEXT:    lui a2, 16
995; RV64I-NEXT:    addiw a2, a2, -1
996; RV64I-NEXT:    and a1, a1, a2
997; RV64I-NEXT:    and a0, a0, a2
998; RV64I-NEXT:    sub a0, a0, a1
999; RV64I-NEXT:    srai a1, a0, 63
1000; RV64I-NEXT:    xor a0, a0, a1
1001; RV64I-NEXT:    sub a0, a0, a1
1002; RV64I-NEXT:    ret
1003;
1004; ZBB-LABEL: abd_minmax_i16:
1005; ZBB:       # %bb.0:
1006; ZBB-NEXT:    zext.h a1, a1
1007; ZBB-NEXT:    zext.h a0, a0
1008; ZBB-NEXT:    minu a2, a0, a1
1009; ZBB-NEXT:    maxu a0, a0, a1
1010; ZBB-NEXT:    sub a0, a0, a2
1011; ZBB-NEXT:    ret
1012  %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
1013  %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
1014  %sub = sub i16 %max, %min
1015  ret i16 %sub
1016}
1017
1018define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
1019; RV32I-LABEL: abd_minmax_i32:
1020; RV32I:       # %bb.0:
1021; RV32I-NEXT:    bltu a1, a0, .LBB15_2
1022; RV32I-NEXT:  # %bb.1:
1023; RV32I-NEXT:    sub a0, a1, a0
1024; RV32I-NEXT:    ret
1025; RV32I-NEXT:  .LBB15_2:
1026; RV32I-NEXT:    sub a0, a0, a1
1027; RV32I-NEXT:    ret
1028;
1029; RV64I-LABEL: abd_minmax_i32:
1030; RV64I:       # %bb.0:
1031; RV64I-NEXT:    slli a1, a1, 32
1032; RV64I-NEXT:    slli a0, a0, 32
1033; RV64I-NEXT:    srli a1, a1, 32
1034; RV64I-NEXT:    srli a0, a0, 32
1035; RV64I-NEXT:    sub a0, a0, a1
1036; RV64I-NEXT:    srai a1, a0, 63
1037; RV64I-NEXT:    xor a0, a0, a1
1038; RV64I-NEXT:    sub a0, a0, a1
1039; RV64I-NEXT:    ret
1040;
1041; RV32ZBB-LABEL: abd_minmax_i32:
1042; RV32ZBB:       # %bb.0:
1043; RV32ZBB-NEXT:    minu a2, a0, a1
1044; RV32ZBB-NEXT:    maxu a0, a0, a1
1045; RV32ZBB-NEXT:    sub a0, a0, a2
1046; RV32ZBB-NEXT:    ret
1047;
1048; RV64ZBB-LABEL: abd_minmax_i32:
1049; RV64ZBB:       # %bb.0:
1050; RV64ZBB-NEXT:    slli a1, a1, 32
1051; RV64ZBB-NEXT:    slli a0, a0, 32
1052; RV64ZBB-NEXT:    srli a1, a1, 32
1053; RV64ZBB-NEXT:    srli a0, a0, 32
1054; RV64ZBB-NEXT:    minu a2, a0, a1
1055; RV64ZBB-NEXT:    maxu a0, a0, a1
1056; RV64ZBB-NEXT:    sub a0, a0, a2
1057; RV64ZBB-NEXT:    ret
1058  %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
1059  %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
1060  %sub = sub i32 %max, %min
1061  ret i32 %sub
1062}
1063
1064define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
1065; RV32I-LABEL: abd_minmax_i64:
1066; RV32I:       # %bb.0:
1067; RV32I-NEXT:    sltu a4, a0, a2
1068; RV32I-NEXT:    sub a3, a1, a3
1069; RV32I-NEXT:    sub a3, a3, a4
1070; RV32I-NEXT:    sub a2, a0, a2
1071; RV32I-NEXT:    beq a3, a1, .LBB16_2
1072; RV32I-NEXT:  # %bb.1:
1073; RV32I-NEXT:    sltu a0, a1, a3
1074; RV32I-NEXT:    j .LBB16_3
1075; RV32I-NEXT:  .LBB16_2:
1076; RV32I-NEXT:    sltu a0, a0, a2
1077; RV32I-NEXT:  .LBB16_3:
1078; RV32I-NEXT:    neg a1, a0
1079; RV32I-NEXT:    xor a2, a2, a1
1080; RV32I-NEXT:    xor a3, a3, a1
1081; RV32I-NEXT:    sltu a1, a2, a1
1082; RV32I-NEXT:    add a3, a3, a0
1083; RV32I-NEXT:    sub a1, a3, a1
1084; RV32I-NEXT:    add a0, a2, a0
1085; RV32I-NEXT:    ret
1086;
1087; RV64I-LABEL: abd_minmax_i64:
1088; RV64I:       # %bb.0:
1089; RV64I-NEXT:    bltu a1, a0, .LBB16_2
1090; RV64I-NEXT:  # %bb.1:
1091; RV64I-NEXT:    sub a0, a1, a0
1092; RV64I-NEXT:    ret
1093; RV64I-NEXT:  .LBB16_2:
1094; RV64I-NEXT:    sub a0, a0, a1
1095; RV64I-NEXT:    ret
1096;
1097; RV32ZBB-LABEL: abd_minmax_i64:
1098; RV32ZBB:       # %bb.0:
1099; RV32ZBB-NEXT:    sltu a4, a0, a2
1100; RV32ZBB-NEXT:    sub a3, a1, a3
1101; RV32ZBB-NEXT:    sub a3, a3, a4
1102; RV32ZBB-NEXT:    sub a2, a0, a2
1103; RV32ZBB-NEXT:    beq a3, a1, .LBB16_2
1104; RV32ZBB-NEXT:  # %bb.1:
1105; RV32ZBB-NEXT:    sltu a0, a1, a3
1106; RV32ZBB-NEXT:    j .LBB16_3
1107; RV32ZBB-NEXT:  .LBB16_2:
1108; RV32ZBB-NEXT:    sltu a0, a0, a2
1109; RV32ZBB-NEXT:  .LBB16_3:
1110; RV32ZBB-NEXT:    neg a1, a0
1111; RV32ZBB-NEXT:    xor a2, a2, a1
1112; RV32ZBB-NEXT:    xor a3, a3, a1
1113; RV32ZBB-NEXT:    sltu a1, a2, a1
1114; RV32ZBB-NEXT:    add a3, a3, a0
1115; RV32ZBB-NEXT:    sub a1, a3, a1
1116; RV32ZBB-NEXT:    add a0, a2, a0
1117; RV32ZBB-NEXT:    ret
1118;
1119; RV64ZBB-LABEL: abd_minmax_i64:
1120; RV64ZBB:       # %bb.0:
1121; RV64ZBB-NEXT:    minu a2, a0, a1
1122; RV64ZBB-NEXT:    maxu a0, a0, a1
1123; RV64ZBB-NEXT:    sub a0, a0, a2
1124; RV64ZBB-NEXT:    ret
1125  %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
1126  %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
1127  %sub = sub i64 %max, %min
1128  ret i64 %sub
1129}
1130
1131define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
1132; RV32I-LABEL: abd_minmax_i128:
1133; RV32I:       # %bb.0:
1134; RV32I-NEXT:    lw a3, 0(a2)
1135; RV32I-NEXT:    lw a5, 4(a2)
1136; RV32I-NEXT:    lw a6, 8(a2)
1137; RV32I-NEXT:    lw a7, 12(a2)
1138; RV32I-NEXT:    lw a2, 8(a1)
1139; RV32I-NEXT:    lw a4, 12(a1)
1140; RV32I-NEXT:    lw t0, 0(a1)
1141; RV32I-NEXT:    lw a1, 4(a1)
1142; RV32I-NEXT:    sltu t1, a2, a6
1143; RV32I-NEXT:    sub a7, a4, a7
1144; RV32I-NEXT:    sltu t2, t0, a3
1145; RV32I-NEXT:    sub a7, a7, t1
1146; RV32I-NEXT:    mv t1, t2
1147; RV32I-NEXT:    beq a1, a5, .LBB17_2
1148; RV32I-NEXT:  # %bb.1:
1149; RV32I-NEXT:    sltu t1, a1, a5
1150; RV32I-NEXT:  .LBB17_2:
1151; RV32I-NEXT:    sub t3, a2, a6
1152; RV32I-NEXT:    sltu a6, t3, t1
1153; RV32I-NEXT:    sub a6, a7, a6
1154; RV32I-NEXT:    sub a7, t3, t1
1155; RV32I-NEXT:    beq a6, a4, .LBB17_4
1156; RV32I-NEXT:  # %bb.3:
1157; RV32I-NEXT:    sltu t1, a4, a6
1158; RV32I-NEXT:    j .LBB17_5
1159; RV32I-NEXT:  .LBB17_4:
1160; RV32I-NEXT:    sltu t1, a2, a7
1161; RV32I-NEXT:  .LBB17_5:
1162; RV32I-NEXT:    sub a5, a1, a5
1163; RV32I-NEXT:    sub a5, a5, t2
1164; RV32I-NEXT:    sub a3, t0, a3
1165; RV32I-NEXT:    beq a5, a1, .LBB17_7
1166; RV32I-NEXT:  # %bb.6:
1167; RV32I-NEXT:    sltu a1, a1, a5
1168; RV32I-NEXT:    j .LBB17_8
1169; RV32I-NEXT:  .LBB17_7:
1170; RV32I-NEXT:    sltu a1, t0, a3
1171; RV32I-NEXT:  .LBB17_8:
1172; RV32I-NEXT:    xor a4, a6, a4
1173; RV32I-NEXT:    xor a2, a7, a2
1174; RV32I-NEXT:    or a2, a2, a4
1175; RV32I-NEXT:    beqz a2, .LBB17_10
1176; RV32I-NEXT:  # %bb.9:
1177; RV32I-NEXT:    mv a1, t1
1178; RV32I-NEXT:  .LBB17_10:
1179; RV32I-NEXT:    neg t0, a1
1180; RV32I-NEXT:    xor a2, a7, t0
1181; RV32I-NEXT:    xor a6, a6, t0
1182; RV32I-NEXT:    xor a4, a3, t0
1183; RV32I-NEXT:    sltu a3, a2, t0
1184; RV32I-NEXT:    add a7, a6, a1
1185; RV32I-NEXT:    sltu a6, a4, t0
1186; RV32I-NEXT:    sub a3, a7, a3
1187; RV32I-NEXT:    xor t1, a5, t0
1188; RV32I-NEXT:    mv a7, a6
1189; RV32I-NEXT:    beqz a5, .LBB17_12
1190; RV32I-NEXT:  # %bb.11:
1191; RV32I-NEXT:    sltu a7, t1, t0
1192; RV32I-NEXT:  .LBB17_12:
1193; RV32I-NEXT:    add a2, a2, a1
1194; RV32I-NEXT:    add t1, t1, a1
1195; RV32I-NEXT:    add a1, a4, a1
1196; RV32I-NEXT:    sltu a4, a2, a7
1197; RV32I-NEXT:    sub a2, a2, a7
1198; RV32I-NEXT:    sub a5, t1, a6
1199; RV32I-NEXT:    sub a3, a3, a4
1200; RV32I-NEXT:    sw a1, 0(a0)
1201; RV32I-NEXT:    sw a5, 4(a0)
1202; RV32I-NEXT:    sw a2, 8(a0)
1203; RV32I-NEXT:    sw a3, 12(a0)
1204; RV32I-NEXT:    ret
1205;
1206; RV64I-LABEL: abd_minmax_i128:
1207; RV64I:       # %bb.0:
1208; RV64I-NEXT:    sltu a4, a0, a2
1209; RV64I-NEXT:    sub a3, a1, a3
1210; RV64I-NEXT:    sub a3, a3, a4
1211; RV64I-NEXT:    sub a2, a0, a2
1212; RV64I-NEXT:    beq a3, a1, .LBB17_2
1213; RV64I-NEXT:  # %bb.1:
1214; RV64I-NEXT:    sltu a0, a1, a3
1215; RV64I-NEXT:    j .LBB17_3
1216; RV64I-NEXT:  .LBB17_2:
1217; RV64I-NEXT:    sltu a0, a0, a2
1218; RV64I-NEXT:  .LBB17_3:
1219; RV64I-NEXT:    neg a1, a0
1220; RV64I-NEXT:    xor a2, a2, a1
1221; RV64I-NEXT:    xor a3, a3, a1
1222; RV64I-NEXT:    sltu a1, a2, a1
1223; RV64I-NEXT:    add a3, a3, a0
1224; RV64I-NEXT:    sub a1, a3, a1
1225; RV64I-NEXT:    add a0, a2, a0
1226; RV64I-NEXT:    ret
1227;
1228; RV32ZBB-LABEL: abd_minmax_i128:
1229; RV32ZBB:       # %bb.0:
1230; RV32ZBB-NEXT:    lw a3, 0(a2)
1231; RV32ZBB-NEXT:    lw a5, 4(a2)
1232; RV32ZBB-NEXT:    lw a6, 8(a2)
1233; RV32ZBB-NEXT:    lw a7, 12(a2)
1234; RV32ZBB-NEXT:    lw a2, 8(a1)
1235; RV32ZBB-NEXT:    lw a4, 12(a1)
1236; RV32ZBB-NEXT:    lw t0, 0(a1)
1237; RV32ZBB-NEXT:    lw a1, 4(a1)
1238; RV32ZBB-NEXT:    sltu t1, a2, a6
1239; RV32ZBB-NEXT:    sub a7, a4, a7
1240; RV32ZBB-NEXT:    sltu t2, t0, a3
1241; RV32ZBB-NEXT:    sub a7, a7, t1
1242; RV32ZBB-NEXT:    mv t1, t2
1243; RV32ZBB-NEXT:    beq a1, a5, .LBB17_2
1244; RV32ZBB-NEXT:  # %bb.1:
1245; RV32ZBB-NEXT:    sltu t1, a1, a5
1246; RV32ZBB-NEXT:  .LBB17_2:
1247; RV32ZBB-NEXT:    sub t3, a2, a6
1248; RV32ZBB-NEXT:    sltu a6, t3, t1
1249; RV32ZBB-NEXT:    sub a6, a7, a6
1250; RV32ZBB-NEXT:    sub a7, t3, t1
1251; RV32ZBB-NEXT:    beq a6, a4, .LBB17_4
1252; RV32ZBB-NEXT:  # %bb.3:
1253; RV32ZBB-NEXT:    sltu t1, a4, a6
1254; RV32ZBB-NEXT:    j .LBB17_5
1255; RV32ZBB-NEXT:  .LBB17_4:
1256; RV32ZBB-NEXT:    sltu t1, a2, a7
1257; RV32ZBB-NEXT:  .LBB17_5:
1258; RV32ZBB-NEXT:    sub a5, a1, a5
1259; RV32ZBB-NEXT:    sub a5, a5, t2
1260; RV32ZBB-NEXT:    sub a3, t0, a3
1261; RV32ZBB-NEXT:    beq a5, a1, .LBB17_7
1262; RV32ZBB-NEXT:  # %bb.6:
1263; RV32ZBB-NEXT:    sltu a1, a1, a5
1264; RV32ZBB-NEXT:    j .LBB17_8
1265; RV32ZBB-NEXT:  .LBB17_7:
1266; RV32ZBB-NEXT:    sltu a1, t0, a3
1267; RV32ZBB-NEXT:  .LBB17_8:
1268; RV32ZBB-NEXT:    xor a4, a6, a4
1269; RV32ZBB-NEXT:    xor a2, a7, a2
1270; RV32ZBB-NEXT:    or a2, a2, a4
1271; RV32ZBB-NEXT:    beqz a2, .LBB17_10
1272; RV32ZBB-NEXT:  # %bb.9:
1273; RV32ZBB-NEXT:    mv a1, t1
1274; RV32ZBB-NEXT:  .LBB17_10:
1275; RV32ZBB-NEXT:    neg t0, a1
1276; RV32ZBB-NEXT:    xor a2, a7, t0
1277; RV32ZBB-NEXT:    xor a6, a6, t0
1278; RV32ZBB-NEXT:    xor a4, a3, t0
1279; RV32ZBB-NEXT:    sltu a3, a2, t0
1280; RV32ZBB-NEXT:    add a7, a6, a1
1281; RV32ZBB-NEXT:    sltu a6, a4, t0
1282; RV32ZBB-NEXT:    sub a3, a7, a3
1283; RV32ZBB-NEXT:    xor t1, a5, t0
1284; RV32ZBB-NEXT:    mv a7, a6
1285; RV32ZBB-NEXT:    beqz a5, .LBB17_12
1286; RV32ZBB-NEXT:  # %bb.11:
1287; RV32ZBB-NEXT:    sltu a7, t1, t0
1288; RV32ZBB-NEXT:  .LBB17_12:
1289; RV32ZBB-NEXT:    add a2, a2, a1
1290; RV32ZBB-NEXT:    add t1, t1, a1
1291; RV32ZBB-NEXT:    add a1, a4, a1
1292; RV32ZBB-NEXT:    sltu a4, a2, a7
1293; RV32ZBB-NEXT:    sub a2, a2, a7
1294; RV32ZBB-NEXT:    sub a5, t1, a6
1295; RV32ZBB-NEXT:    sub a3, a3, a4
1296; RV32ZBB-NEXT:    sw a1, 0(a0)
1297; RV32ZBB-NEXT:    sw a5, 4(a0)
1298; RV32ZBB-NEXT:    sw a2, 8(a0)
1299; RV32ZBB-NEXT:    sw a3, 12(a0)
1300; RV32ZBB-NEXT:    ret
1301;
1302; RV64ZBB-LABEL: abd_minmax_i128:
1303; RV64ZBB:       # %bb.0:
1304; RV64ZBB-NEXT:    sltu a4, a0, a2
1305; RV64ZBB-NEXT:    sub a3, a1, a3
1306; RV64ZBB-NEXT:    sub a3, a3, a4
1307; RV64ZBB-NEXT:    sub a2, a0, a2
1308; RV64ZBB-NEXT:    beq a3, a1, .LBB17_2
1309; RV64ZBB-NEXT:  # %bb.1:
1310; RV64ZBB-NEXT:    sltu a0, a1, a3
1311; RV64ZBB-NEXT:    j .LBB17_3
1312; RV64ZBB-NEXT:  .LBB17_2:
1313; RV64ZBB-NEXT:    sltu a0, a0, a2
1314; RV64ZBB-NEXT:  .LBB17_3:
1315; RV64ZBB-NEXT:    neg a1, a0
1316; RV64ZBB-NEXT:    xor a2, a2, a1
1317; RV64ZBB-NEXT:    xor a3, a3, a1
1318; RV64ZBB-NEXT:    sltu a1, a2, a1
1319; RV64ZBB-NEXT:    add a3, a3, a0
1320; RV64ZBB-NEXT:    sub a1, a3, a1
1321; RV64ZBB-NEXT:    add a0, a2, a0
1322; RV64ZBB-NEXT:    ret
1323  %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
1324  %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
1325  %sub = sub i128 %max, %min
1326  ret i128 %sub
1327}
1328
1329;
1330; select(icmp(a,b),sub(a,b),sub(b,a)) -> abdu(a,b)
1331;
1332
1333define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
1334; RV32I-LABEL: abd_cmp_i8:
1335; RV32I:       # %bb.0:
1336; RV32I-NEXT:    andi a1, a1, 255
1337; RV32I-NEXT:    andi a0, a0, 255
1338; RV32I-NEXT:    sub a0, a0, a1
1339; RV32I-NEXT:    srai a1, a0, 31
1340; RV32I-NEXT:    xor a0, a0, a1
1341; RV32I-NEXT:    sub a0, a0, a1
1342; RV32I-NEXT:    ret
1343;
1344; RV64I-LABEL: abd_cmp_i8:
1345; RV64I:       # %bb.0:
1346; RV64I-NEXT:    andi a1, a1, 255
1347; RV64I-NEXT:    andi a0, a0, 255
1348; RV64I-NEXT:    sub a0, a0, a1
1349; RV64I-NEXT:    srai a1, a0, 63
1350; RV64I-NEXT:    xor a0, a0, a1
1351; RV64I-NEXT:    sub a0, a0, a1
1352; RV64I-NEXT:    ret
1353;
1354; ZBB-LABEL: abd_cmp_i8:
1355; ZBB:       # %bb.0:
1356; ZBB-NEXT:    andi a1, a1, 255
1357; ZBB-NEXT:    andi a0, a0, 255
1358; ZBB-NEXT:    minu a2, a0, a1
1359; ZBB-NEXT:    maxu a0, a0, a1
1360; ZBB-NEXT:    sub a0, a0, a2
1361; ZBB-NEXT:    ret
1362  %cmp = icmp ugt i8 %a, %b
1363  %ab = sub i8 %a, %b
1364  %ba = sub i8 %b, %a
1365  %sel = select i1 %cmp, i8 %ab, i8 %ba
1366  ret i8 %sel
1367}
1368
1369define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
1370; RV32I-LABEL: abd_cmp_i16:
1371; RV32I:       # %bb.0:
1372; RV32I-NEXT:    lui a2, 16
1373; RV32I-NEXT:    addi a2, a2, -1
1374; RV32I-NEXT:    and a1, a1, a2
1375; RV32I-NEXT:    and a0, a0, a2
1376; RV32I-NEXT:    sub a0, a0, a1
1377; RV32I-NEXT:    srai a1, a0, 31
1378; RV32I-NEXT:    xor a0, a0, a1
1379; RV32I-NEXT:    sub a0, a0, a1
1380; RV32I-NEXT:    ret
1381;
1382; RV64I-LABEL: abd_cmp_i16:
1383; RV64I:       # %bb.0:
1384; RV64I-NEXT:    lui a2, 16
1385; RV64I-NEXT:    addiw a2, a2, -1
1386; RV64I-NEXT:    and a1, a1, a2
1387; RV64I-NEXT:    and a0, a0, a2
1388; RV64I-NEXT:    sub a0, a0, a1
1389; RV64I-NEXT:    srai a1, a0, 63
1390; RV64I-NEXT:    xor a0, a0, a1
1391; RV64I-NEXT:    sub a0, a0, a1
1392; RV64I-NEXT:    ret
1393;
1394; ZBB-LABEL: abd_cmp_i16:
1395; ZBB:       # %bb.0:
1396; ZBB-NEXT:    zext.h a1, a1
1397; ZBB-NEXT:    zext.h a0, a0
1398; ZBB-NEXT:    minu a2, a0, a1
1399; ZBB-NEXT:    maxu a0, a0, a1
1400; ZBB-NEXT:    sub a0, a0, a2
1401; ZBB-NEXT:    ret
1402  %cmp = icmp uge i16 %a, %b
1403  %ab = sub i16 %a, %b
1404  %ba = sub i16 %b, %a
1405  %sel = select i1 %cmp, i16 %ab, i16 %ba
1406  ret i16 %sel
1407}
1408
1409define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
1410; RV32I-LABEL: abd_cmp_i32:
1411; RV32I:       # %bb.0:
1412; RV32I-NEXT:    bltu a1, a0, .LBB20_2
1413; RV32I-NEXT:  # %bb.1:
1414; RV32I-NEXT:    sub a0, a1, a0
1415; RV32I-NEXT:    ret
1416; RV32I-NEXT:  .LBB20_2:
1417; RV32I-NEXT:    sub a0, a0, a1
1418; RV32I-NEXT:    ret
1419;
1420; RV64I-LABEL: abd_cmp_i32:
1421; RV64I:       # %bb.0:
1422; RV64I-NEXT:    slli a1, a1, 32
1423; RV64I-NEXT:    slli a0, a0, 32
1424; RV64I-NEXT:    srli a1, a1, 32
1425; RV64I-NEXT:    srli a0, a0, 32
1426; RV64I-NEXT:    sub a0, a0, a1
1427; RV64I-NEXT:    srai a1, a0, 63
1428; RV64I-NEXT:    xor a0, a0, a1
1429; RV64I-NEXT:    sub a0, a0, a1
1430; RV64I-NEXT:    ret
1431;
1432; RV32ZBB-LABEL: abd_cmp_i32:
1433; RV32ZBB:       # %bb.0:
1434; RV32ZBB-NEXT:    minu a2, a0, a1
1435; RV32ZBB-NEXT:    maxu a0, a0, a1
1436; RV32ZBB-NEXT:    sub a0, a0, a2
1437; RV32ZBB-NEXT:    ret
1438;
1439; RV64ZBB-LABEL: abd_cmp_i32:
1440; RV64ZBB:       # %bb.0:
1441; RV64ZBB-NEXT:    slli a1, a1, 32
1442; RV64ZBB-NEXT:    slli a0, a0, 32
1443; RV64ZBB-NEXT:    srli a1, a1, 32
1444; RV64ZBB-NEXT:    srli a0, a0, 32
1445; RV64ZBB-NEXT:    minu a2, a0, a1
1446; RV64ZBB-NEXT:    maxu a0, a0, a1
1447; RV64ZBB-NEXT:    sub a0, a0, a2
1448; RV64ZBB-NEXT:    ret
1449  %cmp = icmp ult i32 %a, %b
1450  %ab = sub i32 %a, %b
1451  %ba = sub i32 %b, %a
1452  %sel = select i1 %cmp, i32 %ba, i32 %ab
1453  ret i32 %sel
1454}
1455
1456define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
1457; RV32I-LABEL: abd_cmp_i64:
1458; RV32I:       # %bb.0:
1459; RV32I-NEXT:    sltu a4, a0, a2
1460; RV32I-NEXT:    sub a3, a1, a3
1461; RV32I-NEXT:    sub a3, a3, a4
1462; RV32I-NEXT:    sub a2, a0, a2
1463; RV32I-NEXT:    beq a3, a1, .LBB21_2
1464; RV32I-NEXT:  # %bb.1:
1465; RV32I-NEXT:    sltu a0, a1, a3
1466; RV32I-NEXT:    j .LBB21_3
1467; RV32I-NEXT:  .LBB21_2:
1468; RV32I-NEXT:    sltu a0, a0, a2
1469; RV32I-NEXT:  .LBB21_3:
1470; RV32I-NEXT:    neg a1, a0
1471; RV32I-NEXT:    xor a2, a2, a1
1472; RV32I-NEXT:    xor a3, a3, a1
1473; RV32I-NEXT:    sltu a1, a2, a1
1474; RV32I-NEXT:    add a3, a3, a0
1475; RV32I-NEXT:    sub a1, a3, a1
1476; RV32I-NEXT:    add a0, a2, a0
1477; RV32I-NEXT:    ret
1478;
1479; RV64I-LABEL: abd_cmp_i64:
1480; RV64I:       # %bb.0:
1481; RV64I-NEXT:    bltu a1, a0, .LBB21_2
1482; RV64I-NEXT:  # %bb.1:
1483; RV64I-NEXT:    sub a0, a1, a0
1484; RV64I-NEXT:    ret
1485; RV64I-NEXT:  .LBB21_2:
1486; RV64I-NEXT:    sub a0, a0, a1
1487; RV64I-NEXT:    ret
1488;
1489; RV32ZBB-LABEL: abd_cmp_i64:
1490; RV32ZBB:       # %bb.0:
1491; RV32ZBB-NEXT:    sltu a4, a0, a2
1492; RV32ZBB-NEXT:    sub a3, a1, a3
1493; RV32ZBB-NEXT:    sub a3, a3, a4
1494; RV32ZBB-NEXT:    sub a2, a0, a2
1495; RV32ZBB-NEXT:    beq a3, a1, .LBB21_2
1496; RV32ZBB-NEXT:  # %bb.1:
1497; RV32ZBB-NEXT:    sltu a0, a1, a3
1498; RV32ZBB-NEXT:    j .LBB21_3
1499; RV32ZBB-NEXT:  .LBB21_2:
1500; RV32ZBB-NEXT:    sltu a0, a0, a2
1501; RV32ZBB-NEXT:  .LBB21_3:
1502; RV32ZBB-NEXT:    neg a1, a0
1503; RV32ZBB-NEXT:    xor a2, a2, a1
1504; RV32ZBB-NEXT:    xor a3, a3, a1
1505; RV32ZBB-NEXT:    sltu a1, a2, a1
1506; RV32ZBB-NEXT:    add a3, a3, a0
1507; RV32ZBB-NEXT:    sub a1, a3, a1
1508; RV32ZBB-NEXT:    add a0, a2, a0
1509; RV32ZBB-NEXT:    ret
1510;
1511; RV64ZBB-LABEL: abd_cmp_i64:
1512; RV64ZBB:       # %bb.0:
1513; RV64ZBB-NEXT:    minu a2, a0, a1
1514; RV64ZBB-NEXT:    maxu a0, a0, a1
1515; RV64ZBB-NEXT:    sub a0, a0, a2
1516; RV64ZBB-NEXT:    ret
1517  %cmp = icmp uge i64 %a, %b
1518  %ab = sub i64 %a, %b
1519  %ba = sub i64 %b, %a
1520  %sel = select i1 %cmp, i64 %ab, i64 %ba
1521  ret i64 %sel
1522}
1523
1524define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
1525; RV32I-LABEL: abd_cmp_i128:
1526; RV32I:       # %bb.0:
1527; RV32I-NEXT:    lw a3, 0(a2)
1528; RV32I-NEXT:    lw a5, 4(a2)
1529; RV32I-NEXT:    lw a6, 8(a2)
1530; RV32I-NEXT:    lw a7, 12(a2)
1531; RV32I-NEXT:    lw a2, 8(a1)
1532; RV32I-NEXT:    lw a4, 12(a1)
1533; RV32I-NEXT:    lw t0, 0(a1)
1534; RV32I-NEXT:    lw a1, 4(a1)
1535; RV32I-NEXT:    sltu t1, a2, a6
1536; RV32I-NEXT:    sub a7, a4, a7
1537; RV32I-NEXT:    sltu t2, t0, a3
1538; RV32I-NEXT:    sub a7, a7, t1
1539; RV32I-NEXT:    mv t1, t2
1540; RV32I-NEXT:    beq a1, a5, .LBB22_2
1541; RV32I-NEXT:  # %bb.1:
1542; RV32I-NEXT:    sltu t1, a1, a5
1543; RV32I-NEXT:  .LBB22_2:
1544; RV32I-NEXT:    sub t3, a2, a6
1545; RV32I-NEXT:    sltu a6, t3, t1
1546; RV32I-NEXT:    sub a6, a7, a6
1547; RV32I-NEXT:    sub a7, t3, t1
1548; RV32I-NEXT:    beq a6, a4, .LBB22_4
1549; RV32I-NEXT:  # %bb.3:
1550; RV32I-NEXT:    sltu t1, a4, a6
1551; RV32I-NEXT:    j .LBB22_5
1552; RV32I-NEXT:  .LBB22_4:
1553; RV32I-NEXT:    sltu t1, a2, a7
1554; RV32I-NEXT:  .LBB22_5:
1555; RV32I-NEXT:    sub a5, a1, a5
1556; RV32I-NEXT:    sub a5, a5, t2
1557; RV32I-NEXT:    sub a3, t0, a3
1558; RV32I-NEXT:    beq a5, a1, .LBB22_7
1559; RV32I-NEXT:  # %bb.6:
1560; RV32I-NEXT:    sltu a1, a1, a5
1561; RV32I-NEXT:    j .LBB22_8
1562; RV32I-NEXT:  .LBB22_7:
1563; RV32I-NEXT:    sltu a1, t0, a3
1564; RV32I-NEXT:  .LBB22_8:
1565; RV32I-NEXT:    xor a4, a6, a4
1566; RV32I-NEXT:    xor a2, a7, a2
1567; RV32I-NEXT:    or a2, a2, a4
1568; RV32I-NEXT:    beqz a2, .LBB22_10
1569; RV32I-NEXT:  # %bb.9:
1570; RV32I-NEXT:    mv a1, t1
1571; RV32I-NEXT:  .LBB22_10:
1572; RV32I-NEXT:    neg t0, a1
1573; RV32I-NEXT:    xor a2, a7, t0
1574; RV32I-NEXT:    xor a6, a6, t0
1575; RV32I-NEXT:    xor a4, a3, t0
1576; RV32I-NEXT:    sltu a3, a2, t0
1577; RV32I-NEXT:    add a7, a6, a1
1578; RV32I-NEXT:    sltu a6, a4, t0
1579; RV32I-NEXT:    sub a3, a7, a3
1580; RV32I-NEXT:    xor t1, a5, t0
1581; RV32I-NEXT:    mv a7, a6
1582; RV32I-NEXT:    beqz a5, .LBB22_12
1583; RV32I-NEXT:  # %bb.11:
1584; RV32I-NEXT:    sltu a7, t1, t0
1585; RV32I-NEXT:  .LBB22_12:
1586; RV32I-NEXT:    add a2, a2, a1
1587; RV32I-NEXT:    add t1, t1, a1
1588; RV32I-NEXT:    add a1, a4, a1
1589; RV32I-NEXT:    sltu a4, a2, a7
1590; RV32I-NEXT:    sub a2, a2, a7
1591; RV32I-NEXT:    sub a5, t1, a6
1592; RV32I-NEXT:    sub a3, a3, a4
1593; RV32I-NEXT:    sw a1, 0(a0)
1594; RV32I-NEXT:    sw a5, 4(a0)
1595; RV32I-NEXT:    sw a2, 8(a0)
1596; RV32I-NEXT:    sw a3, 12(a0)
1597; RV32I-NEXT:    ret
1598;
1599; RV64I-LABEL: abd_cmp_i128:
1600; RV64I:       # %bb.0:
1601; RV64I-NEXT:    sltu a4, a0, a2
1602; RV64I-NEXT:    sub a3, a1, a3
1603; RV64I-NEXT:    sub a3, a3, a4
1604; RV64I-NEXT:    sub a2, a0, a2
1605; RV64I-NEXT:    beq a3, a1, .LBB22_2
1606; RV64I-NEXT:  # %bb.1:
1607; RV64I-NEXT:    sltu a0, a1, a3
1608; RV64I-NEXT:    j .LBB22_3
1609; RV64I-NEXT:  .LBB22_2:
1610; RV64I-NEXT:    sltu a0, a0, a2
1611; RV64I-NEXT:  .LBB22_3:
1612; RV64I-NEXT:    neg a1, a0
1613; RV64I-NEXT:    xor a2, a2, a1
1614; RV64I-NEXT:    xor a3, a3, a1
1615; RV64I-NEXT:    sltu a1, a2, a1
1616; RV64I-NEXT:    add a3, a3, a0
1617; RV64I-NEXT:    sub a1, a3, a1
1618; RV64I-NEXT:    add a0, a2, a0
1619; RV64I-NEXT:    ret
1620;
1621; RV32ZBB-LABEL: abd_cmp_i128:
1622; RV32ZBB:       # %bb.0:
1623; RV32ZBB-NEXT:    lw a3, 0(a2)
1624; RV32ZBB-NEXT:    lw a5, 4(a2)
1625; RV32ZBB-NEXT:    lw a6, 8(a2)
1626; RV32ZBB-NEXT:    lw a7, 12(a2)
1627; RV32ZBB-NEXT:    lw a2, 8(a1)
1628; RV32ZBB-NEXT:    lw a4, 12(a1)
1629; RV32ZBB-NEXT:    lw t0, 0(a1)
1630; RV32ZBB-NEXT:    lw a1, 4(a1)
1631; RV32ZBB-NEXT:    sltu t1, a2, a6
1632; RV32ZBB-NEXT:    sub a7, a4, a7
1633; RV32ZBB-NEXT:    sltu t2, t0, a3
1634; RV32ZBB-NEXT:    sub a7, a7, t1
1635; RV32ZBB-NEXT:    mv t1, t2
1636; RV32ZBB-NEXT:    beq a1, a5, .LBB22_2
1637; RV32ZBB-NEXT:  # %bb.1:
1638; RV32ZBB-NEXT:    sltu t1, a1, a5
1639; RV32ZBB-NEXT:  .LBB22_2:
1640; RV32ZBB-NEXT:    sub t3, a2, a6
1641; RV32ZBB-NEXT:    sltu a6, t3, t1
1642; RV32ZBB-NEXT:    sub a6, a7, a6
1643; RV32ZBB-NEXT:    sub a7, t3, t1
1644; RV32ZBB-NEXT:    beq a6, a4, .LBB22_4
1645; RV32ZBB-NEXT:  # %bb.3:
1646; RV32ZBB-NEXT:    sltu t1, a4, a6
1647; RV32ZBB-NEXT:    j .LBB22_5
1648; RV32ZBB-NEXT:  .LBB22_4:
1649; RV32ZBB-NEXT:    sltu t1, a2, a7
1650; RV32ZBB-NEXT:  .LBB22_5:
1651; RV32ZBB-NEXT:    sub a5, a1, a5
1652; RV32ZBB-NEXT:    sub a5, a5, t2
1653; RV32ZBB-NEXT:    sub a3, t0, a3
1654; RV32ZBB-NEXT:    beq a5, a1, .LBB22_7
1655; RV32ZBB-NEXT:  # %bb.6:
1656; RV32ZBB-NEXT:    sltu a1, a1, a5
1657; RV32ZBB-NEXT:    j .LBB22_8
1658; RV32ZBB-NEXT:  .LBB22_7:
1659; RV32ZBB-NEXT:    sltu a1, t0, a3
1660; RV32ZBB-NEXT:  .LBB22_8:
1661; RV32ZBB-NEXT:    xor a4, a6, a4
1662; RV32ZBB-NEXT:    xor a2, a7, a2
1663; RV32ZBB-NEXT:    or a2, a2, a4
1664; RV32ZBB-NEXT:    beqz a2, .LBB22_10
1665; RV32ZBB-NEXT:  # %bb.9:
1666; RV32ZBB-NEXT:    mv a1, t1
1667; RV32ZBB-NEXT:  .LBB22_10:
1668; RV32ZBB-NEXT:    neg t0, a1
1669; RV32ZBB-NEXT:    xor a2, a7, t0
1670; RV32ZBB-NEXT:    xor a6, a6, t0
1671; RV32ZBB-NEXT:    xor a4, a3, t0
1672; RV32ZBB-NEXT:    sltu a3, a2, t0
1673; RV32ZBB-NEXT:    add a7, a6, a1
1674; RV32ZBB-NEXT:    sltu a6, a4, t0
1675; RV32ZBB-NEXT:    sub a3, a7, a3
1676; RV32ZBB-NEXT:    xor t1, a5, t0
1677; RV32ZBB-NEXT:    mv a7, a6
1678; RV32ZBB-NEXT:    beqz a5, .LBB22_12
1679; RV32ZBB-NEXT:  # %bb.11:
1680; RV32ZBB-NEXT:    sltu a7, t1, t0
1681; RV32ZBB-NEXT:  .LBB22_12:
1682; RV32ZBB-NEXT:    add a2, a2, a1
1683; RV32ZBB-NEXT:    add t1, t1, a1
1684; RV32ZBB-NEXT:    add a1, a4, a1
1685; RV32ZBB-NEXT:    sltu a4, a2, a7
1686; RV32ZBB-NEXT:    sub a2, a2, a7
1687; RV32ZBB-NEXT:    sub a5, t1, a6
1688; RV32ZBB-NEXT:    sub a3, a3, a4
1689; RV32ZBB-NEXT:    sw a1, 0(a0)
1690; RV32ZBB-NEXT:    sw a5, 4(a0)
1691; RV32ZBB-NEXT:    sw a2, 8(a0)
1692; RV32ZBB-NEXT:    sw a3, 12(a0)
1693; RV32ZBB-NEXT:    ret
1694;
1695; RV64ZBB-LABEL: abd_cmp_i128:
1696; RV64ZBB:       # %bb.0:
1697; RV64ZBB-NEXT:    sltu a4, a0, a2
1698; RV64ZBB-NEXT:    sub a3, a1, a3
1699; RV64ZBB-NEXT:    sub a3, a3, a4
1700; RV64ZBB-NEXT:    sub a2, a0, a2
1701; RV64ZBB-NEXT:    beq a3, a1, .LBB22_2
1702; RV64ZBB-NEXT:  # %bb.1:
1703; RV64ZBB-NEXT:    sltu a0, a1, a3
1704; RV64ZBB-NEXT:    j .LBB22_3
1705; RV64ZBB-NEXT:  .LBB22_2:
1706; RV64ZBB-NEXT:    sltu a0, a0, a2
1707; RV64ZBB-NEXT:  .LBB22_3:
1708; RV64ZBB-NEXT:    neg a1, a0
1709; RV64ZBB-NEXT:    xor a2, a2, a1
1710; RV64ZBB-NEXT:    xor a3, a3, a1
1711; RV64ZBB-NEXT:    sltu a1, a2, a1
1712; RV64ZBB-NEXT:    add a3, a3, a0
1713; RV64ZBB-NEXT:    sub a1, a3, a1
1714; RV64ZBB-NEXT:    add a0, a2, a0
1715; RV64ZBB-NEXT:    ret
1716  %cmp = icmp uge i128 %a, %b
1717  %ab = sub i128 %a, %b
1718  %ba = sub i128 %b, %a
1719  %sel = select i1 %cmp, i128 %ab, i128 %ba
1720  ret i128 %sel
1721}
1722
1723;
1724; sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abdu(a,b)
1725;
1726
1727define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
1728; RV32I-LABEL: abd_select_i8:
1729; RV32I:       # %bb.0:
1730; RV32I-NEXT:    andi a1, a1, 255
1731; RV32I-NEXT:    andi a0, a0, 255
1732; RV32I-NEXT:    sub a0, a0, a1
1733; RV32I-NEXT:    srai a1, a0, 31
1734; RV32I-NEXT:    xor a0, a0, a1
1735; RV32I-NEXT:    sub a0, a0, a1
1736; RV32I-NEXT:    ret
1737;
1738; RV64I-LABEL: abd_select_i8:
1739; RV64I:       # %bb.0:
1740; RV64I-NEXT:    andi a1, a1, 255
1741; RV64I-NEXT:    andi a0, a0, 255
1742; RV64I-NEXT:    sub a0, a0, a1
1743; RV64I-NEXT:    srai a1, a0, 63
1744; RV64I-NEXT:    xor a0, a0, a1
1745; RV64I-NEXT:    sub a0, a0, a1
1746; RV64I-NEXT:    ret
1747;
1748; ZBB-LABEL: abd_select_i8:
1749; ZBB:       # %bb.0:
1750; ZBB-NEXT:    andi a1, a1, 255
1751; ZBB-NEXT:    andi a0, a0, 255
1752; ZBB-NEXT:    minu a2, a0, a1
1753; ZBB-NEXT:    maxu a0, a0, a1
1754; ZBB-NEXT:    sub a0, a0, a2
1755; ZBB-NEXT:    ret
1756  %cmp = icmp ult i8 %a, %b
1757  %ab = select i1 %cmp, i8 %a, i8 %b
1758  %ba = select i1 %cmp, i8 %b, i8 %a
1759  %sub = sub i8 %ba, %ab
1760  ret i8 %sub
1761}
1762
1763define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
1764; RV32I-LABEL: abd_select_i16:
1765; RV32I:       # %bb.0:
1766; RV32I-NEXT:    lui a2, 16
1767; RV32I-NEXT:    addi a2, a2, -1
1768; RV32I-NEXT:    and a1, a1, a2
1769; RV32I-NEXT:    and a0, a0, a2
1770; RV32I-NEXT:    sub a0, a0, a1
1771; RV32I-NEXT:    srai a1, a0, 31
1772; RV32I-NEXT:    xor a0, a0, a1
1773; RV32I-NEXT:    sub a0, a0, a1
1774; RV32I-NEXT:    ret
1775;
1776; RV64I-LABEL: abd_select_i16:
1777; RV64I:       # %bb.0:
1778; RV64I-NEXT:    lui a2, 16
1779; RV64I-NEXT:    addiw a2, a2, -1
1780; RV64I-NEXT:    and a1, a1, a2
1781; RV64I-NEXT:    and a0, a0, a2
1782; RV64I-NEXT:    sub a0, a0, a1
1783; RV64I-NEXT:    srai a1, a0, 63
1784; RV64I-NEXT:    xor a0, a0, a1
1785; RV64I-NEXT:    sub a0, a0, a1
1786; RV64I-NEXT:    ret
1787;
1788; ZBB-LABEL: abd_select_i16:
1789; ZBB:       # %bb.0:
1790; ZBB-NEXT:    zext.h a1, a1
1791; ZBB-NEXT:    zext.h a0, a0
1792; ZBB-NEXT:    minu a2, a0, a1
1793; ZBB-NEXT:    maxu a0, a0, a1
1794; ZBB-NEXT:    sub a0, a0, a2
1795; ZBB-NEXT:    ret
1796  %cmp = icmp ule i16 %a, %b
1797  %ab = select i1 %cmp, i16 %a, i16 %b
1798  %ba = select i1 %cmp, i16 %b, i16 %a
1799  %sub = sub i16 %ba, %ab
1800  ret i16 %sub
1801}
1802
1803define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
1804; RV32I-LABEL: abd_select_i32:
1805; RV32I:       # %bb.0:
1806; RV32I-NEXT:    bltu a1, a0, .LBB25_2
1807; RV32I-NEXT:  # %bb.1:
1808; RV32I-NEXT:    sub a0, a1, a0
1809; RV32I-NEXT:    ret
1810; RV32I-NEXT:  .LBB25_2:
1811; RV32I-NEXT:    sub a0, a0, a1
1812; RV32I-NEXT:    ret
1813;
1814; RV64I-LABEL: abd_select_i32:
1815; RV64I:       # %bb.0:
1816; RV64I-NEXT:    slli a1, a1, 32
1817; RV64I-NEXT:    slli a0, a0, 32
1818; RV64I-NEXT:    srli a1, a1, 32
1819; RV64I-NEXT:    srli a0, a0, 32
1820; RV64I-NEXT:    sub a0, a0, a1
1821; RV64I-NEXT:    srai a1, a0, 63
1822; RV64I-NEXT:    xor a0, a0, a1
1823; RV64I-NEXT:    sub a0, a0, a1
1824; RV64I-NEXT:    ret
1825;
1826; RV32ZBB-LABEL: abd_select_i32:
1827; RV32ZBB:       # %bb.0:
1828; RV32ZBB-NEXT:    minu a2, a0, a1
1829; RV32ZBB-NEXT:    maxu a0, a0, a1
1830; RV32ZBB-NEXT:    sub a0, a0, a2
1831; RV32ZBB-NEXT:    ret
1832;
1833; RV64ZBB-LABEL: abd_select_i32:
1834; RV64ZBB:       # %bb.0:
1835; RV64ZBB-NEXT:    slli a1, a1, 32
1836; RV64ZBB-NEXT:    slli a0, a0, 32
1837; RV64ZBB-NEXT:    srli a1, a1, 32
1838; RV64ZBB-NEXT:    srli a0, a0, 32
1839; RV64ZBB-NEXT:    minu a2, a0, a1
1840; RV64ZBB-NEXT:    maxu a0, a0, a1
1841; RV64ZBB-NEXT:    sub a0, a0, a2
1842; RV64ZBB-NEXT:    ret
1843  %cmp = icmp ugt i32 %a, %b
1844  %ab = select i1 %cmp, i32 %a, i32 %b
1845  %ba = select i1 %cmp, i32 %b, i32 %a
1846  %sub = sub i32 %ab, %ba
1847  ret i32 %sub
1848}
1849
1850define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
1851; RV32I-LABEL: abd_select_i64:
1852; RV32I:       # %bb.0:
1853; RV32I-NEXT:    sltu a4, a0, a2
1854; RV32I-NEXT:    sub a3, a1, a3
1855; RV32I-NEXT:    sub a3, a3, a4
1856; RV32I-NEXT:    sub a2, a0, a2
1857; RV32I-NEXT:    beq a3, a1, .LBB26_2
1858; RV32I-NEXT:  # %bb.1:
1859; RV32I-NEXT:    sltu a0, a1, a3
1860; RV32I-NEXT:    j .LBB26_3
1861; RV32I-NEXT:  .LBB26_2:
1862; RV32I-NEXT:    sltu a0, a0, a2
1863; RV32I-NEXT:  .LBB26_3:
1864; RV32I-NEXT:    neg a1, a0
1865; RV32I-NEXT:    xor a2, a2, a1
1866; RV32I-NEXT:    xor a3, a3, a1
1867; RV32I-NEXT:    sltu a1, a2, a1
1868; RV32I-NEXT:    add a3, a3, a0
1869; RV32I-NEXT:    sub a1, a3, a1
1870; RV32I-NEXT:    add a0, a2, a0
1871; RV32I-NEXT:    ret
1872;
1873; RV64I-LABEL: abd_select_i64:
1874; RV64I:       # %bb.0:
1875; RV64I-NEXT:    bltu a1, a0, .LBB26_2
1876; RV64I-NEXT:  # %bb.1:
1877; RV64I-NEXT:    sub a0, a1, a0
1878; RV64I-NEXT:    ret
1879; RV64I-NEXT:  .LBB26_2:
1880; RV64I-NEXT:    sub a0, a0, a1
1881; RV64I-NEXT:    ret
1882;
1883; RV32ZBB-LABEL: abd_select_i64:
1884; RV32ZBB:       # %bb.0:
1885; RV32ZBB-NEXT:    sltu a4, a0, a2
1886; RV32ZBB-NEXT:    sub a3, a1, a3
1887; RV32ZBB-NEXT:    sub a3, a3, a4
1888; RV32ZBB-NEXT:    sub a2, a0, a2
1889; RV32ZBB-NEXT:    beq a3, a1, .LBB26_2
1890; RV32ZBB-NEXT:  # %bb.1:
1891; RV32ZBB-NEXT:    sltu a0, a1, a3
1892; RV32ZBB-NEXT:    j .LBB26_3
1893; RV32ZBB-NEXT:  .LBB26_2:
1894; RV32ZBB-NEXT:    sltu a0, a0, a2
1895; RV32ZBB-NEXT:  .LBB26_3:
1896; RV32ZBB-NEXT:    neg a1, a0
1897; RV32ZBB-NEXT:    xor a2, a2, a1
1898; RV32ZBB-NEXT:    xor a3, a3, a1
1899; RV32ZBB-NEXT:    sltu a1, a2, a1
1900; RV32ZBB-NEXT:    add a3, a3, a0
1901; RV32ZBB-NEXT:    sub a1, a3, a1
1902; RV32ZBB-NEXT:    add a0, a2, a0
1903; RV32ZBB-NEXT:    ret
1904;
1905; RV64ZBB-LABEL: abd_select_i64:
1906; RV64ZBB:       # %bb.0:
1907; RV64ZBB-NEXT:    minu a2, a0, a1
1908; RV64ZBB-NEXT:    maxu a0, a0, a1
1909; RV64ZBB-NEXT:    sub a0, a0, a2
1910; RV64ZBB-NEXT:    ret
1911  %cmp = icmp uge i64 %a, %b
1912  %ab = select i1 %cmp, i64 %a, i64 %b
1913  %ba = select i1 %cmp, i64 %b, i64 %a
1914  %sub = sub i64 %ab, %ba
1915  ret i64 %sub
1916}
1917
1918define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
1919; RV32I-LABEL: abd_select_i128:
1920; RV32I:       # %bb.0:
1921; RV32I-NEXT:    lw a3, 0(a2)
1922; RV32I-NEXT:    lw a5, 4(a2)
1923; RV32I-NEXT:    lw a6, 8(a2)
1924; RV32I-NEXT:    lw a7, 12(a2)
1925; RV32I-NEXT:    lw a2, 8(a1)
1926; RV32I-NEXT:    lw a4, 12(a1)
1927; RV32I-NEXT:    lw t0, 0(a1)
1928; RV32I-NEXT:    lw a1, 4(a1)
1929; RV32I-NEXT:    sltu t1, a2, a6
1930; RV32I-NEXT:    sub a7, a4, a7
1931; RV32I-NEXT:    sltu t2, t0, a3
1932; RV32I-NEXT:    sub a7, a7, t1
1933; RV32I-NEXT:    mv t1, t2
1934; RV32I-NEXT:    beq a1, a5, .LBB27_2
1935; RV32I-NEXT:  # %bb.1:
1936; RV32I-NEXT:    sltu t1, a1, a5
1937; RV32I-NEXT:  .LBB27_2:
1938; RV32I-NEXT:    sub t3, a2, a6
1939; RV32I-NEXT:    sltu a6, t3, t1
1940; RV32I-NEXT:    sub a6, a7, a6
1941; RV32I-NEXT:    sub a7, t3, t1
1942; RV32I-NEXT:    beq a6, a4, .LBB27_4
1943; RV32I-NEXT:  # %bb.3:
1944; RV32I-NEXT:    sltu t1, a4, a6
1945; RV32I-NEXT:    j .LBB27_5
1946; RV32I-NEXT:  .LBB27_4:
1947; RV32I-NEXT:    sltu t1, a2, a7
1948; RV32I-NEXT:  .LBB27_5:
1949; RV32I-NEXT:    sub a5, a1, a5
1950; RV32I-NEXT:    sub a5, a5, t2
1951; RV32I-NEXT:    sub a3, t0, a3
1952; RV32I-NEXT:    beq a5, a1, .LBB27_7
1953; RV32I-NEXT:  # %bb.6:
1954; RV32I-NEXT:    sltu a1, a1, a5
1955; RV32I-NEXT:    j .LBB27_8
1956; RV32I-NEXT:  .LBB27_7:
1957; RV32I-NEXT:    sltu a1, t0, a3
1958; RV32I-NEXT:  .LBB27_8:
1959; RV32I-NEXT:    xor a4, a6, a4
1960; RV32I-NEXT:    xor a2, a7, a2
1961; RV32I-NEXT:    or a2, a2, a4
1962; RV32I-NEXT:    beqz a2, .LBB27_10
1963; RV32I-NEXT:  # %bb.9:
1964; RV32I-NEXT:    mv a1, t1
1965; RV32I-NEXT:  .LBB27_10:
1966; RV32I-NEXT:    neg t0, a1
1967; RV32I-NEXT:    xor a2, a7, t0
1968; RV32I-NEXT:    xor a6, a6, t0
1969; RV32I-NEXT:    xor a4, a3, t0
1970; RV32I-NEXT:    sltu a3, a2, t0
1971; RV32I-NEXT:    add a7, a6, a1
1972; RV32I-NEXT:    sltu a6, a4, t0
1973; RV32I-NEXT:    sub a3, a7, a3
1974; RV32I-NEXT:    xor t1, a5, t0
1975; RV32I-NEXT:    mv a7, a6
1976; RV32I-NEXT:    beqz a5, .LBB27_12
1977; RV32I-NEXT:  # %bb.11:
1978; RV32I-NEXT:    sltu a7, t1, t0
1979; RV32I-NEXT:  .LBB27_12:
1980; RV32I-NEXT:    add a2, a2, a1
1981; RV32I-NEXT:    add t1, t1, a1
1982; RV32I-NEXT:    add a1, a4, a1
1983; RV32I-NEXT:    sltu a4, a2, a7
1984; RV32I-NEXT:    sub a2, a2, a7
1985; RV32I-NEXT:    sub a5, t1, a6
1986; RV32I-NEXT:    sub a3, a3, a4
1987; RV32I-NEXT:    sw a1, 0(a0)
1988; RV32I-NEXT:    sw a5, 4(a0)
1989; RV32I-NEXT:    sw a2, 8(a0)
1990; RV32I-NEXT:    sw a3, 12(a0)
1991; RV32I-NEXT:    ret
1992;
1993; RV64I-LABEL: abd_select_i128:
1994; RV64I:       # %bb.0:
1995; RV64I-NEXT:    sltu a4, a0, a2
1996; RV64I-NEXT:    sub a3, a1, a3
1997; RV64I-NEXT:    sub a3, a3, a4
1998; RV64I-NEXT:    sub a2, a0, a2
1999; RV64I-NEXT:    beq a3, a1, .LBB27_2
2000; RV64I-NEXT:  # %bb.1:
2001; RV64I-NEXT:    sltu a0, a1, a3
2002; RV64I-NEXT:    j .LBB27_3
2003; RV64I-NEXT:  .LBB27_2:
2004; RV64I-NEXT:    sltu a0, a0, a2
2005; RV64I-NEXT:  .LBB27_3:
2006; RV64I-NEXT:    neg a1, a0
2007; RV64I-NEXT:    xor a2, a2, a1
2008; RV64I-NEXT:    xor a3, a3, a1
2009; RV64I-NEXT:    sltu a1, a2, a1
2010; RV64I-NEXT:    add a3, a3, a0
2011; RV64I-NEXT:    sub a1, a3, a1
2012; RV64I-NEXT:    add a0, a2, a0
2013; RV64I-NEXT:    ret
2014;
2015; RV32ZBB-LABEL: abd_select_i128:
2016; RV32ZBB:       # %bb.0:
2017; RV32ZBB-NEXT:    lw a3, 0(a2)
2018; RV32ZBB-NEXT:    lw a5, 4(a2)
2019; RV32ZBB-NEXT:    lw a6, 8(a2)
2020; RV32ZBB-NEXT:    lw a7, 12(a2)
2021; RV32ZBB-NEXT:    lw a2, 8(a1)
2022; RV32ZBB-NEXT:    lw a4, 12(a1)
2023; RV32ZBB-NEXT:    lw t0, 0(a1)
2024; RV32ZBB-NEXT:    lw a1, 4(a1)
2025; RV32ZBB-NEXT:    sltu t1, a2, a6
2026; RV32ZBB-NEXT:    sub a7, a4, a7
2027; RV32ZBB-NEXT:    sltu t2, t0, a3
2028; RV32ZBB-NEXT:    sub a7, a7, t1
2029; RV32ZBB-NEXT:    mv t1, t2
2030; RV32ZBB-NEXT:    beq a1, a5, .LBB27_2
2031; RV32ZBB-NEXT:  # %bb.1:
2032; RV32ZBB-NEXT:    sltu t1, a1, a5
2033; RV32ZBB-NEXT:  .LBB27_2:
2034; RV32ZBB-NEXT:    sub t3, a2, a6
2035; RV32ZBB-NEXT:    sltu a6, t3, t1
2036; RV32ZBB-NEXT:    sub a6, a7, a6
2037; RV32ZBB-NEXT:    sub a7, t3, t1
2038; RV32ZBB-NEXT:    beq a6, a4, .LBB27_4
2039; RV32ZBB-NEXT:  # %bb.3:
2040; RV32ZBB-NEXT:    sltu t1, a4, a6
2041; RV32ZBB-NEXT:    j .LBB27_5
2042; RV32ZBB-NEXT:  .LBB27_4:
2043; RV32ZBB-NEXT:    sltu t1, a2, a7
2044; RV32ZBB-NEXT:  .LBB27_5:
2045; RV32ZBB-NEXT:    sub a5, a1, a5
2046; RV32ZBB-NEXT:    sub a5, a5, t2
2047; RV32ZBB-NEXT:    sub a3, t0, a3
2048; RV32ZBB-NEXT:    beq a5, a1, .LBB27_7
2049; RV32ZBB-NEXT:  # %bb.6:
2050; RV32ZBB-NEXT:    sltu a1, a1, a5
2051; RV32ZBB-NEXT:    j .LBB27_8
2052; RV32ZBB-NEXT:  .LBB27_7:
2053; RV32ZBB-NEXT:    sltu a1, t0, a3
2054; RV32ZBB-NEXT:  .LBB27_8:
2055; RV32ZBB-NEXT:    xor a4, a6, a4
2056; RV32ZBB-NEXT:    xor a2, a7, a2
2057; RV32ZBB-NEXT:    or a2, a2, a4
2058; RV32ZBB-NEXT:    beqz a2, .LBB27_10
2059; RV32ZBB-NEXT:  # %bb.9:
2060; RV32ZBB-NEXT:    mv a1, t1
2061; RV32ZBB-NEXT:  .LBB27_10:
2062; RV32ZBB-NEXT:    neg t0, a1
2063; RV32ZBB-NEXT:    xor a2, a7, t0
2064; RV32ZBB-NEXT:    xor a6, a6, t0
2065; RV32ZBB-NEXT:    xor a4, a3, t0
2066; RV32ZBB-NEXT:    sltu a3, a2, t0
2067; RV32ZBB-NEXT:    add a7, a6, a1
2068; RV32ZBB-NEXT:    sltu a6, a4, t0
2069; RV32ZBB-NEXT:    sub a3, a7, a3
2070; RV32ZBB-NEXT:    xor t1, a5, t0
2071; RV32ZBB-NEXT:    mv a7, a6
2072; RV32ZBB-NEXT:    beqz a5, .LBB27_12
2073; RV32ZBB-NEXT:  # %bb.11:
2074; RV32ZBB-NEXT:    sltu a7, t1, t0
2075; RV32ZBB-NEXT:  .LBB27_12:
2076; RV32ZBB-NEXT:    add a2, a2, a1
2077; RV32ZBB-NEXT:    add t1, t1, a1
2078; RV32ZBB-NEXT:    add a1, a4, a1
2079; RV32ZBB-NEXT:    sltu a4, a2, a7
2080; RV32ZBB-NEXT:    sub a2, a2, a7
2081; RV32ZBB-NEXT:    sub a5, t1, a6
2082; RV32ZBB-NEXT:    sub a3, a3, a4
2083; RV32ZBB-NEXT:    sw a1, 0(a0)
2084; RV32ZBB-NEXT:    sw a5, 4(a0)
2085; RV32ZBB-NEXT:    sw a2, 8(a0)
2086; RV32ZBB-NEXT:    sw a3, 12(a0)
2087; RV32ZBB-NEXT:    ret
2088;
2089; RV64ZBB-LABEL: abd_select_i128:
2090; RV64ZBB:       # %bb.0:
2091; RV64ZBB-NEXT:    sltu a4, a0, a2
2092; RV64ZBB-NEXT:    sub a3, a1, a3
2093; RV64ZBB-NEXT:    sub a3, a3, a4
2094; RV64ZBB-NEXT:    sub a2, a0, a2
2095; RV64ZBB-NEXT:    beq a3, a1, .LBB27_2
2096; RV64ZBB-NEXT:  # %bb.1:
2097; RV64ZBB-NEXT:    sltu a0, a1, a3
2098; RV64ZBB-NEXT:    j .LBB27_3
2099; RV64ZBB-NEXT:  .LBB27_2:
2100; RV64ZBB-NEXT:    sltu a0, a0, a2
2101; RV64ZBB-NEXT:  .LBB27_3:
2102; RV64ZBB-NEXT:    neg a1, a0
2103; RV64ZBB-NEXT:    xor a2, a2, a1
2104; RV64ZBB-NEXT:    xor a3, a3, a1
2105; RV64ZBB-NEXT:    sltu a1, a2, a1
2106; RV64ZBB-NEXT:    add a3, a3, a0
2107; RV64ZBB-NEXT:    sub a1, a3, a1
2108; RV64ZBB-NEXT:    add a0, a2, a0
2109; RV64ZBB-NEXT:    ret
2110  %cmp = icmp ult i128 %a, %b
2111  %ab = select i1 %cmp, i128 %a, i128 %b
2112  %ba = select i1 %cmp, i128 %b, i128 %a
2113  %sub = sub i128 %ba, %ab
2114  ret i128 %sub
2115}
2116
2117declare i8 @llvm.abs.i8(i8, i1)
2118declare i16 @llvm.abs.i16(i16, i1)
2119declare i32 @llvm.abs.i32(i32, i1)
2120declare i64 @llvm.abs.i64(i64, i1)
2121declare i128 @llvm.abs.i128(i128, i1)
2122
2123declare i8 @llvm.umax.i8(i8, i8)
2124declare i16 @llvm.umax.i16(i16, i16)
2125declare i32 @llvm.umax.i32(i32, i32)
2126declare i64 @llvm.umax.i64(i64, i64)
2127
2128declare i8 @llvm.umin.i8(i8, i8)
2129declare i16 @llvm.umin.i16(i16, i16)
2130declare i32 @llvm.umin.i32(i32, i32)
2131declare i64 @llvm.umin.i64(i64, i64)
2132;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
2133; CHECK: {{.*}}
2134; NOZBB: {{.*}}
2135