xref: /llvm-project/llvm/test/CodeGen/RISCV/abdu-neg.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=NOZBB,RV32I
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=NOZBB,RV64I
4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV32ZBB
5; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV64ZBB
6
7;
8; trunc(nabs(sub(zext(a),zext(b)))) -> nabds(a,b)
9;
10
11define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
12; RV32I-LABEL: abd_ext_i8:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    andi a1, a1, 255
15; RV32I-NEXT:    andi a0, a0, 255
16; RV32I-NEXT:    sub a0, a0, a1
17; RV32I-NEXT:    srai a1, a0, 31
18; RV32I-NEXT:    xor a0, a0, a1
19; RV32I-NEXT:    sub a0, a1, a0
20; RV32I-NEXT:    ret
21;
22; RV64I-LABEL: abd_ext_i8:
23; RV64I:       # %bb.0:
24; RV64I-NEXT:    andi a0, a0, 255
25; RV64I-NEXT:    andi a1, a1, 255
26; RV64I-NEXT:    sub a0, a0, a1
27; RV64I-NEXT:    srai a1, a0, 63
28; RV64I-NEXT:    xor a0, a0, a1
29; RV64I-NEXT:    sub a0, a1, a0
30; RV64I-NEXT:    ret
31;
32; RV32ZBB-LABEL: abd_ext_i8:
33; RV32ZBB:       # %bb.0:
34; RV32ZBB-NEXT:    andi a1, a1, 255
35; RV32ZBB-NEXT:    andi a0, a0, 255
36; RV32ZBB-NEXT:    maxu a2, a0, a1
37; RV32ZBB-NEXT:    minu a0, a0, a1
38; RV32ZBB-NEXT:    sub a0, a0, a2
39; RV32ZBB-NEXT:    ret
40;
41; RV64ZBB-LABEL: abd_ext_i8:
42; RV64ZBB:       # %bb.0:
43; RV64ZBB-NEXT:    andi a0, a0, 255
44; RV64ZBB-NEXT:    andi a1, a1, 255
45; RV64ZBB-NEXT:    sub a0, a0, a1
46; RV64ZBB-NEXT:    neg a1, a0
47; RV64ZBB-NEXT:    min a0, a0, a1
48; RV64ZBB-NEXT:    ret
49  %aext = zext i8 %a to i64
50  %bext = zext i8 %b to i64
51  %sub = sub i64 %aext, %bext
52  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
53  %nabs = sub i64 0, %abs
54  %trunc = trunc i64 %nabs to i8
55  ret i8 %trunc
56}
57
58define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
59; RV32I-LABEL: abd_ext_i8_i16:
60; RV32I:       # %bb.0:
61; RV32I-NEXT:    slli a1, a1, 16
62; RV32I-NEXT:    srli a1, a1, 16
63; RV32I-NEXT:    andi a0, a0, 255
64; RV32I-NEXT:    sub a0, a0, a1
65; RV32I-NEXT:    srai a1, a0, 31
66; RV32I-NEXT:    xor a0, a0, a1
67; RV32I-NEXT:    sub a0, a1, a0
68; RV32I-NEXT:    ret
69;
70; RV64I-LABEL: abd_ext_i8_i16:
71; RV64I:       # %bb.0:
72; RV64I-NEXT:    andi a0, a0, 255
73; RV64I-NEXT:    slli a1, a1, 48
74; RV64I-NEXT:    srli a1, a1, 48
75; RV64I-NEXT:    sub a0, a0, a1
76; RV64I-NEXT:    srai a1, a0, 63
77; RV64I-NEXT:    xor a0, a0, a1
78; RV64I-NEXT:    sub a0, a1, a0
79; RV64I-NEXT:    ret
80;
81; RV32ZBB-LABEL: abd_ext_i8_i16:
82; RV32ZBB:       # %bb.0:
83; RV32ZBB-NEXT:    zext.h a1, a1
84; RV32ZBB-NEXT:    andi a0, a0, 255
85; RV32ZBB-NEXT:    maxu a2, a0, a1
86; RV32ZBB-NEXT:    minu a0, a0, a1
87; RV32ZBB-NEXT:    sub a0, a0, a2
88; RV32ZBB-NEXT:    ret
89;
90; RV64ZBB-LABEL: abd_ext_i8_i16:
91; RV64ZBB:       # %bb.0:
92; RV64ZBB-NEXT:    andi a0, a0, 255
93; RV64ZBB-NEXT:    zext.h a1, a1
94; RV64ZBB-NEXT:    sub a0, a0, a1
95; RV64ZBB-NEXT:    neg a1, a0
96; RV64ZBB-NEXT:    min a0, a0, a1
97; RV64ZBB-NEXT:    ret
98  %aext = zext i8 %a to i64
99  %bext = zext i16 %b to i64
100  %sub = sub i64 %aext, %bext
101  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
102  %nabs = sub i64 0, %abs
103  %trunc = trunc i64 %nabs to i8
104  ret i8 %trunc
105}
106
107define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
108; RV32I-LABEL: abd_ext_i8_undef:
109; RV32I:       # %bb.0:
110; RV32I-NEXT:    andi a1, a1, 255
111; RV32I-NEXT:    andi a0, a0, 255
112; RV32I-NEXT:    sub a0, a0, a1
113; RV32I-NEXT:    srai a1, a0, 31
114; RV32I-NEXT:    xor a0, a0, a1
115; RV32I-NEXT:    sub a0, a1, a0
116; RV32I-NEXT:    ret
117;
118; RV64I-LABEL: abd_ext_i8_undef:
119; RV64I:       # %bb.0:
120; RV64I-NEXT:    andi a0, a0, 255
121; RV64I-NEXT:    andi a1, a1, 255
122; RV64I-NEXT:    sub a0, a0, a1
123; RV64I-NEXT:    srai a1, a0, 63
124; RV64I-NEXT:    xor a0, a0, a1
125; RV64I-NEXT:    sub a0, a1, a0
126; RV64I-NEXT:    ret
127;
128; RV32ZBB-LABEL: abd_ext_i8_undef:
129; RV32ZBB:       # %bb.0:
130; RV32ZBB-NEXT:    andi a1, a1, 255
131; RV32ZBB-NEXT:    andi a0, a0, 255
132; RV32ZBB-NEXT:    maxu a2, a0, a1
133; RV32ZBB-NEXT:    minu a0, a0, a1
134; RV32ZBB-NEXT:    sub a0, a0, a2
135; RV32ZBB-NEXT:    ret
136;
137; RV64ZBB-LABEL: abd_ext_i8_undef:
138; RV64ZBB:       # %bb.0:
139; RV64ZBB-NEXT:    andi a0, a0, 255
140; RV64ZBB-NEXT:    andi a1, a1, 255
141; RV64ZBB-NEXT:    sub a0, a0, a1
142; RV64ZBB-NEXT:    neg a1, a0
143; RV64ZBB-NEXT:    min a0, a0, a1
144; RV64ZBB-NEXT:    ret
145  %aext = zext i8 %a to i64
146  %bext = zext i8 %b to i64
147  %sub = sub i64 %aext, %bext
148  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
149  %nabs = sub i64 0, %abs
150  %trunc = trunc i64 %nabs to i8
151  ret i8 %trunc
152}
153
154define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
155; RV32I-LABEL: abd_ext_i16:
156; RV32I:       # %bb.0:
157; RV32I-NEXT:    lui a2, 16
158; RV32I-NEXT:    addi a2, a2, -1
159; RV32I-NEXT:    and a1, a1, a2
160; RV32I-NEXT:    and a0, a0, a2
161; RV32I-NEXT:    sub a0, a0, a1
162; RV32I-NEXT:    srai a1, a0, 31
163; RV32I-NEXT:    xor a0, a0, a1
164; RV32I-NEXT:    sub a0, a1, a0
165; RV32I-NEXT:    ret
166;
167; RV64I-LABEL: abd_ext_i16:
168; RV64I:       # %bb.0:
169; RV64I-NEXT:    lui a2, 16
170; RV64I-NEXT:    addiw a2, a2, -1
171; RV64I-NEXT:    and a0, a0, a2
172; RV64I-NEXT:    and a1, a1, a2
173; RV64I-NEXT:    sub a0, a0, a1
174; RV64I-NEXT:    srai a1, a0, 63
175; RV64I-NEXT:    xor a0, a0, a1
176; RV64I-NEXT:    sub a0, a1, a0
177; RV64I-NEXT:    ret
178;
179; RV32ZBB-LABEL: abd_ext_i16:
180; RV32ZBB:       # %bb.0:
181; RV32ZBB-NEXT:    zext.h a1, a1
182; RV32ZBB-NEXT:    zext.h a0, a0
183; RV32ZBB-NEXT:    maxu a2, a0, a1
184; RV32ZBB-NEXT:    minu a0, a0, a1
185; RV32ZBB-NEXT:    sub a0, a0, a2
186; RV32ZBB-NEXT:    ret
187;
188; RV64ZBB-LABEL: abd_ext_i16:
189; RV64ZBB:       # %bb.0:
190; RV64ZBB-NEXT:    zext.h a0, a0
191; RV64ZBB-NEXT:    zext.h a1, a1
192; RV64ZBB-NEXT:    sub a0, a0, a1
193; RV64ZBB-NEXT:    neg a1, a0
194; RV64ZBB-NEXT:    min a0, a0, a1
195; RV64ZBB-NEXT:    ret
196  %aext = zext i16 %a to i64
197  %bext = zext i16 %b to i64
198  %sub = sub i64 %aext, %bext
199  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
200  %nabs = sub i64 0, %abs
201  %trunc = trunc i64 %nabs to i16
202  ret i16 %trunc
203}
204
205define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
206; RV32I-LABEL: abd_ext_i16_i32:
207; RV32I:       # %bb.0:
208; RV32I-NEXT:    slli a0, a0, 16
209; RV32I-NEXT:    srli a0, a0, 16
210; RV32I-NEXT:    bltu a1, a0, .LBB4_2
211; RV32I-NEXT:  # %bb.1:
212; RV32I-NEXT:    sub a0, a1, a0
213; RV32I-NEXT:    neg a0, a0
214; RV32I-NEXT:    ret
215; RV32I-NEXT:  .LBB4_2:
216; RV32I-NEXT:    sub a0, a0, a1
217; RV32I-NEXT:    neg a0, a0
218; RV32I-NEXT:    ret
219;
220; RV64I-LABEL: abd_ext_i16_i32:
221; RV64I:       # %bb.0:
222; RV64I-NEXT:    slli a0, a0, 48
223; RV64I-NEXT:    slli a1, a1, 32
224; RV64I-NEXT:    srli a0, a0, 48
225; RV64I-NEXT:    srli a1, a1, 32
226; RV64I-NEXT:    sub a0, a0, a1
227; RV64I-NEXT:    srai a1, a0, 63
228; RV64I-NEXT:    xor a0, a0, a1
229; RV64I-NEXT:    sub a0, a1, a0
230; RV64I-NEXT:    ret
231;
232; RV32ZBB-LABEL: abd_ext_i16_i32:
233; RV32ZBB:       # %bb.0:
234; RV32ZBB-NEXT:    zext.h a0, a0
235; RV32ZBB-NEXT:    maxu a2, a0, a1
236; RV32ZBB-NEXT:    minu a0, a0, a1
237; RV32ZBB-NEXT:    sub a0, a0, a2
238; RV32ZBB-NEXT:    ret
239;
240; RV64ZBB-LABEL: abd_ext_i16_i32:
241; RV64ZBB:       # %bb.0:
242; RV64ZBB-NEXT:    zext.h a0, a0
243; RV64ZBB-NEXT:    slli a1, a1, 32
244; RV64ZBB-NEXT:    srli a1, a1, 32
245; RV64ZBB-NEXT:    sub a0, a0, a1
246; RV64ZBB-NEXT:    neg a1, a0
247; RV64ZBB-NEXT:    min a0, a0, a1
248; RV64ZBB-NEXT:    ret
249  %aext = zext i16 %a to i64
250  %bext = zext i32 %b to i64
251  %sub = sub i64 %aext, %bext
252  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
253  %nabs = sub i64 0, %abs
254  %trunc = trunc i64 %nabs to i16
255  ret i16 %trunc
256}
257
258define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
259; RV32I-LABEL: abd_ext_i16_undef:
260; RV32I:       # %bb.0:
261; RV32I-NEXT:    lui a2, 16
262; RV32I-NEXT:    addi a2, a2, -1
263; RV32I-NEXT:    and a1, a1, a2
264; RV32I-NEXT:    and a0, a0, a2
265; RV32I-NEXT:    sub a0, a0, a1
266; RV32I-NEXT:    srai a1, a0, 31
267; RV32I-NEXT:    xor a0, a0, a1
268; RV32I-NEXT:    sub a0, a1, a0
269; RV32I-NEXT:    ret
270;
271; RV64I-LABEL: abd_ext_i16_undef:
272; RV64I:       # %bb.0:
273; RV64I-NEXT:    lui a2, 16
274; RV64I-NEXT:    addiw a2, a2, -1
275; RV64I-NEXT:    and a0, a0, a2
276; RV64I-NEXT:    and a1, a1, a2
277; RV64I-NEXT:    sub a0, a0, a1
278; RV64I-NEXT:    srai a1, a0, 63
279; RV64I-NEXT:    xor a0, a0, a1
280; RV64I-NEXT:    sub a0, a1, a0
281; RV64I-NEXT:    ret
282;
283; RV32ZBB-LABEL: abd_ext_i16_undef:
284; RV32ZBB:       # %bb.0:
285; RV32ZBB-NEXT:    zext.h a1, a1
286; RV32ZBB-NEXT:    zext.h a0, a0
287; RV32ZBB-NEXT:    maxu a2, a0, a1
288; RV32ZBB-NEXT:    minu a0, a0, a1
289; RV32ZBB-NEXT:    sub a0, a0, a2
290; RV32ZBB-NEXT:    ret
291;
292; RV64ZBB-LABEL: abd_ext_i16_undef:
293; RV64ZBB:       # %bb.0:
294; RV64ZBB-NEXT:    zext.h a0, a0
295; RV64ZBB-NEXT:    zext.h a1, a1
296; RV64ZBB-NEXT:    sub a0, a0, a1
297; RV64ZBB-NEXT:    neg a1, a0
298; RV64ZBB-NEXT:    min a0, a0, a1
299; RV64ZBB-NEXT:    ret
300  %aext = zext i16 %a to i64
301  %bext = zext i16 %b to i64
302  %sub = sub i64 %aext, %bext
303  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
304  %nabs = sub i64 0, %abs
305  %trunc = trunc i64 %nabs to i16
306  ret i16 %trunc
307}
308
309define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
310; RV32I-LABEL: abd_ext_i32:
311; RV32I:       # %bb.0:
312; RV32I-NEXT:    bltu a1, a0, .LBB6_2
313; RV32I-NEXT:  # %bb.1:
314; RV32I-NEXT:    sub a0, a1, a0
315; RV32I-NEXT:    neg a0, a0
316; RV32I-NEXT:    ret
317; RV32I-NEXT:  .LBB6_2:
318; RV32I-NEXT:    sub a0, a0, a1
319; RV32I-NEXT:    neg a0, a0
320; RV32I-NEXT:    ret
321;
322; RV64I-LABEL: abd_ext_i32:
323; RV64I:       # %bb.0:
324; RV64I-NEXT:    slli a0, a0, 32
325; RV64I-NEXT:    slli a1, a1, 32
326; RV64I-NEXT:    srli a0, a0, 32
327; RV64I-NEXT:    srli a1, a1, 32
328; RV64I-NEXT:    sub a0, a0, a1
329; RV64I-NEXT:    srai a1, a0, 63
330; RV64I-NEXT:    xor a0, a0, a1
331; RV64I-NEXT:    sub a0, a1, a0
332; RV64I-NEXT:    ret
333;
334; RV32ZBB-LABEL: abd_ext_i32:
335; RV32ZBB:       # %bb.0:
336; RV32ZBB-NEXT:    maxu a2, a0, a1
337; RV32ZBB-NEXT:    minu a0, a0, a1
338; RV32ZBB-NEXT:    sub a0, a0, a2
339; RV32ZBB-NEXT:    ret
340;
341; RV64ZBB-LABEL: abd_ext_i32:
342; RV64ZBB:       # %bb.0:
343; RV64ZBB-NEXT:    slli a0, a0, 32
344; RV64ZBB-NEXT:    slli a1, a1, 32
345; RV64ZBB-NEXT:    srli a0, a0, 32
346; RV64ZBB-NEXT:    srli a1, a1, 32
347; RV64ZBB-NEXT:    sub a0, a0, a1
348; RV64ZBB-NEXT:    neg a1, a0
349; RV64ZBB-NEXT:    min a0, a0, a1
350; RV64ZBB-NEXT:    ret
351  %aext = zext i32 %a to i64
352  %bext = zext i32 %b to i64
353  %sub = sub i64 %aext, %bext
354  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
355  %nabs = sub i64 0, %abs
356  %trunc = trunc i64 %nabs to i32
357  ret i32 %trunc
358}
359
360define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
361; RV32I-LABEL: abd_ext_i32_i16:
362; RV32I:       # %bb.0:
363; RV32I-NEXT:    slli a1, a1, 16
364; RV32I-NEXT:    srli a1, a1, 16
365; RV32I-NEXT:    bltu a1, a0, .LBB7_2
366; RV32I-NEXT:  # %bb.1:
367; RV32I-NEXT:    sub a0, a1, a0
368; RV32I-NEXT:    neg a0, a0
369; RV32I-NEXT:    ret
370; RV32I-NEXT:  .LBB7_2:
371; RV32I-NEXT:    sub a0, a0, a1
372; RV32I-NEXT:    neg a0, a0
373; RV32I-NEXT:    ret
374;
375; RV64I-LABEL: abd_ext_i32_i16:
376; RV64I:       # %bb.0:
377; RV64I-NEXT:    slli a0, a0, 32
378; RV64I-NEXT:    slli a1, a1, 48
379; RV64I-NEXT:    srli a0, a0, 32
380; RV64I-NEXT:    srli a1, a1, 48
381; RV64I-NEXT:    sub a0, a0, a1
382; RV64I-NEXT:    srai a1, a0, 63
383; RV64I-NEXT:    xor a0, a0, a1
384; RV64I-NEXT:    sub a0, a1, a0
385; RV64I-NEXT:    ret
386;
387; RV32ZBB-LABEL: abd_ext_i32_i16:
388; RV32ZBB:       # %bb.0:
389; RV32ZBB-NEXT:    zext.h a1, a1
390; RV32ZBB-NEXT:    maxu a2, a0, a1
391; RV32ZBB-NEXT:    minu a0, a0, a1
392; RV32ZBB-NEXT:    sub a0, a0, a2
393; RV32ZBB-NEXT:    ret
394;
395; RV64ZBB-LABEL: abd_ext_i32_i16:
396; RV64ZBB:       # %bb.0:
397; RV64ZBB-NEXT:    slli a0, a0, 32
398; RV64ZBB-NEXT:    srli a0, a0, 32
399; RV64ZBB-NEXT:    zext.h a1, a1
400; RV64ZBB-NEXT:    sub a0, a0, a1
401; RV64ZBB-NEXT:    neg a1, a0
402; RV64ZBB-NEXT:    min a0, a0, a1
403; RV64ZBB-NEXT:    ret
404  %aext = zext i32 %a to i64
405  %bext = zext i16 %b to i64
406  %sub = sub i64 %aext, %bext
407  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
408  %nabs = sub i64 0, %abs
409  %trunc = trunc i64 %nabs to i32
410  ret i32 %trunc
411}
412
413define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
414; RV32I-LABEL: abd_ext_i32_undef:
415; RV32I:       # %bb.0:
416; RV32I-NEXT:    bltu a1, a0, .LBB8_2
417; RV32I-NEXT:  # %bb.1:
418; RV32I-NEXT:    sub a0, a1, a0
419; RV32I-NEXT:    neg a0, a0
420; RV32I-NEXT:    ret
421; RV32I-NEXT:  .LBB8_2:
422; RV32I-NEXT:    sub a0, a0, a1
423; RV32I-NEXT:    neg a0, a0
424; RV32I-NEXT:    ret
425;
426; RV64I-LABEL: abd_ext_i32_undef:
427; RV64I:       # %bb.0:
428; RV64I-NEXT:    slli a0, a0, 32
429; RV64I-NEXT:    slli a1, a1, 32
430; RV64I-NEXT:    srli a0, a0, 32
431; RV64I-NEXT:    srli a1, a1, 32
432; RV64I-NEXT:    sub a0, a0, a1
433; RV64I-NEXT:    srai a1, a0, 63
434; RV64I-NEXT:    xor a0, a0, a1
435; RV64I-NEXT:    sub a0, a1, a0
436; RV64I-NEXT:    ret
437;
438; RV32ZBB-LABEL: abd_ext_i32_undef:
439; RV32ZBB:       # %bb.0:
440; RV32ZBB-NEXT:    maxu a2, a0, a1
441; RV32ZBB-NEXT:    minu a0, a0, a1
442; RV32ZBB-NEXT:    sub a0, a0, a2
443; RV32ZBB-NEXT:    ret
444;
445; RV64ZBB-LABEL: abd_ext_i32_undef:
446; RV64ZBB:       # %bb.0:
447; RV64ZBB-NEXT:    slli a0, a0, 32
448; RV64ZBB-NEXT:    slli a1, a1, 32
449; RV64ZBB-NEXT:    srli a0, a0, 32
450; RV64ZBB-NEXT:    srli a1, a1, 32
451; RV64ZBB-NEXT:    sub a0, a0, a1
452; RV64ZBB-NEXT:    neg a1, a0
453; RV64ZBB-NEXT:    min a0, a0, a1
454; RV64ZBB-NEXT:    ret
455  %aext = zext i32 %a to i64
456  %bext = zext i32 %b to i64
457  %sub = sub i64 %aext, %bext
458  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
459  %nabs = sub i64 0, %abs
460  %trunc = trunc i64 %nabs to i32
461  ret i32 %trunc
462}
463
464define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
465; RV32I-LABEL: abd_ext_i64:
466; RV32I:       # %bb.0:
467; RV32I-NEXT:    sltu a4, a0, a2
468; RV32I-NEXT:    sub a3, a1, a3
469; RV32I-NEXT:    sub a3, a3, a4
470; RV32I-NEXT:    sub a2, a0, a2
471; RV32I-NEXT:    beq a3, a1, .LBB9_2
472; RV32I-NEXT:  # %bb.1:
473; RV32I-NEXT:    sltu a0, a1, a3
474; RV32I-NEXT:    j .LBB9_3
475; RV32I-NEXT:  .LBB9_2:
476; RV32I-NEXT:    sltu a0, a0, a2
477; RV32I-NEXT:  .LBB9_3:
478; RV32I-NEXT:    neg a1, a0
479; RV32I-NEXT:    xor a2, a2, a1
480; RV32I-NEXT:    xor a3, a3, a1
481; RV32I-NEXT:    sltu a1, a2, a1
482; RV32I-NEXT:    add a3, a3, a0
483; RV32I-NEXT:    add a0, a2, a0
484; RV32I-NEXT:    sub a3, a3, a1
485; RV32I-NEXT:    snez a1, a0
486; RV32I-NEXT:    add a1, a3, a1
487; RV32I-NEXT:    neg a1, a1
488; RV32I-NEXT:    neg a0, a0
489; RV32I-NEXT:    ret
490;
491; RV64I-LABEL: abd_ext_i64:
492; RV64I:       # %bb.0:
493; RV64I-NEXT:    bltu a1, a0, .LBB9_2
494; RV64I-NEXT:  # %bb.1:
495; RV64I-NEXT:    sub a0, a1, a0
496; RV64I-NEXT:    neg a0, a0
497; RV64I-NEXT:    ret
498; RV64I-NEXT:  .LBB9_2:
499; RV64I-NEXT:    sub a0, a0, a1
500; RV64I-NEXT:    neg a0, a0
501; RV64I-NEXT:    ret
502;
503; RV32ZBB-LABEL: abd_ext_i64:
504; RV32ZBB:       # %bb.0:
505; RV32ZBB-NEXT:    sltu a4, a0, a2
506; RV32ZBB-NEXT:    sub a3, a1, a3
507; RV32ZBB-NEXT:    sub a3, a3, a4
508; RV32ZBB-NEXT:    sub a2, a0, a2
509; RV32ZBB-NEXT:    beq a3, a1, .LBB9_2
510; RV32ZBB-NEXT:  # %bb.1:
511; RV32ZBB-NEXT:    sltu a0, a1, a3
512; RV32ZBB-NEXT:    j .LBB9_3
513; RV32ZBB-NEXT:  .LBB9_2:
514; RV32ZBB-NEXT:    sltu a0, a0, a2
515; RV32ZBB-NEXT:  .LBB9_3:
516; RV32ZBB-NEXT:    neg a1, a0
517; RV32ZBB-NEXT:    xor a2, a2, a1
518; RV32ZBB-NEXT:    xor a3, a3, a1
519; RV32ZBB-NEXT:    sltu a1, a2, a1
520; RV32ZBB-NEXT:    add a3, a3, a0
521; RV32ZBB-NEXT:    add a0, a2, a0
522; RV32ZBB-NEXT:    sub a3, a3, a1
523; RV32ZBB-NEXT:    snez a1, a0
524; RV32ZBB-NEXT:    add a1, a3, a1
525; RV32ZBB-NEXT:    neg a1, a1
526; RV32ZBB-NEXT:    neg a0, a0
527; RV32ZBB-NEXT:    ret
528;
529; RV64ZBB-LABEL: abd_ext_i64:
530; RV64ZBB:       # %bb.0:
531; RV64ZBB-NEXT:    maxu a2, a0, a1
532; RV64ZBB-NEXT:    minu a0, a0, a1
533; RV64ZBB-NEXT:    sub a0, a0, a2
534; RV64ZBB-NEXT:    ret
535  %aext = zext i64 %a to i128
536  %bext = zext i64 %b to i128
537  %sub = sub i128 %aext, %bext
538  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
539  %nabs = sub i128 0, %abs
540  %trunc = trunc i128 %nabs to i64
541  ret i64 %trunc
542}
543
544define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
545; RV32I-LABEL: abd_ext_i64_undef:
546; RV32I:       # %bb.0:
547; RV32I-NEXT:    sltu a4, a0, a2
548; RV32I-NEXT:    sub a3, a1, a3
549; RV32I-NEXT:    sub a3, a3, a4
550; RV32I-NEXT:    sub a2, a0, a2
551; RV32I-NEXT:    beq a3, a1, .LBB10_2
552; RV32I-NEXT:  # %bb.1:
553; RV32I-NEXT:    sltu a0, a1, a3
554; RV32I-NEXT:    j .LBB10_3
555; RV32I-NEXT:  .LBB10_2:
556; RV32I-NEXT:    sltu a0, a0, a2
557; RV32I-NEXT:  .LBB10_3:
558; RV32I-NEXT:    neg a1, a0
559; RV32I-NEXT:    xor a2, a2, a1
560; RV32I-NEXT:    xor a3, a3, a1
561; RV32I-NEXT:    sltu a1, a2, a1
562; RV32I-NEXT:    add a3, a3, a0
563; RV32I-NEXT:    add a0, a2, a0
564; RV32I-NEXT:    sub a3, a3, a1
565; RV32I-NEXT:    snez a1, a0
566; RV32I-NEXT:    add a1, a3, a1
567; RV32I-NEXT:    neg a1, a1
568; RV32I-NEXT:    neg a0, a0
569; RV32I-NEXT:    ret
570;
571; RV64I-LABEL: abd_ext_i64_undef:
572; RV64I:       # %bb.0:
573; RV64I-NEXT:    bltu a1, a0, .LBB10_2
574; RV64I-NEXT:  # %bb.1:
575; RV64I-NEXT:    sub a0, a1, a0
576; RV64I-NEXT:    neg a0, a0
577; RV64I-NEXT:    ret
578; RV64I-NEXT:  .LBB10_2:
579; RV64I-NEXT:    sub a0, a0, a1
580; RV64I-NEXT:    neg a0, a0
581; RV64I-NEXT:    ret
582;
583; RV32ZBB-LABEL: abd_ext_i64_undef:
584; RV32ZBB:       # %bb.0:
585; RV32ZBB-NEXT:    sltu a4, a0, a2
586; RV32ZBB-NEXT:    sub a3, a1, a3
587; RV32ZBB-NEXT:    sub a3, a3, a4
588; RV32ZBB-NEXT:    sub a2, a0, a2
589; RV32ZBB-NEXT:    beq a3, a1, .LBB10_2
590; RV32ZBB-NEXT:  # %bb.1:
591; RV32ZBB-NEXT:    sltu a0, a1, a3
592; RV32ZBB-NEXT:    j .LBB10_3
593; RV32ZBB-NEXT:  .LBB10_2:
594; RV32ZBB-NEXT:    sltu a0, a0, a2
595; RV32ZBB-NEXT:  .LBB10_3:
596; RV32ZBB-NEXT:    neg a1, a0
597; RV32ZBB-NEXT:    xor a2, a2, a1
598; RV32ZBB-NEXT:    xor a3, a3, a1
599; RV32ZBB-NEXT:    sltu a1, a2, a1
600; RV32ZBB-NEXT:    add a3, a3, a0
601; RV32ZBB-NEXT:    add a0, a2, a0
602; RV32ZBB-NEXT:    sub a3, a3, a1
603; RV32ZBB-NEXT:    snez a1, a0
604; RV32ZBB-NEXT:    add a1, a3, a1
605; RV32ZBB-NEXT:    neg a1, a1
606; RV32ZBB-NEXT:    neg a0, a0
607; RV32ZBB-NEXT:    ret
608;
609; RV64ZBB-LABEL: abd_ext_i64_undef:
610; RV64ZBB:       # %bb.0:
611; RV64ZBB-NEXT:    maxu a2, a0, a1
612; RV64ZBB-NEXT:    minu a0, a0, a1
613; RV64ZBB-NEXT:    sub a0, a0, a2
614; RV64ZBB-NEXT:    ret
615  %aext = zext i64 %a to i128
616  %bext = zext i64 %b to i128
617  %sub = sub i128 %aext, %bext
618  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
619  %nabs = sub i128 0, %abs
620  %trunc = trunc i128 %nabs to i64
621  ret i64 %trunc
622}
623
624define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
625; RV32I-LABEL: abd_ext_i128:
626; RV32I:       # %bb.0:
627; RV32I-NEXT:    lw a5, 0(a2)
628; RV32I-NEXT:    lw a7, 4(a2)
629; RV32I-NEXT:    lw a3, 8(a2)
630; RV32I-NEXT:    lw t1, 12(a2)
631; RV32I-NEXT:    lw a4, 8(a1)
632; RV32I-NEXT:    lw a6, 12(a1)
633; RV32I-NEXT:    lw a2, 0(a1)
634; RV32I-NEXT:    lw t0, 4(a1)
635; RV32I-NEXT:    sltu a1, a4, a3
636; RV32I-NEXT:    sub t1, a6, t1
637; RV32I-NEXT:    sltu t2, a2, a5
638; RV32I-NEXT:    sub a1, t1, a1
639; RV32I-NEXT:    mv t1, t2
640; RV32I-NEXT:    beq t0, a7, .LBB11_2
641; RV32I-NEXT:  # %bb.1:
642; RV32I-NEXT:    sltu t1, t0, a7
643; RV32I-NEXT:  .LBB11_2:
644; RV32I-NEXT:    sub a3, a4, a3
645; RV32I-NEXT:    sltu t3, a3, t1
646; RV32I-NEXT:    sub a1, a1, t3
647; RV32I-NEXT:    sub a3, a3, t1
648; RV32I-NEXT:    beq a1, a6, .LBB11_4
649; RV32I-NEXT:  # %bb.3:
650; RV32I-NEXT:    sltu t1, a6, a1
651; RV32I-NEXT:    j .LBB11_5
652; RV32I-NEXT:  .LBB11_4:
653; RV32I-NEXT:    sltu t1, a4, a3
654; RV32I-NEXT:  .LBB11_5:
655; RV32I-NEXT:    sub a7, t0, a7
656; RV32I-NEXT:    sub a7, a7, t2
657; RV32I-NEXT:    sub a5, a2, a5
658; RV32I-NEXT:    beq a7, t0, .LBB11_7
659; RV32I-NEXT:  # %bb.6:
660; RV32I-NEXT:    sltu a2, t0, a7
661; RV32I-NEXT:    j .LBB11_8
662; RV32I-NEXT:  .LBB11_7:
663; RV32I-NEXT:    sltu a2, a2, a5
664; RV32I-NEXT:  .LBB11_8:
665; RV32I-NEXT:    xor a6, a1, a6
666; RV32I-NEXT:    xor a4, a3, a4
667; RV32I-NEXT:    or a4, a4, a6
668; RV32I-NEXT:    beqz a4, .LBB11_10
669; RV32I-NEXT:  # %bb.9:
670; RV32I-NEXT:    mv a2, t1
671; RV32I-NEXT:  .LBB11_10:
672; RV32I-NEXT:    neg a4, a2
673; RV32I-NEXT:    xor t0, a5, a4
674; RV32I-NEXT:    xor t3, a7, a4
675; RV32I-NEXT:    sltu a5, t0, a4
676; RV32I-NEXT:    add a6, t3, a2
677; RV32I-NEXT:    add t0, t0, a2
678; RV32I-NEXT:    sub t1, a6, a5
679; RV32I-NEXT:    snez a6, t1
680; RV32I-NEXT:    snez t2, t0
681; RV32I-NEXT:    or a6, t2, a6
682; RV32I-NEXT:    beqz a7, .LBB11_12
683; RV32I-NEXT:  # %bb.11:
684; RV32I-NEXT:    sltu a5, t3, a4
685; RV32I-NEXT:  .LBB11_12:
686; RV32I-NEXT:    xor a3, a3, a4
687; RV32I-NEXT:    xor a1, a1, a4
688; RV32I-NEXT:    add t1, t1, t2
689; RV32I-NEXT:    neg a7, t0
690; RV32I-NEXT:    add t0, a3, a2
691; RV32I-NEXT:    sltu a3, a3, a4
692; RV32I-NEXT:    add a1, a1, a2
693; RV32I-NEXT:    neg a2, t1
694; RV32I-NEXT:    sub a4, t0, a5
695; RV32I-NEXT:    sub a1, a1, a3
696; RV32I-NEXT:    sltu a3, t0, a5
697; RV32I-NEXT:    neg a5, a4
698; RV32I-NEXT:    sub a1, a1, a3
699; RV32I-NEXT:    snez a3, a4
700; RV32I-NEXT:    sltu a4, a5, a6
701; RV32I-NEXT:    add a1, a1, a3
702; RV32I-NEXT:    sub a3, a5, a6
703; RV32I-NEXT:    neg a1, a1
704; RV32I-NEXT:    sub a1, a1, a4
705; RV32I-NEXT:    sw a7, 0(a0)
706; RV32I-NEXT:    sw a2, 4(a0)
707; RV32I-NEXT:    sw a3, 8(a0)
708; RV32I-NEXT:    sw a1, 12(a0)
709; RV32I-NEXT:    ret
710;
711; RV64I-LABEL: abd_ext_i128:
712; RV64I:       # %bb.0:
713; RV64I-NEXT:    sltu a4, a0, a2
714; RV64I-NEXT:    sub a3, a1, a3
715; RV64I-NEXT:    sub a3, a3, a4
716; RV64I-NEXT:    sub a2, a0, a2
717; RV64I-NEXT:    beq a3, a1, .LBB11_2
718; RV64I-NEXT:  # %bb.1:
719; RV64I-NEXT:    sltu a0, a1, a3
720; RV64I-NEXT:    j .LBB11_3
721; RV64I-NEXT:  .LBB11_2:
722; RV64I-NEXT:    sltu a0, a0, a2
723; RV64I-NEXT:  .LBB11_3:
724; RV64I-NEXT:    neg a1, a0
725; RV64I-NEXT:    xor a2, a2, a1
726; RV64I-NEXT:    xor a3, a3, a1
727; RV64I-NEXT:    sltu a1, a2, a1
728; RV64I-NEXT:    add a3, a3, a0
729; RV64I-NEXT:    add a0, a2, a0
730; RV64I-NEXT:    sub a3, a3, a1
731; RV64I-NEXT:    snez a1, a0
732; RV64I-NEXT:    add a1, a3, a1
733; RV64I-NEXT:    neg a1, a1
734; RV64I-NEXT:    neg a0, a0
735; RV64I-NEXT:    ret
736;
737; RV32ZBB-LABEL: abd_ext_i128:
738; RV32ZBB:       # %bb.0:
739; RV32ZBB-NEXT:    lw a5, 0(a2)
740; RV32ZBB-NEXT:    lw a7, 4(a2)
741; RV32ZBB-NEXT:    lw a3, 8(a2)
742; RV32ZBB-NEXT:    lw t1, 12(a2)
743; RV32ZBB-NEXT:    lw a4, 8(a1)
744; RV32ZBB-NEXT:    lw a6, 12(a1)
745; RV32ZBB-NEXT:    lw a2, 0(a1)
746; RV32ZBB-NEXT:    lw t0, 4(a1)
747; RV32ZBB-NEXT:    sltu a1, a4, a3
748; RV32ZBB-NEXT:    sub t1, a6, t1
749; RV32ZBB-NEXT:    sltu t2, a2, a5
750; RV32ZBB-NEXT:    sub a1, t1, a1
751; RV32ZBB-NEXT:    mv t1, t2
752; RV32ZBB-NEXT:    beq t0, a7, .LBB11_2
753; RV32ZBB-NEXT:  # %bb.1:
754; RV32ZBB-NEXT:    sltu t1, t0, a7
755; RV32ZBB-NEXT:  .LBB11_2:
756; RV32ZBB-NEXT:    sub a3, a4, a3
757; RV32ZBB-NEXT:    sltu t3, a3, t1
758; RV32ZBB-NEXT:    sub a1, a1, t3
759; RV32ZBB-NEXT:    sub a3, a3, t1
760; RV32ZBB-NEXT:    beq a1, a6, .LBB11_4
761; RV32ZBB-NEXT:  # %bb.3:
762; RV32ZBB-NEXT:    sltu t1, a6, a1
763; RV32ZBB-NEXT:    j .LBB11_5
764; RV32ZBB-NEXT:  .LBB11_4:
765; RV32ZBB-NEXT:    sltu t1, a4, a3
766; RV32ZBB-NEXT:  .LBB11_5:
767; RV32ZBB-NEXT:    sub a7, t0, a7
768; RV32ZBB-NEXT:    sub a7, a7, t2
769; RV32ZBB-NEXT:    sub a5, a2, a5
770; RV32ZBB-NEXT:    beq a7, t0, .LBB11_7
771; RV32ZBB-NEXT:  # %bb.6:
772; RV32ZBB-NEXT:    sltu a2, t0, a7
773; RV32ZBB-NEXT:    j .LBB11_8
774; RV32ZBB-NEXT:  .LBB11_7:
775; RV32ZBB-NEXT:    sltu a2, a2, a5
776; RV32ZBB-NEXT:  .LBB11_8:
777; RV32ZBB-NEXT:    xor a6, a1, a6
778; RV32ZBB-NEXT:    xor a4, a3, a4
779; RV32ZBB-NEXT:    or a4, a4, a6
780; RV32ZBB-NEXT:    beqz a4, .LBB11_10
781; RV32ZBB-NEXT:  # %bb.9:
782; RV32ZBB-NEXT:    mv a2, t1
783; RV32ZBB-NEXT:  .LBB11_10:
784; RV32ZBB-NEXT:    neg a4, a2
785; RV32ZBB-NEXT:    xor t0, a5, a4
786; RV32ZBB-NEXT:    xor t3, a7, a4
787; RV32ZBB-NEXT:    sltu a5, t0, a4
788; RV32ZBB-NEXT:    add a6, t3, a2
789; RV32ZBB-NEXT:    add t0, t0, a2
790; RV32ZBB-NEXT:    sub t1, a6, a5
791; RV32ZBB-NEXT:    snez a6, t1
792; RV32ZBB-NEXT:    snez t2, t0
793; RV32ZBB-NEXT:    or a6, t2, a6
794; RV32ZBB-NEXT:    beqz a7, .LBB11_12
795; RV32ZBB-NEXT:  # %bb.11:
796; RV32ZBB-NEXT:    sltu a5, t3, a4
797; RV32ZBB-NEXT:  .LBB11_12:
798; RV32ZBB-NEXT:    xor a3, a3, a4
799; RV32ZBB-NEXT:    xor a1, a1, a4
800; RV32ZBB-NEXT:    add t1, t1, t2
801; RV32ZBB-NEXT:    neg a7, t0
802; RV32ZBB-NEXT:    add t0, a3, a2
803; RV32ZBB-NEXT:    sltu a3, a3, a4
804; RV32ZBB-NEXT:    add a1, a1, a2
805; RV32ZBB-NEXT:    neg a2, t1
806; RV32ZBB-NEXT:    sub a4, t0, a5
807; RV32ZBB-NEXT:    sub a1, a1, a3
808; RV32ZBB-NEXT:    sltu a3, t0, a5
809; RV32ZBB-NEXT:    neg a5, a4
810; RV32ZBB-NEXT:    sub a1, a1, a3
811; RV32ZBB-NEXT:    snez a3, a4
812; RV32ZBB-NEXT:    sltu a4, a5, a6
813; RV32ZBB-NEXT:    add a1, a1, a3
814; RV32ZBB-NEXT:    sub a3, a5, a6
815; RV32ZBB-NEXT:    neg a1, a1
816; RV32ZBB-NEXT:    sub a1, a1, a4
817; RV32ZBB-NEXT:    sw a7, 0(a0)
818; RV32ZBB-NEXT:    sw a2, 4(a0)
819; RV32ZBB-NEXT:    sw a3, 8(a0)
820; RV32ZBB-NEXT:    sw a1, 12(a0)
821; RV32ZBB-NEXT:    ret
822;
823; RV64ZBB-LABEL: abd_ext_i128:
824; RV64ZBB:       # %bb.0:
825; RV64ZBB-NEXT:    sltu a4, a0, a2
826; RV64ZBB-NEXT:    sub a3, a1, a3
827; RV64ZBB-NEXT:    sub a3, a3, a4
828; RV64ZBB-NEXT:    sub a2, a0, a2
829; RV64ZBB-NEXT:    beq a3, a1, .LBB11_2
830; RV64ZBB-NEXT:  # %bb.1:
831; RV64ZBB-NEXT:    sltu a0, a1, a3
832; RV64ZBB-NEXT:    j .LBB11_3
833; RV64ZBB-NEXT:  .LBB11_2:
834; RV64ZBB-NEXT:    sltu a0, a0, a2
835; RV64ZBB-NEXT:  .LBB11_3:
836; RV64ZBB-NEXT:    neg a1, a0
837; RV64ZBB-NEXT:    xor a2, a2, a1
838; RV64ZBB-NEXT:    xor a3, a3, a1
839; RV64ZBB-NEXT:    sltu a1, a2, a1
840; RV64ZBB-NEXT:    add a3, a3, a0
841; RV64ZBB-NEXT:    add a0, a2, a0
842; RV64ZBB-NEXT:    sub a3, a3, a1
843; RV64ZBB-NEXT:    snez a1, a0
844; RV64ZBB-NEXT:    add a1, a3, a1
845; RV64ZBB-NEXT:    neg a1, a1
846; RV64ZBB-NEXT:    neg a0, a0
847; RV64ZBB-NEXT:    ret
848  %aext = zext i128 %a to i256
849  %bext = zext i128 %b to i256
850  %sub = sub i256 %aext, %bext
851  %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
852  %nabs = sub i256 0, %abs
853  %trunc = trunc i256 %nabs to i128
854  ret i128 %trunc
855}
856
857define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
858; RV32I-LABEL: abd_ext_i128_undef:
859; RV32I:       # %bb.0:
860; RV32I-NEXT:    lw a5, 0(a2)
861; RV32I-NEXT:    lw a7, 4(a2)
862; RV32I-NEXT:    lw a3, 8(a2)
863; RV32I-NEXT:    lw t1, 12(a2)
864; RV32I-NEXT:    lw a4, 8(a1)
865; RV32I-NEXT:    lw a6, 12(a1)
866; RV32I-NEXT:    lw a2, 0(a1)
867; RV32I-NEXT:    lw t0, 4(a1)
868; RV32I-NEXT:    sltu a1, a4, a3
869; RV32I-NEXT:    sub t1, a6, t1
870; RV32I-NEXT:    sltu t2, a2, a5
871; RV32I-NEXT:    sub a1, t1, a1
872; RV32I-NEXT:    mv t1, t2
873; RV32I-NEXT:    beq t0, a7, .LBB12_2
874; RV32I-NEXT:  # %bb.1:
875; RV32I-NEXT:    sltu t1, t0, a7
876; RV32I-NEXT:  .LBB12_2:
877; RV32I-NEXT:    sub a3, a4, a3
878; RV32I-NEXT:    sltu t3, a3, t1
879; RV32I-NEXT:    sub a1, a1, t3
880; RV32I-NEXT:    sub a3, a3, t1
881; RV32I-NEXT:    beq a1, a6, .LBB12_4
882; RV32I-NEXT:  # %bb.3:
883; RV32I-NEXT:    sltu t1, a6, a1
884; RV32I-NEXT:    j .LBB12_5
885; RV32I-NEXT:  .LBB12_4:
886; RV32I-NEXT:    sltu t1, a4, a3
887; RV32I-NEXT:  .LBB12_5:
888; RV32I-NEXT:    sub a7, t0, a7
889; RV32I-NEXT:    sub a7, a7, t2
890; RV32I-NEXT:    sub a5, a2, a5
891; RV32I-NEXT:    beq a7, t0, .LBB12_7
892; RV32I-NEXT:  # %bb.6:
893; RV32I-NEXT:    sltu a2, t0, a7
894; RV32I-NEXT:    j .LBB12_8
895; RV32I-NEXT:  .LBB12_7:
896; RV32I-NEXT:    sltu a2, a2, a5
897; RV32I-NEXT:  .LBB12_8:
898; RV32I-NEXT:    xor a6, a1, a6
899; RV32I-NEXT:    xor a4, a3, a4
900; RV32I-NEXT:    or a4, a4, a6
901; RV32I-NEXT:    beqz a4, .LBB12_10
902; RV32I-NEXT:  # %bb.9:
903; RV32I-NEXT:    mv a2, t1
904; RV32I-NEXT:  .LBB12_10:
905; RV32I-NEXT:    neg a4, a2
906; RV32I-NEXT:    xor t0, a5, a4
907; RV32I-NEXT:    xor t3, a7, a4
908; RV32I-NEXT:    sltu a5, t0, a4
909; RV32I-NEXT:    add a6, t3, a2
910; RV32I-NEXT:    add t0, t0, a2
911; RV32I-NEXT:    sub t1, a6, a5
912; RV32I-NEXT:    snez a6, t1
913; RV32I-NEXT:    snez t2, t0
914; RV32I-NEXT:    or a6, t2, a6
915; RV32I-NEXT:    beqz a7, .LBB12_12
916; RV32I-NEXT:  # %bb.11:
917; RV32I-NEXT:    sltu a5, t3, a4
918; RV32I-NEXT:  .LBB12_12:
919; RV32I-NEXT:    xor a3, a3, a4
920; RV32I-NEXT:    xor a1, a1, a4
921; RV32I-NEXT:    add t1, t1, t2
922; RV32I-NEXT:    neg a7, t0
923; RV32I-NEXT:    add t0, a3, a2
924; RV32I-NEXT:    sltu a3, a3, a4
925; RV32I-NEXT:    add a1, a1, a2
926; RV32I-NEXT:    neg a2, t1
927; RV32I-NEXT:    sub a4, t0, a5
928; RV32I-NEXT:    sub a1, a1, a3
929; RV32I-NEXT:    sltu a3, t0, a5
930; RV32I-NEXT:    neg a5, a4
931; RV32I-NEXT:    sub a1, a1, a3
932; RV32I-NEXT:    snez a3, a4
933; RV32I-NEXT:    sltu a4, a5, a6
934; RV32I-NEXT:    add a1, a1, a3
935; RV32I-NEXT:    sub a3, a5, a6
936; RV32I-NEXT:    neg a1, a1
937; RV32I-NEXT:    sub a1, a1, a4
938; RV32I-NEXT:    sw a7, 0(a0)
939; RV32I-NEXT:    sw a2, 4(a0)
940; RV32I-NEXT:    sw a3, 8(a0)
941; RV32I-NEXT:    sw a1, 12(a0)
942; RV32I-NEXT:    ret
943;
944; RV64I-LABEL: abd_ext_i128_undef:
945; RV64I:       # %bb.0:
946; RV64I-NEXT:    sltu a4, a0, a2
947; RV64I-NEXT:    sub a3, a1, a3
948; RV64I-NEXT:    sub a3, a3, a4
949; RV64I-NEXT:    sub a2, a0, a2
950; RV64I-NEXT:    beq a3, a1, .LBB12_2
951; RV64I-NEXT:  # %bb.1:
952; RV64I-NEXT:    sltu a0, a1, a3
953; RV64I-NEXT:    j .LBB12_3
954; RV64I-NEXT:  .LBB12_2:
955; RV64I-NEXT:    sltu a0, a0, a2
956; RV64I-NEXT:  .LBB12_3:
957; RV64I-NEXT:    neg a1, a0
958; RV64I-NEXT:    xor a2, a2, a1
959; RV64I-NEXT:    xor a3, a3, a1
960; RV64I-NEXT:    sltu a1, a2, a1
961; RV64I-NEXT:    add a3, a3, a0
962; RV64I-NEXT:    add a0, a2, a0
963; RV64I-NEXT:    sub a3, a3, a1
964; RV64I-NEXT:    snez a1, a0
965; RV64I-NEXT:    add a1, a3, a1
966; RV64I-NEXT:    neg a1, a1
967; RV64I-NEXT:    neg a0, a0
968; RV64I-NEXT:    ret
969;
970; RV32ZBB-LABEL: abd_ext_i128_undef:
971; RV32ZBB:       # %bb.0:
972; RV32ZBB-NEXT:    lw a5, 0(a2)
973; RV32ZBB-NEXT:    lw a7, 4(a2)
974; RV32ZBB-NEXT:    lw a3, 8(a2)
975; RV32ZBB-NEXT:    lw t1, 12(a2)
976; RV32ZBB-NEXT:    lw a4, 8(a1)
977; RV32ZBB-NEXT:    lw a6, 12(a1)
978; RV32ZBB-NEXT:    lw a2, 0(a1)
979; RV32ZBB-NEXT:    lw t0, 4(a1)
980; RV32ZBB-NEXT:    sltu a1, a4, a3
981; RV32ZBB-NEXT:    sub t1, a6, t1
982; RV32ZBB-NEXT:    sltu t2, a2, a5
983; RV32ZBB-NEXT:    sub a1, t1, a1
984; RV32ZBB-NEXT:    mv t1, t2
985; RV32ZBB-NEXT:    beq t0, a7, .LBB12_2
986; RV32ZBB-NEXT:  # %bb.1:
987; RV32ZBB-NEXT:    sltu t1, t0, a7
988; RV32ZBB-NEXT:  .LBB12_2:
989; RV32ZBB-NEXT:    sub a3, a4, a3
990; RV32ZBB-NEXT:    sltu t3, a3, t1
991; RV32ZBB-NEXT:    sub a1, a1, t3
992; RV32ZBB-NEXT:    sub a3, a3, t1
993; RV32ZBB-NEXT:    beq a1, a6, .LBB12_4
994; RV32ZBB-NEXT:  # %bb.3:
995; RV32ZBB-NEXT:    sltu t1, a6, a1
996; RV32ZBB-NEXT:    j .LBB12_5
997; RV32ZBB-NEXT:  .LBB12_4:
998; RV32ZBB-NEXT:    sltu t1, a4, a3
999; RV32ZBB-NEXT:  .LBB12_5:
1000; RV32ZBB-NEXT:    sub a7, t0, a7
1001; RV32ZBB-NEXT:    sub a7, a7, t2
1002; RV32ZBB-NEXT:    sub a5, a2, a5
1003; RV32ZBB-NEXT:    beq a7, t0, .LBB12_7
1004; RV32ZBB-NEXT:  # %bb.6:
1005; RV32ZBB-NEXT:    sltu a2, t0, a7
1006; RV32ZBB-NEXT:    j .LBB12_8
1007; RV32ZBB-NEXT:  .LBB12_7:
1008; RV32ZBB-NEXT:    sltu a2, a2, a5
1009; RV32ZBB-NEXT:  .LBB12_8:
1010; RV32ZBB-NEXT:    xor a6, a1, a6
1011; RV32ZBB-NEXT:    xor a4, a3, a4
1012; RV32ZBB-NEXT:    or a4, a4, a6
1013; RV32ZBB-NEXT:    beqz a4, .LBB12_10
1014; RV32ZBB-NEXT:  # %bb.9:
1015; RV32ZBB-NEXT:    mv a2, t1
1016; RV32ZBB-NEXT:  .LBB12_10:
1017; RV32ZBB-NEXT:    neg a4, a2
1018; RV32ZBB-NEXT:    xor t0, a5, a4
1019; RV32ZBB-NEXT:    xor t3, a7, a4
1020; RV32ZBB-NEXT:    sltu a5, t0, a4
1021; RV32ZBB-NEXT:    add a6, t3, a2
1022; RV32ZBB-NEXT:    add t0, t0, a2
1023; RV32ZBB-NEXT:    sub t1, a6, a5
1024; RV32ZBB-NEXT:    snez a6, t1
1025; RV32ZBB-NEXT:    snez t2, t0
1026; RV32ZBB-NEXT:    or a6, t2, a6
1027; RV32ZBB-NEXT:    beqz a7, .LBB12_12
1028; RV32ZBB-NEXT:  # %bb.11:
1029; RV32ZBB-NEXT:    sltu a5, t3, a4
1030; RV32ZBB-NEXT:  .LBB12_12:
1031; RV32ZBB-NEXT:    xor a3, a3, a4
1032; RV32ZBB-NEXT:    xor a1, a1, a4
1033; RV32ZBB-NEXT:    add t1, t1, t2
1034; RV32ZBB-NEXT:    neg a7, t0
1035; RV32ZBB-NEXT:    add t0, a3, a2
1036; RV32ZBB-NEXT:    sltu a3, a3, a4
1037; RV32ZBB-NEXT:    add a1, a1, a2
1038; RV32ZBB-NEXT:    neg a2, t1
1039; RV32ZBB-NEXT:    sub a4, t0, a5
1040; RV32ZBB-NEXT:    sub a1, a1, a3
1041; RV32ZBB-NEXT:    sltu a3, t0, a5
1042; RV32ZBB-NEXT:    neg a5, a4
1043; RV32ZBB-NEXT:    sub a1, a1, a3
1044; RV32ZBB-NEXT:    snez a3, a4
1045; RV32ZBB-NEXT:    sltu a4, a5, a6
1046; RV32ZBB-NEXT:    add a1, a1, a3
1047; RV32ZBB-NEXT:    sub a3, a5, a6
1048; RV32ZBB-NEXT:    neg a1, a1
1049; RV32ZBB-NEXT:    sub a1, a1, a4
1050; RV32ZBB-NEXT:    sw a7, 0(a0)
1051; RV32ZBB-NEXT:    sw a2, 4(a0)
1052; RV32ZBB-NEXT:    sw a3, 8(a0)
1053; RV32ZBB-NEXT:    sw a1, 12(a0)
1054; RV32ZBB-NEXT:    ret
1055;
1056; RV64ZBB-LABEL: abd_ext_i128_undef:
1057; RV64ZBB:       # %bb.0:
1058; RV64ZBB-NEXT:    sltu a4, a0, a2
1059; RV64ZBB-NEXT:    sub a3, a1, a3
1060; RV64ZBB-NEXT:    sub a3, a3, a4
1061; RV64ZBB-NEXT:    sub a2, a0, a2
1062; RV64ZBB-NEXT:    beq a3, a1, .LBB12_2
1063; RV64ZBB-NEXT:  # %bb.1:
1064; RV64ZBB-NEXT:    sltu a0, a1, a3
1065; RV64ZBB-NEXT:    j .LBB12_3
1066; RV64ZBB-NEXT:  .LBB12_2:
1067; RV64ZBB-NEXT:    sltu a0, a0, a2
1068; RV64ZBB-NEXT:  .LBB12_3:
1069; RV64ZBB-NEXT:    neg a1, a0
1070; RV64ZBB-NEXT:    xor a2, a2, a1
1071; RV64ZBB-NEXT:    xor a3, a3, a1
1072; RV64ZBB-NEXT:    sltu a1, a2, a1
1073; RV64ZBB-NEXT:    add a3, a3, a0
1074; RV64ZBB-NEXT:    add a0, a2, a0
1075; RV64ZBB-NEXT:    sub a3, a3, a1
1076; RV64ZBB-NEXT:    snez a1, a0
1077; RV64ZBB-NEXT:    add a1, a3, a1
1078; RV64ZBB-NEXT:    neg a1, a1
1079; RV64ZBB-NEXT:    neg a0, a0
1080; RV64ZBB-NEXT:    ret
1081  %aext = zext i128 %a to i256
1082  %bext = zext i128 %b to i256
1083  %sub = sub i256 %aext, %bext
1084  %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
1085  %nabs = sub i256 0, %abs
1086  %trunc = trunc i256 %nabs to i128
1087  ret i128 %trunc
1088}
1089
1090;
1091; sub(umin(a,b),umax(a,b)) -> nabds(a,b)
1092;
1093
1094define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
1095; NOZBB-LABEL: abd_minmax_i8:
1096; NOZBB:       # %bb.0:
1097; NOZBB-NEXT:    andi a1, a1, 255
1098; NOZBB-NEXT:    andi a0, a0, 255
1099; NOZBB-NEXT:    mv a2, a0
1100; NOZBB-NEXT:    bgeu a0, a1, .LBB13_3
1101; NOZBB-NEXT:  # %bb.1:
1102; NOZBB-NEXT:    bgeu a1, a0, .LBB13_4
1103; NOZBB-NEXT:  .LBB13_2:
1104; NOZBB-NEXT:    sub a0, a2, a0
1105; NOZBB-NEXT:    ret
1106; NOZBB-NEXT:  .LBB13_3:
1107; NOZBB-NEXT:    mv a2, a1
1108; NOZBB-NEXT:    bltu a1, a0, .LBB13_2
1109; NOZBB-NEXT:  .LBB13_4:
1110; NOZBB-NEXT:    sub a0, a2, a1
1111; NOZBB-NEXT:    ret
1112;
1113; ZBB-LABEL: abd_minmax_i8:
1114; ZBB:       # %bb.0:
1115; ZBB-NEXT:    andi a1, a1, 255
1116; ZBB-NEXT:    andi a0, a0, 255
1117; ZBB-NEXT:    minu a2, a0, a1
1118; ZBB-NEXT:    maxu a0, a0, a1
1119; ZBB-NEXT:    sub a0, a2, a0
1120; ZBB-NEXT:    ret
1121  %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
1122  %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
1123  %sub = sub i8 %min, %max
1124  ret i8 %sub
1125}
1126
1127define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
1128; RV32I-LABEL: abd_minmax_i16:
1129; RV32I:       # %bb.0:
1130; RV32I-NEXT:    lui a2, 16
1131; RV32I-NEXT:    addi a2, a2, -1
1132; RV32I-NEXT:    and a1, a1, a2
1133; RV32I-NEXT:    and a0, a0, a2
1134; RV32I-NEXT:    mv a2, a0
1135; RV32I-NEXT:    bgeu a0, a1, .LBB14_3
1136; RV32I-NEXT:  # %bb.1:
1137; RV32I-NEXT:    bgeu a1, a0, .LBB14_4
1138; RV32I-NEXT:  .LBB14_2:
1139; RV32I-NEXT:    sub a0, a2, a0
1140; RV32I-NEXT:    ret
1141; RV32I-NEXT:  .LBB14_3:
1142; RV32I-NEXT:    mv a2, a1
1143; RV32I-NEXT:    bltu a1, a0, .LBB14_2
1144; RV32I-NEXT:  .LBB14_4:
1145; RV32I-NEXT:    sub a0, a2, a1
1146; RV32I-NEXT:    ret
1147;
1148; RV64I-LABEL: abd_minmax_i16:
1149; RV64I:       # %bb.0:
1150; RV64I-NEXT:    lui a2, 16
1151; RV64I-NEXT:    addiw a2, a2, -1
1152; RV64I-NEXT:    and a1, a1, a2
1153; RV64I-NEXT:    and a0, a0, a2
1154; RV64I-NEXT:    mv a2, a0
1155; RV64I-NEXT:    bgeu a0, a1, .LBB14_3
1156; RV64I-NEXT:  # %bb.1:
1157; RV64I-NEXT:    bgeu a1, a0, .LBB14_4
1158; RV64I-NEXT:  .LBB14_2:
1159; RV64I-NEXT:    sub a0, a2, a0
1160; RV64I-NEXT:    ret
1161; RV64I-NEXT:  .LBB14_3:
1162; RV64I-NEXT:    mv a2, a1
1163; RV64I-NEXT:    bltu a1, a0, .LBB14_2
1164; RV64I-NEXT:  .LBB14_4:
1165; RV64I-NEXT:    sub a0, a2, a1
1166; RV64I-NEXT:    ret
1167;
1168; ZBB-LABEL: abd_minmax_i16:
1169; ZBB:       # %bb.0:
1170; ZBB-NEXT:    zext.h a1, a1
1171; ZBB-NEXT:    zext.h a0, a0
1172; ZBB-NEXT:    minu a2, a0, a1
1173; ZBB-NEXT:    maxu a0, a0, a1
1174; ZBB-NEXT:    sub a0, a2, a0
1175; ZBB-NEXT:    ret
1176  %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
1177  %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
1178  %sub = sub i16 %min, %max
1179  ret i16 %sub
1180}
1181
1182define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
1183; RV32I-LABEL: abd_minmax_i32:
1184; RV32I:       # %bb.0:
1185; RV32I-NEXT:    mv a2, a0
1186; RV32I-NEXT:    bgeu a0, a1, .LBB15_3
1187; RV32I-NEXT:  # %bb.1:
1188; RV32I-NEXT:    bgeu a1, a0, .LBB15_4
1189; RV32I-NEXT:  .LBB15_2:
1190; RV32I-NEXT:    sub a0, a2, a0
1191; RV32I-NEXT:    ret
1192; RV32I-NEXT:  .LBB15_3:
1193; RV32I-NEXT:    mv a2, a1
1194; RV32I-NEXT:    bltu a1, a0, .LBB15_2
1195; RV32I-NEXT:  .LBB15_4:
1196; RV32I-NEXT:    sub a0, a2, a1
1197; RV32I-NEXT:    ret
1198;
1199; RV64I-LABEL: abd_minmax_i32:
1200; RV64I:       # %bb.0:
1201; RV64I-NEXT:    sext.w a1, a1
1202; RV64I-NEXT:    sext.w a0, a0
1203; RV64I-NEXT:    mv a2, a0
1204; RV64I-NEXT:    bgeu a0, a1, .LBB15_3
1205; RV64I-NEXT:  # %bb.1:
1206; RV64I-NEXT:    bgeu a1, a0, .LBB15_4
1207; RV64I-NEXT:  .LBB15_2:
1208; RV64I-NEXT:    subw a0, a2, a0
1209; RV64I-NEXT:    ret
1210; RV64I-NEXT:  .LBB15_3:
1211; RV64I-NEXT:    mv a2, a1
1212; RV64I-NEXT:    bltu a1, a0, .LBB15_2
1213; RV64I-NEXT:  .LBB15_4:
1214; RV64I-NEXT:    subw a0, a2, a1
1215; RV64I-NEXT:    ret
1216;
1217; RV32ZBB-LABEL: abd_minmax_i32:
1218; RV32ZBB:       # %bb.0:
1219; RV32ZBB-NEXT:    minu a2, a0, a1
1220; RV32ZBB-NEXT:    maxu a0, a0, a1
1221; RV32ZBB-NEXT:    sub a0, a2, a0
1222; RV32ZBB-NEXT:    ret
1223;
1224; RV64ZBB-LABEL: abd_minmax_i32:
1225; RV64ZBB:       # %bb.0:
1226; RV64ZBB-NEXT:    sext.w a1, a1
1227; RV64ZBB-NEXT:    sext.w a0, a0
1228; RV64ZBB-NEXT:    minu a2, a0, a1
1229; RV64ZBB-NEXT:    maxu a0, a0, a1
1230; RV64ZBB-NEXT:    subw a0, a2, a0
1231; RV64ZBB-NEXT:    ret
1232  %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
1233  %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
1234  %sub = sub i32 %min, %max
1235  ret i32 %sub
1236}
1237
1238define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
1239; RV32I-LABEL: abd_minmax_i64:
1240; RV32I:       # %bb.0:
1241; RV32I-NEXT:    beq a1, a3, .LBB16_2
1242; RV32I-NEXT:  # %bb.1:
1243; RV32I-NEXT:    sltu a6, a1, a3
1244; RV32I-NEXT:    j .LBB16_3
1245; RV32I-NEXT:  .LBB16_2:
1246; RV32I-NEXT:    sltu a6, a0, a2
1247; RV32I-NEXT:  .LBB16_3:
1248; RV32I-NEXT:    mv a4, a1
1249; RV32I-NEXT:    mv a5, a0
1250; RV32I-NEXT:    bnez a6, .LBB16_5
1251; RV32I-NEXT:  # %bb.4:
1252; RV32I-NEXT:    mv a4, a3
1253; RV32I-NEXT:    mv a5, a2
1254; RV32I-NEXT:  .LBB16_5:
1255; RV32I-NEXT:    beq a1, a3, .LBB16_7
1256; RV32I-NEXT:  # %bb.6:
1257; RV32I-NEXT:    sltu a6, a3, a1
1258; RV32I-NEXT:    beqz a6, .LBB16_8
1259; RV32I-NEXT:    j .LBB16_9
1260; RV32I-NEXT:  .LBB16_7:
1261; RV32I-NEXT:    sltu a6, a2, a0
1262; RV32I-NEXT:    bnez a6, .LBB16_9
1263; RV32I-NEXT:  .LBB16_8:
1264; RV32I-NEXT:    mv a1, a3
1265; RV32I-NEXT:    mv a0, a2
1266; RV32I-NEXT:  .LBB16_9:
1267; RV32I-NEXT:    sltu a2, a5, a0
1268; RV32I-NEXT:    sub a1, a4, a1
1269; RV32I-NEXT:    sub a1, a1, a2
1270; RV32I-NEXT:    sub a0, a5, a0
1271; RV32I-NEXT:    ret
1272;
1273; RV64I-LABEL: abd_minmax_i64:
1274; RV64I:       # %bb.0:
1275; RV64I-NEXT:    mv a2, a0
1276; RV64I-NEXT:    bgeu a0, a1, .LBB16_3
1277; RV64I-NEXT:  # %bb.1:
1278; RV64I-NEXT:    bgeu a1, a0, .LBB16_4
1279; RV64I-NEXT:  .LBB16_2:
1280; RV64I-NEXT:    sub a0, a2, a0
1281; RV64I-NEXT:    ret
1282; RV64I-NEXT:  .LBB16_3:
1283; RV64I-NEXT:    mv a2, a1
1284; RV64I-NEXT:    bltu a1, a0, .LBB16_2
1285; RV64I-NEXT:  .LBB16_4:
1286; RV64I-NEXT:    sub a0, a2, a1
1287; RV64I-NEXT:    ret
1288;
1289; RV32ZBB-LABEL: abd_minmax_i64:
1290; RV32ZBB:       # %bb.0:
1291; RV32ZBB-NEXT:    beq a1, a3, .LBB16_2
1292; RV32ZBB-NEXT:  # %bb.1:
1293; RV32ZBB-NEXT:    sltu a6, a1, a3
1294; RV32ZBB-NEXT:    j .LBB16_3
1295; RV32ZBB-NEXT:  .LBB16_2:
1296; RV32ZBB-NEXT:    sltu a6, a0, a2
1297; RV32ZBB-NEXT:  .LBB16_3:
1298; RV32ZBB-NEXT:    mv a4, a1
1299; RV32ZBB-NEXT:    mv a5, a0
1300; RV32ZBB-NEXT:    bnez a6, .LBB16_5
1301; RV32ZBB-NEXT:  # %bb.4:
1302; RV32ZBB-NEXT:    mv a4, a3
1303; RV32ZBB-NEXT:    mv a5, a2
1304; RV32ZBB-NEXT:  .LBB16_5:
1305; RV32ZBB-NEXT:    beq a1, a3, .LBB16_7
1306; RV32ZBB-NEXT:  # %bb.6:
1307; RV32ZBB-NEXT:    sltu a6, a3, a1
1308; RV32ZBB-NEXT:    beqz a6, .LBB16_8
1309; RV32ZBB-NEXT:    j .LBB16_9
1310; RV32ZBB-NEXT:  .LBB16_7:
1311; RV32ZBB-NEXT:    sltu a6, a2, a0
1312; RV32ZBB-NEXT:    bnez a6, .LBB16_9
1313; RV32ZBB-NEXT:  .LBB16_8:
1314; RV32ZBB-NEXT:    mv a1, a3
1315; RV32ZBB-NEXT:    mv a0, a2
1316; RV32ZBB-NEXT:  .LBB16_9:
1317; RV32ZBB-NEXT:    sltu a2, a5, a0
1318; RV32ZBB-NEXT:    sub a1, a4, a1
1319; RV32ZBB-NEXT:    sub a1, a1, a2
1320; RV32ZBB-NEXT:    sub a0, a5, a0
1321; RV32ZBB-NEXT:    ret
1322;
1323; RV64ZBB-LABEL: abd_minmax_i64:
1324; RV64ZBB:       # %bb.0:
1325; RV64ZBB-NEXT:    minu a2, a0, a1
1326; RV64ZBB-NEXT:    maxu a0, a0, a1
1327; RV64ZBB-NEXT:    sub a0, a2, a0
1328; RV64ZBB-NEXT:    ret
1329  %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
1330  %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
1331  %sub = sub i64 %min, %max
1332  ret i64 %sub
1333}
1334
1335define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
1336; RV32I-LABEL: abd_minmax_i128:
1337; RV32I:       # %bb.0:
1338; RV32I-NEXT:    lw a6, 4(a2)
1339; RV32I-NEXT:    lw a7, 8(a2)
1340; RV32I-NEXT:    lw t0, 12(a2)
1341; RV32I-NEXT:    lw a5, 12(a1)
1342; RV32I-NEXT:    lw a3, 4(a1)
1343; RV32I-NEXT:    lw a4, 8(a1)
1344; RV32I-NEXT:    beq a5, t0, .LBB17_2
1345; RV32I-NEXT:  # %bb.1:
1346; RV32I-NEXT:    sltu t1, a5, t0
1347; RV32I-NEXT:    j .LBB17_3
1348; RV32I-NEXT:  .LBB17_2:
1349; RV32I-NEXT:    sltu t1, a4, a7
1350; RV32I-NEXT:  .LBB17_3:
1351; RV32I-NEXT:    lw t2, 0(a2)
1352; RV32I-NEXT:    lw a1, 0(a1)
1353; RV32I-NEXT:    beq a3, a6, .LBB17_5
1354; RV32I-NEXT:  # %bb.4:
1355; RV32I-NEXT:    sltu t6, a3, a6
1356; RV32I-NEXT:    j .LBB17_6
1357; RV32I-NEXT:  .LBB17_5:
1358; RV32I-NEXT:    sltu t6, a1, t2
1359; RV32I-NEXT:  .LBB17_6:
1360; RV32I-NEXT:    xor a2, a5, t0
1361; RV32I-NEXT:    xor t3, a4, a7
1362; RV32I-NEXT:    or t5, t3, a2
1363; RV32I-NEXT:    beqz t5, .LBB17_8
1364; RV32I-NEXT:  # %bb.7:
1365; RV32I-NEXT:    mv t6, t1
1366; RV32I-NEXT:  .LBB17_8:
1367; RV32I-NEXT:    mv a2, a1
1368; RV32I-NEXT:    mv t1, a3
1369; RV32I-NEXT:    mv t4, a5
1370; RV32I-NEXT:    mv t3, a4
1371; RV32I-NEXT:    bnez t6, .LBB17_10
1372; RV32I-NEXT:  # %bb.9:
1373; RV32I-NEXT:    mv a2, t2
1374; RV32I-NEXT:    mv t1, a6
1375; RV32I-NEXT:    mv t4, t0
1376; RV32I-NEXT:    mv t3, a7
1377; RV32I-NEXT:  .LBB17_10:
1378; RV32I-NEXT:    beq a5, t0, .LBB17_12
1379; RV32I-NEXT:  # %bb.11:
1380; RV32I-NEXT:    sltu t6, t0, a5
1381; RV32I-NEXT:    j .LBB17_13
1382; RV32I-NEXT:  .LBB17_12:
1383; RV32I-NEXT:    sltu t6, a7, a4
1384; RV32I-NEXT:  .LBB17_13:
1385; RV32I-NEXT:    addi sp, sp, -16
1386; RV32I-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
1387; RV32I-NEXT:    beq a3, a6, .LBB17_15
1388; RV32I-NEXT:  # %bb.14:
1389; RV32I-NEXT:    sltu s0, a6, a3
1390; RV32I-NEXT:    bnez t5, .LBB17_16
1391; RV32I-NEXT:    j .LBB17_17
1392; RV32I-NEXT:  .LBB17_15:
1393; RV32I-NEXT:    sltu s0, t2, a1
1394; RV32I-NEXT:    beqz t5, .LBB17_17
1395; RV32I-NEXT:  .LBB17_16:
1396; RV32I-NEXT:    mv s0, t6
1397; RV32I-NEXT:  .LBB17_17:
1398; RV32I-NEXT:    bnez s0, .LBB17_19
1399; RV32I-NEXT:  # %bb.18:
1400; RV32I-NEXT:    mv a1, t2
1401; RV32I-NEXT:    mv a3, a6
1402; RV32I-NEXT:    mv a5, t0
1403; RV32I-NEXT:    mv a4, a7
1404; RV32I-NEXT:  .LBB17_19:
1405; RV32I-NEXT:    sltu a7, t3, a4
1406; RV32I-NEXT:    sub a5, t4, a5
1407; RV32I-NEXT:    sltu a6, a2, a1
1408; RV32I-NEXT:    sub a5, a5, a7
1409; RV32I-NEXT:    mv a7, a6
1410; RV32I-NEXT:    beq t1, a3, .LBB17_21
1411; RV32I-NEXT:  # %bb.20:
1412; RV32I-NEXT:    sltu a7, t1, a3
1413; RV32I-NEXT:  .LBB17_21:
1414; RV32I-NEXT:    sub a4, t3, a4
1415; RV32I-NEXT:    sub a3, t1, a3
1416; RV32I-NEXT:    sub a2, a2, a1
1417; RV32I-NEXT:    sltu a1, a4, a7
1418; RV32I-NEXT:    sub a4, a4, a7
1419; RV32I-NEXT:    sub a3, a3, a6
1420; RV32I-NEXT:    sub a5, a5, a1
1421; RV32I-NEXT:    sw a2, 0(a0)
1422; RV32I-NEXT:    sw a3, 4(a0)
1423; RV32I-NEXT:    sw a4, 8(a0)
1424; RV32I-NEXT:    sw a5, 12(a0)
1425; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
1426; RV32I-NEXT:    addi sp, sp, 16
1427; RV32I-NEXT:    ret
1428;
1429; RV64I-LABEL: abd_minmax_i128:
1430; RV64I:       # %bb.0:
1431; RV64I-NEXT:    beq a1, a3, .LBB17_2
1432; RV64I-NEXT:  # %bb.1:
1433; RV64I-NEXT:    sltu a6, a1, a3
1434; RV64I-NEXT:    j .LBB17_3
1435; RV64I-NEXT:  .LBB17_2:
1436; RV64I-NEXT:    sltu a6, a0, a2
1437; RV64I-NEXT:  .LBB17_3:
1438; RV64I-NEXT:    mv a4, a1
1439; RV64I-NEXT:    mv a5, a0
1440; RV64I-NEXT:    bnez a6, .LBB17_5
1441; RV64I-NEXT:  # %bb.4:
1442; RV64I-NEXT:    mv a4, a3
1443; RV64I-NEXT:    mv a5, a2
1444; RV64I-NEXT:  .LBB17_5:
1445; RV64I-NEXT:    beq a1, a3, .LBB17_7
1446; RV64I-NEXT:  # %bb.6:
1447; RV64I-NEXT:    sltu a6, a3, a1
1448; RV64I-NEXT:    beqz a6, .LBB17_8
1449; RV64I-NEXT:    j .LBB17_9
1450; RV64I-NEXT:  .LBB17_7:
1451; RV64I-NEXT:    sltu a6, a2, a0
1452; RV64I-NEXT:    bnez a6, .LBB17_9
1453; RV64I-NEXT:  .LBB17_8:
1454; RV64I-NEXT:    mv a1, a3
1455; RV64I-NEXT:    mv a0, a2
1456; RV64I-NEXT:  .LBB17_9:
1457; RV64I-NEXT:    sltu a2, a5, a0
1458; RV64I-NEXT:    sub a1, a4, a1
1459; RV64I-NEXT:    sub a1, a1, a2
1460; RV64I-NEXT:    sub a0, a5, a0
1461; RV64I-NEXT:    ret
1462;
1463; RV32ZBB-LABEL: abd_minmax_i128:
1464; RV32ZBB:       # %bb.0:
1465; RV32ZBB-NEXT:    lw a6, 4(a2)
1466; RV32ZBB-NEXT:    lw a7, 8(a2)
1467; RV32ZBB-NEXT:    lw t0, 12(a2)
1468; RV32ZBB-NEXT:    lw a5, 12(a1)
1469; RV32ZBB-NEXT:    lw a3, 4(a1)
1470; RV32ZBB-NEXT:    lw a4, 8(a1)
1471; RV32ZBB-NEXT:    beq a5, t0, .LBB17_2
1472; RV32ZBB-NEXT:  # %bb.1:
1473; RV32ZBB-NEXT:    sltu t1, a5, t0
1474; RV32ZBB-NEXT:    j .LBB17_3
1475; RV32ZBB-NEXT:  .LBB17_2:
1476; RV32ZBB-NEXT:    sltu t1, a4, a7
1477; RV32ZBB-NEXT:  .LBB17_3:
1478; RV32ZBB-NEXT:    lw t2, 0(a2)
1479; RV32ZBB-NEXT:    lw a1, 0(a1)
1480; RV32ZBB-NEXT:    beq a3, a6, .LBB17_5
1481; RV32ZBB-NEXT:  # %bb.4:
1482; RV32ZBB-NEXT:    sltu t6, a3, a6
1483; RV32ZBB-NEXT:    j .LBB17_6
1484; RV32ZBB-NEXT:  .LBB17_5:
1485; RV32ZBB-NEXT:    sltu t6, a1, t2
1486; RV32ZBB-NEXT:  .LBB17_6:
1487; RV32ZBB-NEXT:    xor a2, a5, t0
1488; RV32ZBB-NEXT:    xor t3, a4, a7
1489; RV32ZBB-NEXT:    or t5, t3, a2
1490; RV32ZBB-NEXT:    beqz t5, .LBB17_8
1491; RV32ZBB-NEXT:  # %bb.7:
1492; RV32ZBB-NEXT:    mv t6, t1
1493; RV32ZBB-NEXT:  .LBB17_8:
1494; RV32ZBB-NEXT:    mv a2, a1
1495; RV32ZBB-NEXT:    mv t1, a3
1496; RV32ZBB-NEXT:    mv t4, a5
1497; RV32ZBB-NEXT:    mv t3, a4
1498; RV32ZBB-NEXT:    bnez t6, .LBB17_10
1499; RV32ZBB-NEXT:  # %bb.9:
1500; RV32ZBB-NEXT:    mv a2, t2
1501; RV32ZBB-NEXT:    mv t1, a6
1502; RV32ZBB-NEXT:    mv t4, t0
1503; RV32ZBB-NEXT:    mv t3, a7
1504; RV32ZBB-NEXT:  .LBB17_10:
1505; RV32ZBB-NEXT:    beq a5, t0, .LBB17_12
1506; RV32ZBB-NEXT:  # %bb.11:
1507; RV32ZBB-NEXT:    sltu t6, t0, a5
1508; RV32ZBB-NEXT:    j .LBB17_13
1509; RV32ZBB-NEXT:  .LBB17_12:
1510; RV32ZBB-NEXT:    sltu t6, a7, a4
1511; RV32ZBB-NEXT:  .LBB17_13:
1512; RV32ZBB-NEXT:    addi sp, sp, -16
1513; RV32ZBB-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
1514; RV32ZBB-NEXT:    beq a3, a6, .LBB17_15
1515; RV32ZBB-NEXT:  # %bb.14:
1516; RV32ZBB-NEXT:    sltu s0, a6, a3
1517; RV32ZBB-NEXT:    bnez t5, .LBB17_16
1518; RV32ZBB-NEXT:    j .LBB17_17
1519; RV32ZBB-NEXT:  .LBB17_15:
1520; RV32ZBB-NEXT:    sltu s0, t2, a1
1521; RV32ZBB-NEXT:    beqz t5, .LBB17_17
1522; RV32ZBB-NEXT:  .LBB17_16:
1523; RV32ZBB-NEXT:    mv s0, t6
1524; RV32ZBB-NEXT:  .LBB17_17:
1525; RV32ZBB-NEXT:    bnez s0, .LBB17_19
1526; RV32ZBB-NEXT:  # %bb.18:
1527; RV32ZBB-NEXT:    mv a1, t2
1528; RV32ZBB-NEXT:    mv a3, a6
1529; RV32ZBB-NEXT:    mv a5, t0
1530; RV32ZBB-NEXT:    mv a4, a7
1531; RV32ZBB-NEXT:  .LBB17_19:
1532; RV32ZBB-NEXT:    sltu a7, t3, a4
1533; RV32ZBB-NEXT:    sub a5, t4, a5
1534; RV32ZBB-NEXT:    sltu a6, a2, a1
1535; RV32ZBB-NEXT:    sub a5, a5, a7
1536; RV32ZBB-NEXT:    mv a7, a6
1537; RV32ZBB-NEXT:    beq t1, a3, .LBB17_21
1538; RV32ZBB-NEXT:  # %bb.20:
1539; RV32ZBB-NEXT:    sltu a7, t1, a3
1540; RV32ZBB-NEXT:  .LBB17_21:
1541; RV32ZBB-NEXT:    sub a4, t3, a4
1542; RV32ZBB-NEXT:    sub a3, t1, a3
1543; RV32ZBB-NEXT:    sub a2, a2, a1
1544; RV32ZBB-NEXT:    sltu a1, a4, a7
1545; RV32ZBB-NEXT:    sub a4, a4, a7
1546; RV32ZBB-NEXT:    sub a3, a3, a6
1547; RV32ZBB-NEXT:    sub a5, a5, a1
1548; RV32ZBB-NEXT:    sw a2, 0(a0)
1549; RV32ZBB-NEXT:    sw a3, 4(a0)
1550; RV32ZBB-NEXT:    sw a4, 8(a0)
1551; RV32ZBB-NEXT:    sw a5, 12(a0)
1552; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
1553; RV32ZBB-NEXT:    addi sp, sp, 16
1554; RV32ZBB-NEXT:    ret
1555;
1556; RV64ZBB-LABEL: abd_minmax_i128:
1557; RV64ZBB:       # %bb.0:
1558; RV64ZBB-NEXT:    beq a1, a3, .LBB17_2
1559; RV64ZBB-NEXT:  # %bb.1:
1560; RV64ZBB-NEXT:    sltu a6, a1, a3
1561; RV64ZBB-NEXT:    j .LBB17_3
1562; RV64ZBB-NEXT:  .LBB17_2:
1563; RV64ZBB-NEXT:    sltu a6, a0, a2
1564; RV64ZBB-NEXT:  .LBB17_3:
1565; RV64ZBB-NEXT:    mv a4, a1
1566; RV64ZBB-NEXT:    mv a5, a0
1567; RV64ZBB-NEXT:    bnez a6, .LBB17_5
1568; RV64ZBB-NEXT:  # %bb.4:
1569; RV64ZBB-NEXT:    mv a4, a3
1570; RV64ZBB-NEXT:    mv a5, a2
1571; RV64ZBB-NEXT:  .LBB17_5:
1572; RV64ZBB-NEXT:    beq a1, a3, .LBB17_7
1573; RV64ZBB-NEXT:  # %bb.6:
1574; RV64ZBB-NEXT:    sltu a6, a3, a1
1575; RV64ZBB-NEXT:    beqz a6, .LBB17_8
1576; RV64ZBB-NEXT:    j .LBB17_9
1577; RV64ZBB-NEXT:  .LBB17_7:
1578; RV64ZBB-NEXT:    sltu a6, a2, a0
1579; RV64ZBB-NEXT:    bnez a6, .LBB17_9
1580; RV64ZBB-NEXT:  .LBB17_8:
1581; RV64ZBB-NEXT:    mv a1, a3
1582; RV64ZBB-NEXT:    mv a0, a2
1583; RV64ZBB-NEXT:  .LBB17_9:
1584; RV64ZBB-NEXT:    sltu a2, a5, a0
1585; RV64ZBB-NEXT:    sub a1, a4, a1
1586; RV64ZBB-NEXT:    sub a1, a1, a2
1587; RV64ZBB-NEXT:    sub a0, a5, a0
1588; RV64ZBB-NEXT:    ret
1589  %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
1590  %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
1591  %sub = sub i128 %min, %max
1592  ret i128 %sub
1593}
1594
1595;
1596; select(icmp(a,b),sub(a,b),sub(b,a)) -> nabds(a,b)
1597;
1598
1599define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
1600; NOZBB-LABEL: abd_cmp_i8:
1601; NOZBB:       # %bb.0:
1602; NOZBB-NEXT:    andi a2, a0, 255
1603; NOZBB-NEXT:    andi a3, a1, 255
1604; NOZBB-NEXT:    bgeu a3, a2, .LBB18_2
1605; NOZBB-NEXT:  # %bb.1:
1606; NOZBB-NEXT:    sub a0, a1, a0
1607; NOZBB-NEXT:    ret
1608; NOZBB-NEXT:  .LBB18_2:
1609; NOZBB-NEXT:    sub a0, a0, a1
1610; NOZBB-NEXT:    ret
1611;
1612; ZBB-LABEL: abd_cmp_i8:
1613; ZBB:       # %bb.0:
1614; ZBB-NEXT:    andi a2, a0, 255
1615; ZBB-NEXT:    andi a3, a1, 255
1616; ZBB-NEXT:    bgeu a3, a2, .LBB18_2
1617; ZBB-NEXT:  # %bb.1:
1618; ZBB-NEXT:    sub a0, a1, a0
1619; ZBB-NEXT:    ret
1620; ZBB-NEXT:  .LBB18_2:
1621; ZBB-NEXT:    sub a0, a0, a1
1622; ZBB-NEXT:    ret
1623  %cmp = icmp ule i8 %a, %b
1624  %ab = sub i8 %a, %b
1625  %ba = sub i8 %b, %a
1626  %sel = select i1 %cmp, i8 %ab, i8 %ba
1627  ret i8 %sel
1628}
1629
1630define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
1631; RV32I-LABEL: abd_cmp_i16:
1632; RV32I:       # %bb.0:
1633; RV32I-NEXT:    lui a2, 16
1634; RV32I-NEXT:    addi a2, a2, -1
1635; RV32I-NEXT:    and a3, a1, a2
1636; RV32I-NEXT:    and a2, a0, a2
1637; RV32I-NEXT:    bltu a2, a3, .LBB19_2
1638; RV32I-NEXT:  # %bb.1:
1639; RV32I-NEXT:    sub a0, a1, a0
1640; RV32I-NEXT:    ret
1641; RV32I-NEXT:  .LBB19_2:
1642; RV32I-NEXT:    sub a0, a0, a1
1643; RV32I-NEXT:    ret
1644;
1645; RV64I-LABEL: abd_cmp_i16:
1646; RV64I:       # %bb.0:
1647; RV64I-NEXT:    lui a2, 16
1648; RV64I-NEXT:    addiw a2, a2, -1
1649; RV64I-NEXT:    and a3, a1, a2
1650; RV64I-NEXT:    and a2, a0, a2
1651; RV64I-NEXT:    bltu a2, a3, .LBB19_2
1652; RV64I-NEXT:  # %bb.1:
1653; RV64I-NEXT:    sub a0, a1, a0
1654; RV64I-NEXT:    ret
1655; RV64I-NEXT:  .LBB19_2:
1656; RV64I-NEXT:    sub a0, a0, a1
1657; RV64I-NEXT:    ret
1658;
1659; ZBB-LABEL: abd_cmp_i16:
1660; ZBB:       # %bb.0:
1661; ZBB-NEXT:    zext.h a2, a1
1662; ZBB-NEXT:    zext.h a3, a0
1663; ZBB-NEXT:    bltu a3, a2, .LBB19_2
1664; ZBB-NEXT:  # %bb.1:
1665; ZBB-NEXT:    sub a0, a1, a0
1666; ZBB-NEXT:    ret
1667; ZBB-NEXT:  .LBB19_2:
1668; ZBB-NEXT:    sub a0, a0, a1
1669; ZBB-NEXT:    ret
1670  %cmp = icmp ult i16 %a, %b
1671  %ab = sub i16 %a, %b
1672  %ba = sub i16 %b, %a
1673  %sel = select i1 %cmp, i16 %ab, i16 %ba
1674  ret i16 %sel
1675}
1676
1677define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
1678; RV32I-LABEL: abd_cmp_i32:
1679; RV32I:       # %bb.0:
1680; RV32I-NEXT:    bgeu a0, a1, .LBB20_2
1681; RV32I-NEXT:  # %bb.1:
1682; RV32I-NEXT:    sub a0, a0, a1
1683; RV32I-NEXT:    ret
1684; RV32I-NEXT:  .LBB20_2:
1685; RV32I-NEXT:    sub a0, a1, a0
1686; RV32I-NEXT:    ret
1687;
1688; RV64I-LABEL: abd_cmp_i32:
1689; RV64I:       # %bb.0:
1690; RV64I-NEXT:    sext.w a2, a1
1691; RV64I-NEXT:    sext.w a3, a0
1692; RV64I-NEXT:    bgeu a3, a2, .LBB20_2
1693; RV64I-NEXT:  # %bb.1:
1694; RV64I-NEXT:    subw a0, a0, a1
1695; RV64I-NEXT:    ret
1696; RV64I-NEXT:  .LBB20_2:
1697; RV64I-NEXT:    subw a0, a1, a0
1698; RV64I-NEXT:    ret
1699;
1700; RV32ZBB-LABEL: abd_cmp_i32:
1701; RV32ZBB:       # %bb.0:
1702; RV32ZBB-NEXT:    bgeu a0, a1, .LBB20_2
1703; RV32ZBB-NEXT:  # %bb.1:
1704; RV32ZBB-NEXT:    sub a0, a0, a1
1705; RV32ZBB-NEXT:    ret
1706; RV32ZBB-NEXT:  .LBB20_2:
1707; RV32ZBB-NEXT:    sub a0, a1, a0
1708; RV32ZBB-NEXT:    ret
1709;
1710; RV64ZBB-LABEL: abd_cmp_i32:
1711; RV64ZBB:       # %bb.0:
1712; RV64ZBB-NEXT:    sext.w a2, a1
1713; RV64ZBB-NEXT:    sext.w a3, a0
1714; RV64ZBB-NEXT:    bgeu a3, a2, .LBB20_2
1715; RV64ZBB-NEXT:  # %bb.1:
1716; RV64ZBB-NEXT:    subw a0, a0, a1
1717; RV64ZBB-NEXT:    ret
1718; RV64ZBB-NEXT:  .LBB20_2:
1719; RV64ZBB-NEXT:    subw a0, a1, a0
1720; RV64ZBB-NEXT:    ret
1721  %cmp = icmp uge i32 %a, %b
1722  %ab = sub i32 %a, %b
1723  %ba = sub i32 %b, %a
1724  %sel = select i1 %cmp, i32 %ba, i32 %ab
1725  ret i32 %sel
1726}
1727
1728define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
1729; RV32I-LABEL: abd_cmp_i64:
1730; RV32I:       # %bb.0:
1731; RV32I-NEXT:    sltu a4, a0, a2
1732; RV32I-NEXT:    mv a5, a4
1733; RV32I-NEXT:    beq a1, a3, .LBB21_2
1734; RV32I-NEXT:  # %bb.1:
1735; RV32I-NEXT:    sltu a5, a1, a3
1736; RV32I-NEXT:  .LBB21_2:
1737; RV32I-NEXT:    bnez a5, .LBB21_4
1738; RV32I-NEXT:  # %bb.3:
1739; RV32I-NEXT:    sltu a4, a2, a0
1740; RV32I-NEXT:    sub a1, a3, a1
1741; RV32I-NEXT:    sub a1, a1, a4
1742; RV32I-NEXT:    sub a0, a2, a0
1743; RV32I-NEXT:    ret
1744; RV32I-NEXT:  .LBB21_4:
1745; RV32I-NEXT:    sub a1, a1, a3
1746; RV32I-NEXT:    sub a1, a1, a4
1747; RV32I-NEXT:    sub a0, a0, a2
1748; RV32I-NEXT:    ret
1749;
1750; RV64I-LABEL: abd_cmp_i64:
1751; RV64I:       # %bb.0:
1752; RV64I-NEXT:    bltu a0, a1, .LBB21_2
1753; RV64I-NEXT:  # %bb.1:
1754; RV64I-NEXT:    sub a0, a1, a0
1755; RV64I-NEXT:    ret
1756; RV64I-NEXT:  .LBB21_2:
1757; RV64I-NEXT:    sub a0, a0, a1
1758; RV64I-NEXT:    ret
1759;
1760; RV32ZBB-LABEL: abd_cmp_i64:
1761; RV32ZBB:       # %bb.0:
1762; RV32ZBB-NEXT:    sltu a4, a0, a2
1763; RV32ZBB-NEXT:    mv a5, a4
1764; RV32ZBB-NEXT:    beq a1, a3, .LBB21_2
1765; RV32ZBB-NEXT:  # %bb.1:
1766; RV32ZBB-NEXT:    sltu a5, a1, a3
1767; RV32ZBB-NEXT:  .LBB21_2:
1768; RV32ZBB-NEXT:    bnez a5, .LBB21_4
1769; RV32ZBB-NEXT:  # %bb.3:
1770; RV32ZBB-NEXT:    sltu a4, a2, a0
1771; RV32ZBB-NEXT:    sub a1, a3, a1
1772; RV32ZBB-NEXT:    sub a1, a1, a4
1773; RV32ZBB-NEXT:    sub a0, a2, a0
1774; RV32ZBB-NEXT:    ret
1775; RV32ZBB-NEXT:  .LBB21_4:
1776; RV32ZBB-NEXT:    sub a1, a1, a3
1777; RV32ZBB-NEXT:    sub a1, a1, a4
1778; RV32ZBB-NEXT:    sub a0, a0, a2
1779; RV32ZBB-NEXT:    ret
1780;
1781; RV64ZBB-LABEL: abd_cmp_i64:
1782; RV64ZBB:       # %bb.0:
1783; RV64ZBB-NEXT:    bltu a0, a1, .LBB21_2
1784; RV64ZBB-NEXT:  # %bb.1:
1785; RV64ZBB-NEXT:    sub a0, a1, a0
1786; RV64ZBB-NEXT:    ret
1787; RV64ZBB-NEXT:  .LBB21_2:
1788; RV64ZBB-NEXT:    sub a0, a0, a1
1789; RV64ZBB-NEXT:    ret
1790  %cmp = icmp ult i64 %a, %b
1791  %ab = sub i64 %a, %b
1792  %ba = sub i64 %b, %a
1793  %sel = select i1 %cmp, i64 %ab, i64 %ba
1794  ret i64 %sel
1795}
1796
1797define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
1798; RV32I-LABEL: abd_cmp_i128:
1799; RV32I:       # %bb.0:
1800; RV32I-NEXT:    lw a3, 0(a2)
1801; RV32I-NEXT:    lw a4, 4(a2)
1802; RV32I-NEXT:    lw a5, 8(a2)
1803; RV32I-NEXT:    lw a7, 12(a2)
1804; RV32I-NEXT:    lw a6, 8(a1)
1805; RV32I-NEXT:    lw t0, 12(a1)
1806; RV32I-NEXT:    lw a2, 0(a1)
1807; RV32I-NEXT:    lw a1, 4(a1)
1808; RV32I-NEXT:    sltu t1, a6, a5
1809; RV32I-NEXT:    mv t4, t1
1810; RV32I-NEXT:    beq t0, a7, .LBB22_2
1811; RV32I-NEXT:  # %bb.1:
1812; RV32I-NEXT:    sltu t4, t0, a7
1813; RV32I-NEXT:  .LBB22_2:
1814; RV32I-NEXT:    sltu t2, a2, a3
1815; RV32I-NEXT:    mv t3, t2
1816; RV32I-NEXT:    beq a1, a4, .LBB22_4
1817; RV32I-NEXT:  # %bb.3:
1818; RV32I-NEXT:    sltu t3, a1, a4
1819; RV32I-NEXT:  .LBB22_4:
1820; RV32I-NEXT:    xor t5, t0, a7
1821; RV32I-NEXT:    xor t6, a6, a5
1822; RV32I-NEXT:    or t5, t6, t5
1823; RV32I-NEXT:    mv t6, t3
1824; RV32I-NEXT:    beqz t5, .LBB22_6
1825; RV32I-NEXT:  # %bb.5:
1826; RV32I-NEXT:    mv t6, t4
1827; RV32I-NEXT:  .LBB22_6:
1828; RV32I-NEXT:    sltu t4, a3, a2
1829; RV32I-NEXT:    mv t5, t4
1830; RV32I-NEXT:    beq a1, a4, .LBB22_8
1831; RV32I-NEXT:  # %bb.7:
1832; RV32I-NEXT:    sltu t5, a4, a1
1833; RV32I-NEXT:  .LBB22_8:
1834; RV32I-NEXT:    bnez t6, .LBB22_10
1835; RV32I-NEXT:  # %bb.9:
1836; RV32I-NEXT:    sltu t1, a5, a6
1837; RV32I-NEXT:    sub a7, a7, t0
1838; RV32I-NEXT:    sub a5, a5, a6
1839; RV32I-NEXT:    sub a4, a4, a1
1840; RV32I-NEXT:    sub a6, a7, t1
1841; RV32I-NEXT:    sltu a7, a5, t5
1842; RV32I-NEXT:    sub a1, a5, t5
1843; RV32I-NEXT:    sub a5, a4, t4
1844; RV32I-NEXT:    sub a4, a6, a7
1845; RV32I-NEXT:    sub a2, a3, a2
1846; RV32I-NEXT:    j .LBB22_11
1847; RV32I-NEXT:  .LBB22_10:
1848; RV32I-NEXT:    sub a7, t0, a7
1849; RV32I-NEXT:    sub a5, a6, a5
1850; RV32I-NEXT:    sub a4, a1, a4
1851; RV32I-NEXT:    sub a6, a7, t1
1852; RV32I-NEXT:    sltu a7, a5, t3
1853; RV32I-NEXT:    sub a1, a5, t3
1854; RV32I-NEXT:    sub a5, a4, t2
1855; RV32I-NEXT:    sub a4, a6, a7
1856; RV32I-NEXT:    sub a2, a2, a3
1857; RV32I-NEXT:  .LBB22_11:
1858; RV32I-NEXT:    sw a2, 0(a0)
1859; RV32I-NEXT:    sw a5, 4(a0)
1860; RV32I-NEXT:    sw a1, 8(a0)
1861; RV32I-NEXT:    sw a4, 12(a0)
1862; RV32I-NEXT:    ret
1863;
1864; RV64I-LABEL: abd_cmp_i128:
1865; RV64I:       # %bb.0:
1866; RV64I-NEXT:    sltu a4, a0, a2
1867; RV64I-NEXT:    mv a5, a4
1868; RV64I-NEXT:    beq a1, a3, .LBB22_2
1869; RV64I-NEXT:  # %bb.1:
1870; RV64I-NEXT:    sltu a5, a1, a3
1871; RV64I-NEXT:  .LBB22_2:
1872; RV64I-NEXT:    bnez a5, .LBB22_4
1873; RV64I-NEXT:  # %bb.3:
1874; RV64I-NEXT:    sltu a4, a2, a0
1875; RV64I-NEXT:    sub a1, a3, a1
1876; RV64I-NEXT:    sub a1, a1, a4
1877; RV64I-NEXT:    sub a0, a2, a0
1878; RV64I-NEXT:    ret
1879; RV64I-NEXT:  .LBB22_4:
1880; RV64I-NEXT:    sub a1, a1, a3
1881; RV64I-NEXT:    sub a1, a1, a4
1882; RV64I-NEXT:    sub a0, a0, a2
1883; RV64I-NEXT:    ret
1884;
1885; RV32ZBB-LABEL: abd_cmp_i128:
1886; RV32ZBB:       # %bb.0:
1887; RV32ZBB-NEXT:    lw a3, 0(a2)
1888; RV32ZBB-NEXT:    lw a4, 4(a2)
1889; RV32ZBB-NEXT:    lw a5, 8(a2)
1890; RV32ZBB-NEXT:    lw a7, 12(a2)
1891; RV32ZBB-NEXT:    lw a6, 8(a1)
1892; RV32ZBB-NEXT:    lw t0, 12(a1)
1893; RV32ZBB-NEXT:    lw a2, 0(a1)
1894; RV32ZBB-NEXT:    lw a1, 4(a1)
1895; RV32ZBB-NEXT:    sltu t1, a6, a5
1896; RV32ZBB-NEXT:    mv t4, t1
1897; RV32ZBB-NEXT:    beq t0, a7, .LBB22_2
1898; RV32ZBB-NEXT:  # %bb.1:
1899; RV32ZBB-NEXT:    sltu t4, t0, a7
1900; RV32ZBB-NEXT:  .LBB22_2:
1901; RV32ZBB-NEXT:    sltu t2, a2, a3
1902; RV32ZBB-NEXT:    mv t3, t2
1903; RV32ZBB-NEXT:    beq a1, a4, .LBB22_4
1904; RV32ZBB-NEXT:  # %bb.3:
1905; RV32ZBB-NEXT:    sltu t3, a1, a4
1906; RV32ZBB-NEXT:  .LBB22_4:
1907; RV32ZBB-NEXT:    xor t5, t0, a7
1908; RV32ZBB-NEXT:    xor t6, a6, a5
1909; RV32ZBB-NEXT:    or t5, t6, t5
1910; RV32ZBB-NEXT:    mv t6, t3
1911; RV32ZBB-NEXT:    beqz t5, .LBB22_6
1912; RV32ZBB-NEXT:  # %bb.5:
1913; RV32ZBB-NEXT:    mv t6, t4
1914; RV32ZBB-NEXT:  .LBB22_6:
1915; RV32ZBB-NEXT:    sltu t4, a3, a2
1916; RV32ZBB-NEXT:    mv t5, t4
1917; RV32ZBB-NEXT:    beq a1, a4, .LBB22_8
1918; RV32ZBB-NEXT:  # %bb.7:
1919; RV32ZBB-NEXT:    sltu t5, a4, a1
1920; RV32ZBB-NEXT:  .LBB22_8:
1921; RV32ZBB-NEXT:    bnez t6, .LBB22_10
1922; RV32ZBB-NEXT:  # %bb.9:
1923; RV32ZBB-NEXT:    sltu t1, a5, a6
1924; RV32ZBB-NEXT:    sub a7, a7, t0
1925; RV32ZBB-NEXT:    sub a5, a5, a6
1926; RV32ZBB-NEXT:    sub a4, a4, a1
1927; RV32ZBB-NEXT:    sub a6, a7, t1
1928; RV32ZBB-NEXT:    sltu a7, a5, t5
1929; RV32ZBB-NEXT:    sub a1, a5, t5
1930; RV32ZBB-NEXT:    sub a5, a4, t4
1931; RV32ZBB-NEXT:    sub a4, a6, a7
1932; RV32ZBB-NEXT:    sub a2, a3, a2
1933; RV32ZBB-NEXT:    j .LBB22_11
1934; RV32ZBB-NEXT:  .LBB22_10:
1935; RV32ZBB-NEXT:    sub a7, t0, a7
1936; RV32ZBB-NEXT:    sub a5, a6, a5
1937; RV32ZBB-NEXT:    sub a4, a1, a4
1938; RV32ZBB-NEXT:    sub a6, a7, t1
1939; RV32ZBB-NEXT:    sltu a7, a5, t3
1940; RV32ZBB-NEXT:    sub a1, a5, t3
1941; RV32ZBB-NEXT:    sub a5, a4, t2
1942; RV32ZBB-NEXT:    sub a4, a6, a7
1943; RV32ZBB-NEXT:    sub a2, a2, a3
1944; RV32ZBB-NEXT:  .LBB22_11:
1945; RV32ZBB-NEXT:    sw a2, 0(a0)
1946; RV32ZBB-NEXT:    sw a5, 4(a0)
1947; RV32ZBB-NEXT:    sw a1, 8(a0)
1948; RV32ZBB-NEXT:    sw a4, 12(a0)
1949; RV32ZBB-NEXT:    ret
1950;
1951; RV64ZBB-LABEL: abd_cmp_i128:
1952; RV64ZBB:       # %bb.0:
1953; RV64ZBB-NEXT:    sltu a4, a0, a2
1954; RV64ZBB-NEXT:    mv a5, a4
1955; RV64ZBB-NEXT:    beq a1, a3, .LBB22_2
1956; RV64ZBB-NEXT:  # %bb.1:
1957; RV64ZBB-NEXT:    sltu a5, a1, a3
1958; RV64ZBB-NEXT:  .LBB22_2:
1959; RV64ZBB-NEXT:    bnez a5, .LBB22_4
1960; RV64ZBB-NEXT:  # %bb.3:
1961; RV64ZBB-NEXT:    sltu a4, a2, a0
1962; RV64ZBB-NEXT:    sub a1, a3, a1
1963; RV64ZBB-NEXT:    sub a1, a1, a4
1964; RV64ZBB-NEXT:    sub a0, a2, a0
1965; RV64ZBB-NEXT:    ret
1966; RV64ZBB-NEXT:  .LBB22_4:
1967; RV64ZBB-NEXT:    sub a1, a1, a3
1968; RV64ZBB-NEXT:    sub a1, a1, a4
1969; RV64ZBB-NEXT:    sub a0, a0, a2
1970; RV64ZBB-NEXT:    ret
1971  %cmp = icmp ult i128 %a, %b
1972  %ab = sub i128 %a, %b
1973  %ba = sub i128 %b, %a
1974  %sel = select i1 %cmp, i128 %ab, i128 %ba
1975  ret i128 %sel
1976}
1977
1978declare i8 @llvm.abs.i8(i8, i1)
1979declare i16 @llvm.abs.i16(i16, i1)
1980declare i32 @llvm.abs.i32(i32, i1)
1981declare i64 @llvm.abs.i64(i64, i1)
1982declare i128 @llvm.abs.i128(i128, i1)
1983
1984declare i8 @llvm.umax.i8(i8, i8)
1985declare i16 @llvm.umax.i16(i16, i16)
1986declare i32 @llvm.umax.i32(i32, i32)
1987declare i64 @llvm.umax.i64(i64, i64)
1988
1989declare i8 @llvm.umin.i8(i8, i8)
1990declare i16 @llvm.umin.i16(i16, i16)
1991declare i32 @llvm.umin.i32(i32, i32)
1992declare i64 @llvm.umin.i64(i64, i64)
1993