1; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \ 2; RUN: grep -v "Verify generated machine code" | \ 3; RUN: FileCheck %s --check-prefixes=CHECK 4; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \ 5; RUN: grep -v "Verify generated machine code" | \ 6; RUN: FileCheck %s --check-prefixes=CHECK,RV64 7 8; REQUIRES: asserts 9 10; CHECK-LABEL: Pass Arguments: 11; CHECK-NEXT: Target Library Information 12; CHECK-NEXT: Target Pass Configuration 13; CHECK-NEXT: Machine Module Information 14; CHECK-NEXT: Target Transform Information 15; CHECK-NEXT: Assumption Cache Tracker 16; CHECK-NEXT: Profile summary info 17; CHECK-NEXT: Type-Based Alias Analysis 18; CHECK-NEXT: Scoped NoAlias Alias Analysis 19; CHECK-NEXT: Create Garbage Collector Module Metadata 20; CHECK-NEXT: Machine Branch Probability Analysis 21; CHECK-NEXT: Default Regalloc Eviction Advisor 22; CHECK-NEXT: Default Regalloc Priority Advisor 23; CHECK-NEXT: ModulePass Manager 24; CHECK-NEXT: Pre-ISel Intrinsic Lowering 25; CHECK-NEXT: FunctionPass Manager 26; CHECK-NEXT: Expand large div/rem 27; CHECK-NEXT: Expand large fp convert 28; CHECK-NEXT: Expand Atomic instructions 29; CHECK-NEXT: RISC-V Zacas ABI fix 30; CHECK-NEXT: Dominator Tree Construction 31; CHECK-NEXT: Natural Loop Information 32; CHECK-NEXT: Canonicalize natural loops 33; CHECK-NEXT: Lazy Branch Probability Analysis 34; CHECK-NEXT: Lazy Block Frequency Analysis 35; CHECK-NEXT: Optimization Remark Emitter 36; CHECK-NEXT: Scalar Evolution Analysis 37; CHECK-NEXT: Loop Data Prefetch 38; CHECK-NEXT: RISC-V gather/scatter lowering 39; CHECK-NEXT: Interleaved Access Pass 40; CHECK-NEXT: RISC-V CodeGenPrepare 41; CHECK-NEXT: Module Verifier 42; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 43; CHECK-NEXT: Canonicalize natural loops 44; CHECK-NEXT: Scalar Evolution Analysis 45; CHECK-NEXT: Loop Pass Manager 46; CHECK-NEXT: Canonicalize Freeze Instructions in Loops 47; CHECK-NEXT: Induction Variable Users 48; CHECK-NEXT: Loop Strength Reduction 49; CHECK-NEXT: Loop Terminator Folding 50; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 51; CHECK-NEXT: Function Alias Analysis Results 52; CHECK-NEXT: Merge contiguous icmps into a memcmp 53; CHECK-NEXT: Natural Loop Information 54; CHECK-NEXT: Lazy Branch Probability Analysis 55; CHECK-NEXT: Lazy Block Frequency Analysis 56; CHECK-NEXT: Expand memcmp() to load/stores 57; CHECK-NEXT: Lower Garbage Collection Instructions 58; CHECK-NEXT: Shadow Stack GC Lowering 59; CHECK-NEXT: Remove unreachable blocks from the CFG 60; CHECK-NEXT: Natural Loop Information 61; CHECK-NEXT: Post-Dominator Tree Construction 62; CHECK-NEXT: Branch Probability Analysis 63; CHECK-NEXT: Block Frequency Analysis 64; CHECK-NEXT: Constant Hoisting 65; CHECK-NEXT: Replace intrinsics with calls to vector library 66; CHECK-NEXT: Lazy Branch Probability Analysis 67; CHECK-NEXT: Lazy Block Frequency Analysis 68; CHECK-NEXT: Optimization Remark Emitter 69; CHECK-NEXT: Partially inline calls to library functions 70; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining) 71; CHECK-NEXT: Scalarize Masked Memory Intrinsics 72; CHECK-NEXT: Expand reduction intrinsics 73; CHECK-NEXT: Natural Loop Information 74; CHECK-NEXT: Type Promotion 75; CHECK-NEXT: CodeGen Prepare 76; CHECK-NEXT: Dominator Tree Construction 77; CHECK-NEXT: Exception handling preparation 78; CHECK-NEXT: A No-Op Barrier Pass 79; CHECK-NEXT: FunctionPass Manager 80; CHECK-NEXT: Merge internal globals 81; CHECK-NEXT: Dominator Tree Construction 82; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 83; CHECK-NEXT: Function Alias Analysis Results 84; CHECK-NEXT: ObjC ARC contraction 85; CHECK-NEXT: Prepare callbr 86; CHECK-NEXT: Safe Stack instrumentation pass 87; CHECK-NEXT: Insert stack protectors 88; CHECK-NEXT: Module Verifier 89; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 90; CHECK-NEXT: Function Alias Analysis Results 91; CHECK-NEXT: Natural Loop Information 92; CHECK-NEXT: Post-Dominator Tree Construction 93; CHECK-NEXT: Branch Probability Analysis 94; CHECK-NEXT: Assignment Tracking Analysis 95; CHECK-NEXT: Lazy Branch Probability Analysis 96; CHECK-NEXT: Lazy Block Frequency Analysis 97; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection 98; CHECK-NEXT: Finalize ISel and expand pseudo-instructions 99; CHECK-NEXT: RISC-V Vector Peephole Optimization 100; CHECK-NEXT: Lazy Machine Block Frequency Analysis 101; CHECK-NEXT: Early Tail Duplication 102; CHECK-NEXT: Optimize machine instruction PHIs 103; CHECK-NEXT: Slot index numbering 104; CHECK-NEXT: Merge disjoint stack slots 105; CHECK-NEXT: Local Stack Slot Allocation 106; CHECK-NEXT: Remove dead machine instructions 107; CHECK-NEXT: MachineDominator Tree Construction 108; CHECK-NEXT: Machine Natural Loop Construction 109; CHECK-NEXT: Machine Block Frequency Analysis 110; CHECK-NEXT: Early Machine Loop Invariant Code Motion 111; CHECK-NEXT: MachineDominator Tree Construction 112; CHECK-NEXT: Machine Block Frequency Analysis 113; CHECK-NEXT: Machine Common Subexpression Elimination 114; CHECK-NEXT: MachinePostDominator Tree Construction 115; CHECK-NEXT: Machine Cycle Info Analysis 116; CHECK-NEXT: Machine code sinking 117; CHECK-NEXT: Peephole Optimizations 118; CHECK-NEXT: Remove dead machine instructions 119; CHECK-NEXT: Machine Trace Metrics 120; CHECK-NEXT: Lazy Machine Block Frequency Analysis 121; CHECK-NEXT: Machine InstCombiner 122; RV64-NEXT: RISC-V Optimize W Instructions 123; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass 124; CHECK-NEXT: RISC-V Merge Base Offset 125; CHECK-NEXT: MachineDominator Tree Construction 126; CHECK-NEXT: RISC-V VL Optimizer 127; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass 128; CHECK-NEXT: RISC-V Insert Write VXRM Pass 129; CHECK-NEXT: RISC-V Landing Pad Setup 130; CHECK-NEXT: Detect Dead Lanes 131; CHECK-NEXT: Init Undef Pass 132; CHECK-NEXT: Process Implicit Definitions 133; CHECK-NEXT: Remove unreachable machine basic blocks 134; CHECK-NEXT: Live Variable Analysis 135; CHECK-NEXT: Eliminate PHI nodes for register allocation 136; CHECK-NEXT: Two-Address instruction pass 137; CHECK-NEXT: Slot index numbering 138; CHECK-NEXT: Live Interval Analysis 139; CHECK-NEXT: Register Coalescer 140; CHECK-NEXT: Rename Disconnected Subregister Components 141; CHECK-NEXT: Machine Instruction Scheduler 142; CHECK-NEXT: Machine Block Frequency Analysis 143; CHECK-NEXT: Debug Variable Analysis 144; CHECK-NEXT: Live Stack Slot Analysis 145; CHECK-NEXT: Virtual Register Map 146; CHECK-NEXT: Live Register Matrix 147; CHECK-NEXT: Bundle Machine CFG Edges 148; CHECK-NEXT: Spill Code Placement Analysis 149; CHECK-NEXT: Lazy Machine Block Frequency Analysis 150; CHECK-NEXT: Machine Optimization Remark Emitter 151; CHECK-NEXT: Greedy Register Allocator 152; CHECK-NEXT: Virtual Register Rewriter 153; CHECK-NEXT: RISC-V Insert VSETVLI pass 154; CHECK-NEXT: RISC-V Dead register definitions 155; CHECK-NEXT: Virtual Register Map 156; CHECK-NEXT: Live Register Matrix 157; CHECK-NEXT: Greedy Register Allocator 158; CHECK-NEXT: Virtual Register Rewriter 159; CHECK-NEXT: Register Allocation Pass Scoring 160; CHECK-NEXT: Stack Slot Coloring 161; CHECK-NEXT: Machine Copy Propagation Pass 162; CHECK-NEXT: Machine Loop Invariant Code Motion 163; CHECK-NEXT: RISC-V Redundant Copy Elimination 164; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis 165; CHECK-NEXT: Fixup Statepoint Caller Saved 166; CHECK-NEXT: PostRA Machine Sink 167; CHECK-NEXT: MachineDominator Tree Construction 168; CHECK-NEXT: Machine Natural Loop Construction 169; CHECK-NEXT: Machine Block Frequency Analysis 170; CHECK-NEXT: MachinePostDominator Tree Construction 171; CHECK-NEXT: Lazy Machine Block Frequency Analysis 172; CHECK-NEXT: Machine Optimization Remark Emitter 173; CHECK-NEXT: Shrink Wrapping analysis 174; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization 175; CHECK-NEXT: Machine Late Instructions Cleanup Pass 176; CHECK-NEXT: Control Flow Optimizer 177; CHECK-NEXT: Lazy Machine Block Frequency Analysis 178; CHECK-NEXT: Tail Duplication 179; CHECK-NEXT: Machine Copy Propagation Pass 180; CHECK-NEXT: Post-RA pseudo instruction expansion pass 181; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass 182; CHECK-NEXT: Insert KCFI indirect call checks 183; CHECK-NEXT: MachineDominator Tree Construction 184; CHECK-NEXT: Machine Natural Loop Construction 185; CHECK-NEXT: PostRA Machine Instruction Scheduler 186; CHECK-NEXT: Analyze Machine Code For Garbage Collection 187; CHECK-NEXT: Machine Block Frequency Analysis 188; CHECK-NEXT: MachinePostDominator Tree Construction 189; CHECK-NEXT: Branch Probability Basic Block Placement 190; CHECK-NEXT: Insert fentry calls 191; CHECK-NEXT: Insert XRay ops 192; CHECK-NEXT: Implement the 'patchable-function' attribute 193; CHECK-NEXT: Machine Copy Propagation Pass 194; CHECK-NEXT: Branch relaxation pass 195; CHECK-NEXT: RISC-V Make Compressible 196; CHECK-NEXT: Contiguously Lay Out Funclets 197; CHECK-NEXT: Remove Loads Into Fake Uses 198; CHECK-NEXT: StackMap Liveness Analysis 199; CHECK-NEXT: Live DEBUG_VALUE analysis 200; CHECK-NEXT: Machine Sanitizer Binary Metadata 201; CHECK-NEXT: Machine Outliner 202; CHECK-NEXT: FunctionPass Manager 203; CHECK-NEXT: Insert CFI remember/restore state instructions 204; CHECK-NEXT: Lazy Machine Block Frequency Analysis 205; CHECK-NEXT: Machine Optimization Remark Emitter 206; CHECK-NEXT: Stack Frame Layout Analysis 207; CHECK-NEXT: RISC-V Zcmp move merging pass 208; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass 209; CHECK-NEXT: RISC-V Indirect Branch Tracking 210; CHECK-NEXT: RISC-V pseudo instruction expansion pass 211; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass 212; CHECK-NEXT: Unpack machine instruction bundles 213; CHECK-NEXT: Lazy Machine Block Frequency Analysis 214; CHECK-NEXT: Machine Optimization Remark Emitter 215; CHECK-NEXT: RISC-V Assembly Printer 216; CHECK-NEXT: Free MachineFunction 217