1; RUN: llc -mtriple=riscv32 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \ 2; RUN: grep -v "Verify generated machine code" | \ 3; RUN: FileCheck %s --check-prefixes=CHECK 4; RUN: llc -mtriple=riscv64 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \ 5; RUN: grep -v "Verify generated machine code" | \ 6; RUN: FileCheck %s --check-prefixes=CHECK 7 8; REQUIRES: asserts 9 10; CHECK-LABEL: Pass Arguments: 11; CHECK-NEXT: Target Library Information 12; CHECK-NEXT: Target Pass Configuration 13; CHECK-NEXT: Machine Module Information 14; CHECK-NEXT: Target Transform Information 15; CHECK-NEXT: Create Garbage Collector Module Metadata 16; CHECK-NEXT: Assumption Cache Tracker 17; CHECK-NEXT: Profile summary info 18; CHECK-NEXT: Machine Branch Probability Analysis 19; CHECK-NEXT: ModulePass Manager 20; CHECK-NEXT: Pre-ISel Intrinsic Lowering 21; CHECK-NEXT: FunctionPass Manager 22; CHECK-NEXT: Expand large div/rem 23; CHECK-NEXT: Expand large fp convert 24; CHECK-NEXT: Expand Atomic instructions 25; CHECK-NEXT: RISC-V Zacas ABI fix 26; CHECK-NEXT: Module Verifier 27; CHECK-NEXT: Lower Garbage Collection Instructions 28; CHECK-NEXT: Shadow Stack GC Lowering 29; CHECK-NEXT: Remove unreachable blocks from the CFG 30; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining) 31; CHECK-NEXT: Scalarize Masked Memory Intrinsics 32; CHECK-NEXT: Expand reduction intrinsics 33; CHECK-NEXT: Exception handling preparation 34; CHECK-NEXT: Prepare callbr 35; CHECK-NEXT: Safe Stack instrumentation pass 36; CHECK-NEXT: Insert stack protectors 37; CHECK-NEXT: Module Verifier 38; CHECK-NEXT: Assignment Tracking Analysis 39; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection 40; CHECK-NEXT: Finalize ISel and expand pseudo-instructions 41; CHECK-NEXT: Local Stack Slot Allocation 42; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass 43; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass 44; CHECK-NEXT: RISC-V Insert Write VXRM Pass 45; CHECK-NEXT: RISC-V Landing Pad Setup 46; CHECK-NEXT: Init Undef Pass 47; CHECK-NEXT: Eliminate PHI nodes for register allocation 48; CHECK-NEXT: Two-Address instruction pass 49; CHECK-NEXT: Fast Register Allocator 50; CHECK-NEXT: RISC-V Insert VSETVLI pass 51; CHECK-NEXT: Fast Register Allocator 52; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis 53; CHECK-NEXT: Fixup Statepoint Caller Saved 54; CHECK-NEXT: Lazy Machine Block Frequency Analysis 55; CHECK-NEXT: Machine Optimization Remark Emitter 56; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization 57; CHECK-NEXT: Post-RA pseudo instruction expansion pass 58; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass 59; CHECK-NEXT: Insert KCFI indirect call checks 60; CHECK-NEXT: Analyze Machine Code For Garbage Collection 61; CHECK-NEXT: Insert fentry calls 62; CHECK-NEXT: Insert XRay ops 63; CHECK-NEXT: Implement the 'patchable-function' attribute 64; CHECK-NEXT: Branch relaxation pass 65; CHECK-NEXT: RISC-V Make Compressible 66; CHECK-NEXT: Contiguously Lay Out Funclets 67; CHECK-NEXT: Remove Loads Into Fake Uses 68; CHECK-NEXT: StackMap Liveness Analysis 69; CHECK-NEXT: Live DEBUG_VALUE analysis 70; CHECK-NEXT: Machine Sanitizer Binary Metadata 71; CHECK-NEXT: Insert CFI remember/restore state instructions 72; CHECK-NEXT: Lazy Machine Block Frequency Analysis 73; CHECK-NEXT: Machine Optimization Remark Emitter 74; CHECK-NEXT: Stack Frame Layout Analysis 75; CHECK-NEXT: RISC-V Indirect Branch Tracking 76; CHECK-NEXT: RISC-V pseudo instruction expansion pass 77; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass 78; CHECK-NEXT: Unpack machine instruction bundles 79; CHECK-NEXT: Lazy Machine Block Frequency Analysis 80; CHECK-NEXT: Machine Optimization Remark Emitter 81; CHECK-NEXT: RISC-V Assembly Printer 82; CHECK-NEXT: Free MachineFunction 83