xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll (revision dde5546b79f784ab71cac325e0a0698c67c4dcde) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I
3; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I
4
5define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
6; RV32I-LABEL: ucmp.8.8:
7; RV32I:       # %bb.0:
8; RV32I-NEXT:    sltu a2, a1, a0
9; RV32I-NEXT:    sltu a0, a0, a1
10; RV32I-NEXT:    sub a0, a2, a0
11; RV32I-NEXT:    ret
12;
13; RV64I-LABEL: ucmp.8.8:
14; RV64I:       # %bb.0:
15; RV64I-NEXT:    sltu a2, a1, a0
16; RV64I-NEXT:    sltu a0, a0, a1
17; RV64I-NEXT:    sub a0, a2, a0
18; RV64I-NEXT:    ret
19  %1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
20  ret i8 %1
21}
22
23define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
24; RV32I-LABEL: ucmp.8.16:
25; RV32I:       # %bb.0:
26; RV32I-NEXT:    sltu a2, a1, a0
27; RV32I-NEXT:    sltu a0, a0, a1
28; RV32I-NEXT:    sub a0, a2, a0
29; RV32I-NEXT:    ret
30;
31; RV64I-LABEL: ucmp.8.16:
32; RV64I:       # %bb.0:
33; RV64I-NEXT:    sltu a2, a1, a0
34; RV64I-NEXT:    sltu a0, a0, a1
35; RV64I-NEXT:    sub a0, a2, a0
36; RV64I-NEXT:    ret
37  %1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
38  ret i8 %1
39}
40
41define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
42; RV32I-LABEL: ucmp.8.32:
43; RV32I:       # %bb.0:
44; RV32I-NEXT:    sltu a2, a1, a0
45; RV32I-NEXT:    sltu a0, a0, a1
46; RV32I-NEXT:    sub a0, a2, a0
47; RV32I-NEXT:    ret
48;
49; RV64I-LABEL: ucmp.8.32:
50; RV64I:       # %bb.0:
51; RV64I-NEXT:    sext.w a0, a0
52; RV64I-NEXT:    sext.w a1, a1
53; RV64I-NEXT:    sltu a2, a1, a0
54; RV64I-NEXT:    sltu a0, a0, a1
55; RV64I-NEXT:    sub a0, a2, a0
56; RV64I-NEXT:    ret
57  %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
58  ret i8 %1
59}
60
61define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
62; RV32I-LABEL: ucmp.8.64:
63; RV32I:       # %bb.0:
64; RV32I-NEXT:    beq a1, a3, .LBB3_2
65; RV32I-NEXT:  # %bb.1:
66; RV32I-NEXT:    sltu a4, a3, a1
67; RV32I-NEXT:    sltu a0, a1, a3
68; RV32I-NEXT:    sub a0, a4, a0
69; RV32I-NEXT:    ret
70; RV32I-NEXT:  .LBB3_2:
71; RV32I-NEXT:    sltu a4, a2, a0
72; RV32I-NEXT:    sltu a0, a0, a2
73; RV32I-NEXT:    sub a0, a4, a0
74; RV32I-NEXT:    ret
75;
76; RV64I-LABEL: ucmp.8.64:
77; RV64I:       # %bb.0:
78; RV64I-NEXT:    sltu a2, a1, a0
79; RV64I-NEXT:    sltu a0, a0, a1
80; RV64I-NEXT:    sub a0, a2, a0
81; RV64I-NEXT:    ret
82  %1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
83  ret i8 %1
84}
85
86define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
87; RV32I-LABEL: ucmp.32.32:
88; RV32I:       # %bb.0:
89; RV32I-NEXT:    sltu a2, a1, a0
90; RV32I-NEXT:    sltu a0, a0, a1
91; RV32I-NEXT:    sub a0, a2, a0
92; RV32I-NEXT:    ret
93;
94; RV64I-LABEL: ucmp.32.32:
95; RV64I:       # %bb.0:
96; RV64I-NEXT:    sext.w a0, a0
97; RV64I-NEXT:    sext.w a1, a1
98; RV64I-NEXT:    sltu a2, a1, a0
99; RV64I-NEXT:    sltu a0, a0, a1
100; RV64I-NEXT:    subw a0, a2, a0
101; RV64I-NEXT:    ret
102  %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
103  ret i32 %1
104}
105
106define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
107; RV32I-LABEL: ucmp.32.32_sext:
108; RV32I:       # %bb.0:
109; RV32I-NEXT:    sltu a2, a1, a0
110; RV32I-NEXT:    sltu a0, a0, a1
111; RV32I-NEXT:    sub a0, a2, a0
112; RV32I-NEXT:    ret
113;
114; RV64I-LABEL: ucmp.32.32_sext:
115; RV64I:       # %bb.0:
116; RV64I-NEXT:    sltu a2, a1, a0
117; RV64I-NEXT:    sltu a0, a0, a1
118; RV64I-NEXT:    subw a0, a2, a0
119; RV64I-NEXT:    ret
120  %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
121  ret i32 %1
122}
123
124define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {
125; RV32I-LABEL: ucmp.32.32_zext:
126; RV32I:       # %bb.0:
127; RV32I-NEXT:    sltu a2, a1, a0
128; RV32I-NEXT:    sltu a0, a0, a1
129; RV32I-NEXT:    sub a0, a2, a0
130; RV32I-NEXT:    ret
131;
132; RV64I-LABEL: ucmp.32.32_zext:
133; RV64I:       # %bb.0:
134; RV64I-NEXT:    sext.w a0, a0
135; RV64I-NEXT:    sext.w a1, a1
136; RV64I-NEXT:    sltu a2, a1, a0
137; RV64I-NEXT:    sltu a0, a0, a1
138; RV64I-NEXT:    subw a0, a2, a0
139; RV64I-NEXT:    ret
140  %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
141  ret i32 %1
142}
143
144define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
145; RV32I-LABEL: ucmp.32.64:
146; RV32I:       # %bb.0:
147; RV32I-NEXT:    beq a1, a3, .LBB7_2
148; RV32I-NEXT:  # %bb.1:
149; RV32I-NEXT:    sltu a4, a3, a1
150; RV32I-NEXT:    sltu a0, a1, a3
151; RV32I-NEXT:    sub a0, a4, a0
152; RV32I-NEXT:    ret
153; RV32I-NEXT:  .LBB7_2:
154; RV32I-NEXT:    sltu a4, a2, a0
155; RV32I-NEXT:    sltu a0, a0, a2
156; RV32I-NEXT:    sub a0, a4, a0
157; RV32I-NEXT:    ret
158;
159; RV64I-LABEL: ucmp.32.64:
160; RV64I:       # %bb.0:
161; RV64I-NEXT:    sltu a2, a1, a0
162; RV64I-NEXT:    sltu a0, a0, a1
163; RV64I-NEXT:    subw a0, a2, a0
164; RV64I-NEXT:    ret
165  %1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
166  ret i32 %1
167}
168
169define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
170; RV32I-LABEL: ucmp.64.64:
171; RV32I:       # %bb.0:
172; RV32I-NEXT:    beq a1, a3, .LBB8_2
173; RV32I-NEXT:  # %bb.1:
174; RV32I-NEXT:    sltu a4, a3, a1
175; RV32I-NEXT:    sltu a1, a1, a3
176; RV32I-NEXT:    j .LBB8_3
177; RV32I-NEXT:  .LBB8_2:
178; RV32I-NEXT:    sltu a4, a2, a0
179; RV32I-NEXT:    sltu a1, a0, a2
180; RV32I-NEXT:  .LBB8_3:
181; RV32I-NEXT:    sub a0, a4, a1
182; RV32I-NEXT:    sltu a1, a4, a1
183; RV32I-NEXT:    neg a1, a1
184; RV32I-NEXT:    ret
185;
186; RV64I-LABEL: ucmp.64.64:
187; RV64I:       # %bb.0:
188; RV64I-NEXT:    sltu a2, a1, a0
189; RV64I-NEXT:    sltu a0, a0, a1
190; RV64I-NEXT:    sub a0, a2, a0
191; RV64I-NEXT:    ret
192  %1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
193  ret i64 %1
194}
195