1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s --check-prefix=RV32 4; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s --check-prefix=RV64 6 7define float @test_f32(float %x, float %y) nounwind { 8; RV32-LABEL: test_f32: 9; RV32: # %bb.0: # %entry 10; RV32-NEXT: addi sp, sp, -16 11; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 12; RV32-NEXT: call fmodf 13; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 14; RV32-NEXT: addi sp, sp, 16 15; RV32-NEXT: ret 16; 17; RV64-LABEL: test_f32: 18; RV64: # %bb.0: # %entry 19; RV64-NEXT: addi sp, sp, -16 20; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 21; RV64-NEXT: call fmodf 22; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 23; RV64-NEXT: addi sp, sp, 16 24; RV64-NEXT: ret 25entry: 26 %z = frem float %x, %y 27 ret float %z 28} 29 30define double @test_f64(double %x, double %y) nounwind { 31; RV32-LABEL: test_f64: 32; RV32: # %bb.0: # %entry 33; RV32-NEXT: addi sp, sp, -16 34; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 35; RV32-NEXT: call fmod 36; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 37; RV32-NEXT: addi sp, sp, 16 38; RV32-NEXT: ret 39; 40; RV64-LABEL: test_f64: 41; RV64: # %bb.0: # %entry 42; RV64-NEXT: addi sp, sp, -16 43; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 44; RV64-NEXT: call fmod 45; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 46; RV64-NEXT: addi sp, sp, 16 47; RV64-NEXT: ret 48entry: 49 %z = frem double %x, %y 50 ret double %z 51} 52