1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK 3; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK 4 5define void @add_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 6 ; CHECK-LABEL: name: add_nxv2i32 7 ; CHECK: bb.1 (%ir-block.0): 8 ; CHECK-NEXT: liveins: $v8, $v9 9 ; CHECK-NEXT: {{ $}} 10 ; CHECK-NEXT: PseudoRET 11 %c = add <vscale x 2 x i32> %a, %b 12 ret void 13} 14 15define void @sub_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 16 ; CHECK-LABEL: name: sub_nxv2i32 17 ; CHECK: bb.1 (%ir-block.0): 18 ; CHECK-NEXT: liveins: $v8, $v9 19 ; CHECK-NEXT: {{ $}} 20 ; CHECK-NEXT: PseudoRET 21 %c = sub <vscale x 2 x i32> %a, %b 22 ret void 23} 24 25define void @and_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 26 ; CHECK-LABEL: name: and_nxv2i32 27 ; CHECK: bb.1 (%ir-block.0): 28 ; CHECK-NEXT: liveins: $v8, $v9 29 ; CHECK-NEXT: {{ $}} 30 ; CHECK-NEXT: PseudoRET 31 %c = and <vscale x 2 x i32> %a, %b 32 ret void 33} 34 35define void @or_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 36 ; CHECK-LABEL: name: or_nxv2i32 37 ; CHECK: bb.1 (%ir-block.0): 38 ; CHECK-NEXT: liveins: $v8, $v9 39 ; CHECK-NEXT: {{ $}} 40 ; CHECK-NEXT: PseudoRET 41 %c = or <vscale x 2 x i32> %a, %b 42 ret void 43} 44 45define void @xor_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 46 ; CHECK-LABEL: name: xor_nxv2i32 47 ; CHECK: bb.1 (%ir-block.0): 48 ; CHECK-NEXT: liveins: $v8, $v9 49 ; CHECK-NEXT: {{ $}} 50 ; CHECK-NEXT: PseudoRET 51 %c = xor <vscale x 2 x i32> %a, %b 52 ret void 53} 54