xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll (revision 3a38baa0e730b53ed70cfdb68fd87813eaa40ede)
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64I %s
6
7declare void @llvm.va_copy(ptr, ptr)
8define void @test_va_copy(ptr %dest_list, ptr %src_list) {
9  ; RV32I-LABEL: name: test_va_copy
10  ; RV32I: bb.1 (%ir-block.0):
11  ; RV32I-NEXT:   liveins: $x10, $x11
12  ; RV32I-NEXT: {{  $}}
13  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
14  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
15  ; RV32I-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[COPY]](p0), [[COPY1]](p0)
16  ; RV32I-NEXT:   PseudoRET
17  ;
18  ; RV64I-LABEL: name: test_va_copy
19  ; RV64I: bb.1 (%ir-block.0):
20  ; RV64I-NEXT:   liveins: $x10, $x11
21  ; RV64I-NEXT: {{  $}}
22  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
23  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
24  ; RV64I-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[COPY]](p0), [[COPY1]](p0)
25  ; RV64I-NEXT:   PseudoRET
26  call void @llvm.va_copy(ptr %dest_list, ptr %src_list)
27  ret void
28}
29