1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \ 3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s 4; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \ 5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s 6 7define <vscale x 1 x i1> @insertelement_nxv1i1_0() { 8 ; RV32-LABEL: name: insertelement_nxv1i1_0 9 ; RV32: bb.1 (%ir-block.0): 10 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF 11 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 12 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 13 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 14 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) 15 ; RV32-NEXT: PseudoRET implicit $v0 16 ; 17 ; RV64-LABEL: name: insertelement_nxv1i1_0 18 ; RV64: bb.1 (%ir-block.0): 19 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF 20 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 21 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 22 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 23 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) 24 ; RV64-NEXT: PseudoRET implicit $v0 25 %a = insertelement <vscale x 1 x i1> poison, i1 0, i32 0 26 ret <vscale x 1 x i1> %a 27} 28 29define <vscale x 1 x i1> @insertelement_nxv1i1_1() { 30 ; RV32-LABEL: name: insertelement_nxv1i1_1 31 ; RV32: bb.1 (%ir-block.0): 32 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF 33 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 34 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 35 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 36 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) 37 ; RV32-NEXT: PseudoRET implicit $v0 38 ; 39 ; RV64-LABEL: name: insertelement_nxv1i1_1 40 ; RV64: bb.1 (%ir-block.0): 41 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF 42 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 43 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 44 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 45 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) 46 ; RV64-NEXT: PseudoRET implicit $v0 47 %a = insertelement <vscale x 1 x i1> poison, i1 -1, i32 0 48 ret <vscale x 1 x i1> %a 49} 50 51define <vscale x 1 x i1> @insertelement_nxv1i1_2(i1 %x, i32 %idx) { 52 ; RV32-LABEL: name: insertelement_nxv1i1_2 53 ; RV32: bb.1 (%ir-block.0): 54 ; RV32-NEXT: liveins: $x10, $x11 55 ; RV32-NEXT: {{ $}} 56 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 57 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 58 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 59 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF 60 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) 61 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) 62 ; RV32-NEXT: PseudoRET implicit $v0 63 ; 64 ; RV64-LABEL: name: insertelement_nxv1i1_2 65 ; RV64: bb.1 (%ir-block.0): 66 ; RV64-NEXT: liveins: $x10, $x11 67 ; RV64-NEXT: {{ $}} 68 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 69 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) 70 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 71 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) 72 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF 73 ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) 74 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) 75 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) 76 ; RV64-NEXT: PseudoRET implicit $v0 77 %a = insertelement <vscale x 1 x i1> poison, i1 %x, i32 %idx 78 ret <vscale x 1 x i1> %a 79} 80 81define <vscale x 2 x i1> @insertelement_nxv2i1_0() { 82 ; RV32-LABEL: name: insertelement_nxv2i1_0 83 ; RV32: bb.1 (%ir-block.0): 84 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF 85 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 86 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 87 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 88 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) 89 ; RV32-NEXT: PseudoRET implicit $v0 90 ; 91 ; RV64-LABEL: name: insertelement_nxv2i1_0 92 ; RV64: bb.1 (%ir-block.0): 93 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF 94 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 95 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 96 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 97 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) 98 ; RV64-NEXT: PseudoRET implicit $v0 99 %a = insertelement <vscale x 2 x i1> poison, i1 0, i32 1 100 ret <vscale x 2 x i1> %a 101} 102 103define <vscale x 2 x i1> @insertelement_nxv2i1_1() { 104 ; RV32-LABEL: name: insertelement_nxv2i1_1 105 ; RV32: bb.1 (%ir-block.0): 106 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF 107 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 108 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 109 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 110 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) 111 ; RV32-NEXT: PseudoRET implicit $v0 112 ; 113 ; RV64-LABEL: name: insertelement_nxv2i1_1 114 ; RV64: bb.1 (%ir-block.0): 115 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF 116 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 117 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 118 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 119 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) 120 ; RV64-NEXT: PseudoRET implicit $v0 121 %a = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0 122 ret <vscale x 2 x i1> %a 123} 124 125define <vscale x 2 x i1> @insertelement_nxv2i1_2(i1 %x, i32 %idx) { 126 ; RV32-LABEL: name: insertelement_nxv2i1_2 127 ; RV32: bb.1 (%ir-block.0): 128 ; RV32-NEXT: liveins: $x10, $x11 129 ; RV32-NEXT: {{ $}} 130 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 131 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 132 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 133 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF 134 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) 135 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) 136 ; RV32-NEXT: PseudoRET implicit $v0 137 ; 138 ; RV64-LABEL: name: insertelement_nxv2i1_2 139 ; RV64: bb.1 (%ir-block.0): 140 ; RV64-NEXT: liveins: $x10, $x11 141 ; RV64-NEXT: {{ $}} 142 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 143 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) 144 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 145 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) 146 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF 147 ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) 148 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) 149 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) 150 ; RV64-NEXT: PseudoRET implicit $v0 151 %a = insertelement <vscale x 2 x i1> poison, i1 %x, i32 %idx 152 ret <vscale x 2 x i1> %a 153} 154 155define <vscale x 4 x i1> @insertelement_nxv4i1_0() { 156 ; RV32-LABEL: name: insertelement_nxv4i1_0 157 ; RV32: bb.1 (%ir-block.0): 158 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF 159 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 160 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 161 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 162 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 163 ; RV32-NEXT: PseudoRET implicit $v0 164 ; 165 ; RV64-LABEL: name: insertelement_nxv4i1_0 166 ; RV64: bb.1 (%ir-block.0): 167 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF 168 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 169 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 170 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 171 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 172 ; RV64-NEXT: PseudoRET implicit $v0 173 %a = insertelement <vscale x 4 x i1> poison, i1 0, i32 2 174 ret <vscale x 4 x i1> %a 175} 176 177define <vscale x 4 x i1> @insertelement_nxv4i1_1() { 178 ; RV32-LABEL: name: insertelement_nxv4i1_1 179 ; RV32: bb.1 (%ir-block.0): 180 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF 181 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 182 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 183 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 184 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 185 ; RV32-NEXT: PseudoRET implicit $v0 186 ; 187 ; RV64-LABEL: name: insertelement_nxv4i1_1 188 ; RV64: bb.1 (%ir-block.0): 189 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF 190 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 191 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 192 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 193 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 194 ; RV64-NEXT: PseudoRET implicit $v0 195 %a = insertelement <vscale x 4 x i1> poison, i1 -1, i32 0 196 ret <vscale x 4 x i1> %a 197} 198 199define <vscale x 4 x i1> @insertelement_nxv4i1_2(i1 %x) { 200 ; RV32-LABEL: name: insertelement_nxv4i1_2 201 ; RV32: bb.1 (%ir-block.0): 202 ; RV32-NEXT: liveins: $x10 203 ; RV32-NEXT: {{ $}} 204 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 205 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 206 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF 207 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 208 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32) 209 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 210 ; RV32-NEXT: PseudoRET implicit $v0 211 ; 212 ; RV64-LABEL: name: insertelement_nxv4i1_2 213 ; RV64: bb.1 (%ir-block.0): 214 ; RV64-NEXT: liveins: $x10 215 ; RV64-NEXT: {{ $}} 216 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 217 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) 218 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF 219 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 220 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s64) 221 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 222 ; RV64-NEXT: PseudoRET implicit $v0 223 %a = insertelement <vscale x 4 x i1> poison, i1 %x, i32 0 224 ret <vscale x 4 x i1> %a 225} 226 227define <vscale x 8 x i1> @insertelement_nxv8i1_0() { 228 ; RV32-LABEL: name: insertelement_nxv8i1_0 229 ; RV32: bb.1 (%ir-block.0): 230 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF 231 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 232 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 233 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 234 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) 235 ; RV32-NEXT: PseudoRET implicit $v0 236 ; 237 ; RV64-LABEL: name: insertelement_nxv8i1_0 238 ; RV64: bb.1 (%ir-block.0): 239 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF 240 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 241 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 242 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 243 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) 244 ; RV64-NEXT: PseudoRET implicit $v0 245 %a = insertelement <vscale x 8 x i1> poison, i1 0, i32 0 246 ret <vscale x 8 x i1> %a 247} 248 249define <vscale x 8 x i1> @insertelement_nxv8i1_1() { 250 ; RV32-LABEL: name: insertelement_nxv8i1_1 251 ; RV32: bb.1 (%ir-block.0): 252 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF 253 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 254 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 255 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 256 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) 257 ; RV32-NEXT: PseudoRET implicit $v0 258 ; 259 ; RV64-LABEL: name: insertelement_nxv8i1_1 260 ; RV64: bb.1 (%ir-block.0): 261 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF 262 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 263 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 264 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 265 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) 266 ; RV64-NEXT: PseudoRET implicit $v0 267 %a = insertelement <vscale x 8 x i1> poison, i1 -1, i32 0 268 ret <vscale x 8 x i1> %a 269} 270 271define <vscale x 8 x i1> @insertelement_nxv8i1_2(i1 %x, i32 %idx) { 272 ; RV32-LABEL: name: insertelement_nxv8i1_2 273 ; RV32: bb.1 (%ir-block.0): 274 ; RV32-NEXT: liveins: $x10, $x11 275 ; RV32-NEXT: {{ $}} 276 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 277 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 278 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 279 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF 280 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) 281 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) 282 ; RV32-NEXT: PseudoRET implicit $v0 283 ; 284 ; RV64-LABEL: name: insertelement_nxv8i1_2 285 ; RV64: bb.1 (%ir-block.0): 286 ; RV64-NEXT: liveins: $x10, $x11 287 ; RV64-NEXT: {{ $}} 288 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 289 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) 290 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 291 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) 292 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF 293 ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) 294 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) 295 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) 296 ; RV64-NEXT: PseudoRET implicit $v0 297 %a = insertelement <vscale x 8 x i1> poison, i1 %x, i32 %idx 298 ret <vscale x 8 x i1> %a 299} 300 301define <vscale x 16 x i1> @insertelement_nxv16i1_0() { 302 ; RV32-LABEL: name: insertelement_nxv16i1_0 303 ; RV32: bb.1 (%ir-block.0): 304 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF 305 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 306 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 307 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 308 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) 309 ; RV32-NEXT: PseudoRET implicit $v0 310 ; 311 ; RV64-LABEL: name: insertelement_nxv16i1_0 312 ; RV64: bb.1 (%ir-block.0): 313 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF 314 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false 315 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 316 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 317 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) 318 ; RV64-NEXT: PseudoRET implicit $v0 319 %a = insertelement <vscale x 16 x i1> poison, i1 0, i32 15 320 ret <vscale x 16 x i1> %a 321} 322 323define <vscale x 16 x i1> @insertelement_nxv16i1_1() { 324 ; RV32-LABEL: name: insertelement_nxv16i1_1 325 ; RV32: bb.1 (%ir-block.0): 326 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF 327 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 328 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 329 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) 330 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) 331 ; RV32-NEXT: PseudoRET implicit $v0 332 ; 333 ; RV64-LABEL: name: insertelement_nxv16i1_1 334 ; RV64: bb.1 (%ir-block.0): 335 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF 336 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 337 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 338 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) 339 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) 340 ; RV64-NEXT: PseudoRET implicit $v0 341 %a = insertelement <vscale x 16 x i1> poison, i1 -1, i32 0 342 ret <vscale x 16 x i1> %a 343} 344 345define <vscale x 16 x i1> @insertelement_nxv16i1_2(i1 %x, i32 %idx) { 346 ; RV32-LABEL: name: insertelement_nxv16i1_2 347 ; RV32: bb.1 (%ir-block.0): 348 ; RV32-NEXT: liveins: $x10, $x11 349 ; RV32-NEXT: {{ $}} 350 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 351 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 352 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 353 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF 354 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) 355 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) 356 ; RV32-NEXT: PseudoRET implicit $v0 357 ; 358 ; RV64-LABEL: name: insertelement_nxv16i1_2 359 ; RV64: bb.1 (%ir-block.0): 360 ; RV64-NEXT: liveins: $x10, $x11 361 ; RV64-NEXT: {{ $}} 362 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 363 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) 364 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 365 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) 366 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF 367 ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) 368 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) 369 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) 370 ; RV64-NEXT: PseudoRET implicit $v0 371 %a = insertelement <vscale x 16 x i1> poison, i1 %x, i32 %idx 372 ret <vscale x 16 x i1> %a 373} 374 375define <vscale x 4 x i1> @insertelement_nxv4i1_3(<vscale x 4 x i1> %v, i1 %x) { 376 ; RV32-LABEL: name: insertelement_nxv4i1_3 377 ; RV32: bb.1 (%ir-block.0): 378 ; RV32-NEXT: liveins: $v0, $x10 379 ; RV32-NEXT: {{ $}} 380 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 381 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 382 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32) 383 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 384 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s32) 385 ; RV32-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 386 ; RV32-NEXT: PseudoRET implicit $v0 387 ; 388 ; RV64-LABEL: name: insertelement_nxv4i1_3 389 ; RV64: bb.1 (%ir-block.0): 390 ; RV64-NEXT: liveins: $v0, $x10 391 ; RV64-NEXT: {{ $}} 392 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 393 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 394 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s64) 395 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 396 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s64) 397 ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) 398 ; RV64-NEXT: PseudoRET implicit $v0 399 %a = insertelement <vscale x 4 x i1> %v, i1 %x, i32 0 400 ret <vscale x 4 x i1> %a 401} 402 403define <vscale x 1 x i8> @insertelement_nxv1i8_0() { 404 ; RV32-LABEL: name: insertelement_nxv1i8_0 405 ; RV32: bb.1 (%ir-block.0): 406 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF 407 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 408 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 409 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 410 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) 411 ; RV32-NEXT: PseudoRET implicit $v8 412 ; 413 ; RV64-LABEL: name: insertelement_nxv1i8_0 414 ; RV64: bb.1 (%ir-block.0): 415 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF 416 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 417 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 418 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 419 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) 420 ; RV64-NEXT: PseudoRET implicit $v8 421 %a = insertelement <vscale x 1 x i8> poison, i8 0, i32 0 422 ret <vscale x 1 x i8> %a 423} 424 425define <vscale x 1 x i8> @insertelement_nxv1i8_1() { 426 ; RV32-LABEL: name: insertelement_nxv1i8_1 427 ; RV32: bb.1 (%ir-block.0): 428 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF 429 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 430 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 431 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 432 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) 433 ; RV32-NEXT: PseudoRET implicit $v8 434 ; 435 ; RV64-LABEL: name: insertelement_nxv1i8_1 436 ; RV64: bb.1 (%ir-block.0): 437 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF 438 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 439 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 440 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 441 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) 442 ; RV64-NEXT: PseudoRET implicit $v8 443 %a = insertelement <vscale x 1 x i8> poison, i8 -1, i32 0 444 ret <vscale x 1 x i8> %a 445} 446 447define <vscale x 1 x i8> @insertelement_nxv1i8_2(i8 %x) { 448 ; RV32-LABEL: name: insertelement_nxv1i8_2 449 ; RV32: bb.1 (%ir-block.0): 450 ; RV32-NEXT: liveins: $x10 451 ; RV32-NEXT: {{ $}} 452 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 453 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 454 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF 455 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 456 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) 457 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) 458 ; RV32-NEXT: PseudoRET implicit $v8 459 ; 460 ; RV64-LABEL: name: insertelement_nxv1i8_2 461 ; RV64: bb.1 (%ir-block.0): 462 ; RV64-NEXT: liveins: $x10 463 ; RV64-NEXT: {{ $}} 464 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 465 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) 466 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF 467 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 468 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) 469 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) 470 ; RV64-NEXT: PseudoRET implicit $v8 471 %a = insertelement <vscale x 1 x i8> poison, i8 %x, i32 0 472 ret <vscale x 1 x i8> %a 473} 474 475define <vscale x 2 x i8> @insertelement_nxv2i8_0() { 476 ; RV32-LABEL: name: insertelement_nxv2i8_0 477 ; RV32: bb.1 (%ir-block.0): 478 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF 479 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 480 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 481 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 482 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) 483 ; RV32-NEXT: PseudoRET implicit $v8 484 ; 485 ; RV64-LABEL: name: insertelement_nxv2i8_0 486 ; RV64: bb.1 (%ir-block.0): 487 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF 488 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 489 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 490 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 491 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) 492 ; RV64-NEXT: PseudoRET implicit $v8 493 %a = insertelement <vscale x 2 x i8> poison, i8 0, i32 0 494 ret <vscale x 2 x i8> %a 495} 496 497define <vscale x 2 x i8> @insertelement_nxv2i8_1() { 498 ; RV32-LABEL: name: insertelement_nxv2i8_1 499 ; RV32: bb.1 (%ir-block.0): 500 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF 501 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 502 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 503 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 504 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) 505 ; RV32-NEXT: PseudoRET implicit $v8 506 ; 507 ; RV64-LABEL: name: insertelement_nxv2i8_1 508 ; RV64: bb.1 (%ir-block.0): 509 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF 510 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 511 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 512 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 513 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) 514 ; RV64-NEXT: PseudoRET implicit $v8 515 %a = insertelement <vscale x 2 x i8> poison, i8 -1, i32 0 516 ret <vscale x 2 x i8> %a 517} 518 519define <vscale x 2 x i8> @insertelement_nxv2i8_2(i8 %x) { 520 ; RV32-LABEL: name: insertelement_nxv2i8_2 521 ; RV32: bb.1 (%ir-block.0): 522 ; RV32-NEXT: liveins: $x10 523 ; RV32-NEXT: {{ $}} 524 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 525 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 526 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF 527 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 528 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) 529 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) 530 ; RV32-NEXT: PseudoRET implicit $v8 531 ; 532 ; RV64-LABEL: name: insertelement_nxv2i8_2 533 ; RV64: bb.1 (%ir-block.0): 534 ; RV64-NEXT: liveins: $x10 535 ; RV64-NEXT: {{ $}} 536 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 537 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) 538 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF 539 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 540 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) 541 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) 542 ; RV64-NEXT: PseudoRET implicit $v8 543 %a = insertelement <vscale x 2 x i8> poison, i8 %x, i32 0 544 ret <vscale x 2 x i8> %a 545} 546 547define <vscale x 4 x i8> @insertelement_nxv4i8_0() { 548 ; RV32-LABEL: name: insertelement_nxv4i8_0 549 ; RV32: bb.1 (%ir-block.0): 550 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF 551 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 552 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 553 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 554 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 555 ; RV32-NEXT: PseudoRET implicit $v8 556 ; 557 ; RV64-LABEL: name: insertelement_nxv4i8_0 558 ; RV64: bb.1 (%ir-block.0): 559 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF 560 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 561 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 562 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 563 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 564 ; RV64-NEXT: PseudoRET implicit $v8 565 %a = insertelement <vscale x 4 x i8> poison, i8 0, i32 0 566 ret <vscale x 4 x i8> %a 567} 568 569define <vscale x 4 x i8> @insertelement_nxv4i8_1() { 570 ; RV32-LABEL: name: insertelement_nxv4i8_1 571 ; RV32: bb.1 (%ir-block.0): 572 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF 573 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 574 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 575 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 576 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 577 ; RV32-NEXT: PseudoRET implicit $v8 578 ; 579 ; RV64-LABEL: name: insertelement_nxv4i8_1 580 ; RV64: bb.1 (%ir-block.0): 581 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF 582 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 583 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 584 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 585 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 586 ; RV64-NEXT: PseudoRET implicit $v8 587 %a = insertelement <vscale x 4 x i8> poison, i8 -1, i32 0 588 ret <vscale x 4 x i8> %a 589} 590 591define <vscale x 4 x i8> @insertelement_nxv4i8_2(i8 %x) { 592 ; RV32-LABEL: name: insertelement_nxv4i8_2 593 ; RV32: bb.1 (%ir-block.0): 594 ; RV32-NEXT: liveins: $x10 595 ; RV32-NEXT: {{ $}} 596 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 597 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 598 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF 599 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 600 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) 601 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 602 ; RV32-NEXT: PseudoRET implicit $v8 603 ; 604 ; RV64-LABEL: name: insertelement_nxv4i8_2 605 ; RV64: bb.1 (%ir-block.0): 606 ; RV64-NEXT: liveins: $x10 607 ; RV64-NEXT: {{ $}} 608 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 609 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) 610 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF 611 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 612 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) 613 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 614 ; RV64-NEXT: PseudoRET implicit $v8 615 %a = insertelement <vscale x 4 x i8> poison, i8 %x, i32 0 616 ret <vscale x 4 x i8> %a 617} 618 619define <vscale x 8 x i8> @insertelement_nxv8i8_0() { 620 ; RV32-LABEL: name: insertelement_nxv8i8_0 621 ; RV32: bb.1 (%ir-block.0): 622 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF 623 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 624 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 625 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 626 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) 627 ; RV32-NEXT: PseudoRET implicit $v8 628 ; 629 ; RV64-LABEL: name: insertelement_nxv8i8_0 630 ; RV64: bb.1 (%ir-block.0): 631 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF 632 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 633 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 634 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 635 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) 636 ; RV64-NEXT: PseudoRET implicit $v8 637 %a = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 638 ret <vscale x 8 x i8> %a 639} 640 641define <vscale x 8 x i8> @insertelement_nxv8i8_1() { 642 ; RV32-LABEL: name: insertelement_nxv8i8_1 643 ; RV32: bb.1 (%ir-block.0): 644 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF 645 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 646 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 647 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 648 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) 649 ; RV32-NEXT: PseudoRET implicit $v8 650 ; 651 ; RV64-LABEL: name: insertelement_nxv8i8_1 652 ; RV64: bb.1 (%ir-block.0): 653 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF 654 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 655 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 656 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 657 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) 658 ; RV64-NEXT: PseudoRET implicit $v8 659 %a = insertelement <vscale x 8 x i8> poison, i8 -1, i32 0 660 ret <vscale x 8 x i8> %a 661} 662 663define <vscale x 8 x i8> @insertelement_nxv8i8_2(i8 %x) { 664 ; RV32-LABEL: name: insertelement_nxv8i8_2 665 ; RV32: bb.1 (%ir-block.0): 666 ; RV32-NEXT: liveins: $x10 667 ; RV32-NEXT: {{ $}} 668 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 669 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 670 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF 671 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 672 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) 673 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) 674 ; RV32-NEXT: PseudoRET implicit $v8 675 ; 676 ; RV64-LABEL: name: insertelement_nxv8i8_2 677 ; RV64: bb.1 (%ir-block.0): 678 ; RV64-NEXT: liveins: $x10 679 ; RV64-NEXT: {{ $}} 680 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 681 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) 682 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF 683 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 684 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) 685 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) 686 ; RV64-NEXT: PseudoRET implicit $v8 687 %a = insertelement <vscale x 8 x i8> poison, i8 %x, i32 0 688 ret <vscale x 8 x i8> %a 689} 690 691define <vscale x 16 x i8> @insertelement_nxv16i8_0() { 692 ; RV32-LABEL: name: insertelement_nxv16i8_0 693 ; RV32: bb.1 (%ir-block.0): 694 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF 695 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 696 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 697 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 698 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) 699 ; RV32-NEXT: PseudoRET implicit $v8m2 700 ; 701 ; RV64-LABEL: name: insertelement_nxv16i8_0 702 ; RV64: bb.1 (%ir-block.0): 703 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF 704 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 705 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 706 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 707 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) 708 ; RV64-NEXT: PseudoRET implicit $v8m2 709 %a = insertelement <vscale x 16 x i8> poison, i8 0, i64 0 710 ret <vscale x 16 x i8> %a 711} 712 713define <vscale x 16 x i8> @insertelement_nxv16i8_1() { 714 ; RV32-LABEL: name: insertelement_nxv16i8_1 715 ; RV32: bb.1 (%ir-block.0): 716 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF 717 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 718 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 719 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) 720 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) 721 ; RV32-NEXT: PseudoRET implicit $v8m2 722 ; 723 ; RV64-LABEL: name: insertelement_nxv16i8_1 724 ; RV64: bb.1 (%ir-block.0): 725 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF 726 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 727 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 728 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) 729 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) 730 ; RV64-NEXT: PseudoRET implicit $v8m2 731 %a = insertelement <vscale x 16 x i8> poison, i8 -1, i32 0 732 ret <vscale x 16 x i8> %a 733} 734 735define <vscale x 16 x i8> @insertelement_nxv16i8_2(i8 %x, i64 %idx) { 736 ; RV32-LABEL: name: insertelement_nxv16i8_2 737 ; RV32: bb.1 (%ir-block.0): 738 ; RV32-NEXT: liveins: $x10, $x11, $x12 739 ; RV32-NEXT: {{ $}} 740 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 741 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 742 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 743 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 744 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) 745 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF 746 ; RV32-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64) 747 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[TRUNC1]](s32) 748 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) 749 ; RV32-NEXT: PseudoRET implicit $v8m2 750 ; 751 ; RV64-LABEL: name: insertelement_nxv16i8_2 752 ; RV64: bb.1 (%ir-block.0): 753 ; RV64-NEXT: liveins: $x10, $x11 754 ; RV64-NEXT: {{ $}} 755 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 756 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) 757 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 758 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF 759 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s64) 760 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) 761 ; RV64-NEXT: PseudoRET implicit $v8m2 762 %a = insertelement <vscale x 16 x i8> poison, i8 %x, i64 %idx 763 ret <vscale x 16 x i8> %a 764} 765 766define <vscale x 4 x i8> @insertelement_nxv4i8_3(<vscale x 4 x i8> %v, i8 %x) { 767 ; RV32-LABEL: name: insertelement_nxv4i8_3 768 ; RV32: bb.1 (%ir-block.0): 769 ; RV32-NEXT: liveins: $v8, $x10 770 ; RV32-NEXT: {{ $}} 771 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 772 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 773 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 774 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 775 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s32) 776 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 777 ; RV32-NEXT: PseudoRET implicit $v8 778 ; 779 ; RV64-LABEL: name: insertelement_nxv4i8_3 780 ; RV64: bb.1 (%ir-block.0): 781 ; RV64-NEXT: liveins: $v8, $x10 782 ; RV64-NEXT: {{ $}} 783 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 784 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 785 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64) 786 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 787 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s64) 788 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) 789 ; RV64-NEXT: PseudoRET implicit $v8 790 %a = insertelement <vscale x 4 x i8> %v, i8 %x, i32 0 791 ret <vscale x 4 x i8> %a 792} 793 794define <vscale x 1 x i16> @insertelement_nxv1i16_0() { 795 ; RV32-LABEL: name: insertelement_nxv1i16_0 796 ; RV32: bb.1 (%ir-block.0): 797 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF 798 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 799 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 800 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 801 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) 802 ; RV32-NEXT: PseudoRET implicit $v8 803 ; 804 ; RV64-LABEL: name: insertelement_nxv1i16_0 805 ; RV64: bb.1 (%ir-block.0): 806 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF 807 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 808 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 809 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 810 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) 811 ; RV64-NEXT: PseudoRET implicit $v8 812 %a = insertelement <vscale x 1 x i16> poison, i16 0, i32 0 813 ret <vscale x 1 x i16> %a 814} 815 816define <vscale x 1 x i16> @insertelement_nxv1i16_1() { 817 ; RV32-LABEL: name: insertelement_nxv1i16_1 818 ; RV32: bb.1 (%ir-block.0): 819 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF 820 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 821 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 822 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 823 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) 824 ; RV32-NEXT: PseudoRET implicit $v8 825 ; 826 ; RV64-LABEL: name: insertelement_nxv1i16_1 827 ; RV64: bb.1 (%ir-block.0): 828 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF 829 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 830 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 831 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 832 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) 833 ; RV64-NEXT: PseudoRET implicit $v8 834 %a = insertelement <vscale x 1 x i16> poison, i16 -1, i32 0 835 ret <vscale x 1 x i16> %a 836} 837 838define <vscale x 1 x i16> @insertelement_nxv1i16_2(i16 %x) { 839 ; RV32-LABEL: name: insertelement_nxv1i16_2 840 ; RV32: bb.1 (%ir-block.0): 841 ; RV32-NEXT: liveins: $x10 842 ; RV32-NEXT: {{ $}} 843 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 844 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 845 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF 846 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 847 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) 848 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) 849 ; RV32-NEXT: PseudoRET implicit $v8 850 ; 851 ; RV64-LABEL: name: insertelement_nxv1i16_2 852 ; RV64: bb.1 (%ir-block.0): 853 ; RV64-NEXT: liveins: $x10 854 ; RV64-NEXT: {{ $}} 855 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 856 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) 857 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF 858 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 859 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) 860 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) 861 ; RV64-NEXT: PseudoRET implicit $v8 862 %a = insertelement <vscale x 1 x i16> poison, i16 %x, i32 0 863 ret <vscale x 1 x i16> %a 864} 865 866define <vscale x 2 x i16> @insertelement_nxv2i16_0() { 867 ; RV32-LABEL: name: insertelement_nxv2i16_0 868 ; RV32: bb.1 (%ir-block.0): 869 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF 870 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 871 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 872 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 873 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) 874 ; RV32-NEXT: PseudoRET implicit $v8 875 ; 876 ; RV64-LABEL: name: insertelement_nxv2i16_0 877 ; RV64: bb.1 (%ir-block.0): 878 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF 879 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 880 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 881 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 882 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) 883 ; RV64-NEXT: PseudoRET implicit $v8 884 %a = insertelement <vscale x 2 x i16> poison, i16 0, i64 1 885 ret <vscale x 2 x i16> %a 886} 887 888define <vscale x 2 x i16> @insertelement_nxv2i16_1() { 889 ; RV32-LABEL: name: insertelement_nxv2i16_1 890 ; RV32: bb.1 (%ir-block.0): 891 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF 892 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 893 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 894 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 895 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) 896 ; RV32-NEXT: PseudoRET implicit $v8 897 ; 898 ; RV64-LABEL: name: insertelement_nxv2i16_1 899 ; RV64: bb.1 (%ir-block.0): 900 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF 901 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 902 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 903 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 904 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) 905 ; RV64-NEXT: PseudoRET implicit $v8 906 %a = insertelement <vscale x 2 x i16> poison, i16 -1, i32 0 907 ret <vscale x 2 x i16> %a 908} 909 910define <vscale x 2 x i16> @insertelement_nxv2i16_2(i16 %x) { 911 ; RV32-LABEL: name: insertelement_nxv2i16_2 912 ; RV32: bb.1 (%ir-block.0): 913 ; RV32-NEXT: liveins: $x10 914 ; RV32-NEXT: {{ $}} 915 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 916 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 917 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF 918 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 919 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) 920 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) 921 ; RV32-NEXT: PseudoRET implicit $v8 922 ; 923 ; RV64-LABEL: name: insertelement_nxv2i16_2 924 ; RV64: bb.1 (%ir-block.0): 925 ; RV64-NEXT: liveins: $x10 926 ; RV64-NEXT: {{ $}} 927 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 928 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) 929 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF 930 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 931 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) 932 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) 933 ; RV64-NEXT: PseudoRET implicit $v8 934 %a = insertelement <vscale x 2 x i16> poison, i16 %x, i32 0 935 ret <vscale x 2 x i16> %a 936} 937 938define <vscale x 4 x i16> @insertelement_nxv4i16_0() { 939 ; RV32-LABEL: name: insertelement_nxv4i16_0 940 ; RV32: bb.1 (%ir-block.0): 941 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF 942 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 943 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 944 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 945 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 946 ; RV32-NEXT: PseudoRET implicit $v8 947 ; 948 ; RV64-LABEL: name: insertelement_nxv4i16_0 949 ; RV64: bb.1 (%ir-block.0): 950 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF 951 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 952 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 953 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 954 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 955 ; RV64-NEXT: PseudoRET implicit $v8 956 %a = insertelement <vscale x 4 x i16> poison, i16 0, i32 0 957 ret <vscale x 4 x i16> %a 958} 959 960define <vscale x 4 x i16> @insertelement_nxv4i16_1() { 961 ; RV32-LABEL: name: insertelement_nxv4i16_1 962 ; RV32: bb.1 (%ir-block.0): 963 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF 964 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 965 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 966 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 967 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 968 ; RV32-NEXT: PseudoRET implicit $v8 969 ; 970 ; RV64-LABEL: name: insertelement_nxv4i16_1 971 ; RV64: bb.1 (%ir-block.0): 972 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF 973 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 974 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 975 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 976 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 977 ; RV64-NEXT: PseudoRET implicit $v8 978 %a = insertelement <vscale x 4 x i16> poison, i16 -1, i32 0 979 ret <vscale x 4 x i16> %a 980} 981 982define <vscale x 4 x i16> @insertelement_nxv4i16_2(i16 %x) { 983 ; RV32-LABEL: name: insertelement_nxv4i16_2 984 ; RV32: bb.1 (%ir-block.0): 985 ; RV32-NEXT: liveins: $x10 986 ; RV32-NEXT: {{ $}} 987 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 988 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 989 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF 990 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 991 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) 992 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 993 ; RV32-NEXT: PseudoRET implicit $v8 994 ; 995 ; RV64-LABEL: name: insertelement_nxv4i16_2 996 ; RV64: bb.1 (%ir-block.0): 997 ; RV64-NEXT: liveins: $x10 998 ; RV64-NEXT: {{ $}} 999 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1000 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) 1001 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF 1002 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1003 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) 1004 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 1005 ; RV64-NEXT: PseudoRET implicit $v8 1006 %a = insertelement <vscale x 4 x i16> poison, i16 %x, i32 0 1007 ret <vscale x 4 x i16> %a 1008} 1009 1010define <vscale x 8 x i16> @insertelement_nxv8i16_0() { 1011 ; RV32-LABEL: name: insertelement_nxv8i16_0 1012 ; RV32: bb.1 (%ir-block.0): 1013 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF 1014 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 1015 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1016 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 1017 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) 1018 ; RV32-NEXT: PseudoRET implicit $v8m2 1019 ; 1020 ; RV64-LABEL: name: insertelement_nxv8i16_0 1021 ; RV64: bb.1 (%ir-block.0): 1022 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF 1023 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 1024 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1025 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 1026 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) 1027 ; RV64-NEXT: PseudoRET implicit $v8m2 1028 %a = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 1029 ret <vscale x 8 x i16> %a 1030} 1031 1032define <vscale x 8 x i16> @insertelement_nxv8i16_1() { 1033 ; RV32-LABEL: name: insertelement_nxv8i16_1 1034 ; RV32: bb.1 (%ir-block.0): 1035 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF 1036 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 1037 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1038 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 1039 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) 1040 ; RV32-NEXT: PseudoRET implicit $v8m2 1041 ; 1042 ; RV64-LABEL: name: insertelement_nxv8i16_1 1043 ; RV64: bb.1 (%ir-block.0): 1044 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF 1045 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 1046 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1047 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 1048 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) 1049 ; RV64-NEXT: PseudoRET implicit $v8m2 1050 %a = insertelement <vscale x 8 x i16> poison, i16 -1, i32 0 1051 ret <vscale x 8 x i16> %a 1052} 1053 1054define <vscale x 8 x i16> @insertelement_nxv8i16_2(i16 %x) { 1055 ; RV32-LABEL: name: insertelement_nxv8i16_2 1056 ; RV32: bb.1 (%ir-block.0): 1057 ; RV32-NEXT: liveins: $x10 1058 ; RV32-NEXT: {{ $}} 1059 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1060 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 1061 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF 1062 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1063 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) 1064 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) 1065 ; RV32-NEXT: PseudoRET implicit $v8m2 1066 ; 1067 ; RV64-LABEL: name: insertelement_nxv8i16_2 1068 ; RV64: bb.1 (%ir-block.0): 1069 ; RV64-NEXT: liveins: $x10 1070 ; RV64-NEXT: {{ $}} 1071 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1072 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) 1073 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF 1074 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1075 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) 1076 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) 1077 ; RV64-NEXT: PseudoRET implicit $v8m2 1078 %a = insertelement <vscale x 8 x i16> poison, i16 %x, i32 0 1079 ret <vscale x 8 x i16> %a 1080} 1081 1082define <vscale x 16 x i16> @insertelement_nxv16i16_0() { 1083 ; RV32-LABEL: name: insertelement_nxv16i16_0 1084 ; RV32: bb.1 (%ir-block.0): 1085 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF 1086 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 1087 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1088 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 1089 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) 1090 ; RV32-NEXT: PseudoRET implicit $v8m4 1091 ; 1092 ; RV64-LABEL: name: insertelement_nxv16i16_0 1093 ; RV64: bb.1 (%ir-block.0): 1094 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF 1095 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 1096 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1097 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 1098 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) 1099 ; RV64-NEXT: PseudoRET implicit $v8m4 1100 %a = insertelement <vscale x 16 x i16> poison, i16 0, i32 0 1101 ret <vscale x 16 x i16> %a 1102} 1103 1104define <vscale x 16 x i16> @insertelement_nxv16i16_1() { 1105 ; RV32-LABEL: name: insertelement_nxv16i16_1 1106 ; RV32: bb.1 (%ir-block.0): 1107 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF 1108 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 1109 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1110 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) 1111 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) 1112 ; RV32-NEXT: PseudoRET implicit $v8m4 1113 ; 1114 ; RV64-LABEL: name: insertelement_nxv16i16_1 1115 ; RV64: bb.1 (%ir-block.0): 1116 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF 1117 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 1118 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1119 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) 1120 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) 1121 ; RV64-NEXT: PseudoRET implicit $v8m4 1122 %a = insertelement <vscale x 16 x i16> poison, i16 -1, i32 0 1123 ret <vscale x 16 x i16> %a 1124} 1125 1126define <vscale x 16 x i16> @insertelement_nxv16i16_2(i16 %x) { 1127 ; RV32-LABEL: name: insertelement_nxv16i16_2 1128 ; RV32: bb.1 (%ir-block.0): 1129 ; RV32-NEXT: liveins: $x10 1130 ; RV32-NEXT: {{ $}} 1131 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1132 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 1133 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF 1134 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1135 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) 1136 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) 1137 ; RV32-NEXT: PseudoRET implicit $v8m4 1138 ; 1139 ; RV64-LABEL: name: insertelement_nxv16i16_2 1140 ; RV64: bb.1 (%ir-block.0): 1141 ; RV64-NEXT: liveins: $x10 1142 ; RV64-NEXT: {{ $}} 1143 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1144 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) 1145 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF 1146 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1147 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) 1148 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) 1149 ; RV64-NEXT: PseudoRET implicit $v8m4 1150 %a = insertelement <vscale x 16 x i16> poison, i16 %x, i32 0 1151 ret <vscale x 16 x i16> %a 1152} 1153 1154define <vscale x 4 x i16> @insertelement_nxv4i16(<vscale x 4 x i16> %v, i16 %x) { 1155 ; RV32-LABEL: name: insertelement_nxv4i16 1156 ; RV32: bb.1 (%ir-block.0): 1157 ; RV32-NEXT: liveins: $v8, $x10 1158 ; RV32-NEXT: {{ $}} 1159 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 1160 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 1161 ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 1162 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1163 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s32) 1164 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 1165 ; RV32-NEXT: PseudoRET implicit $v8 1166 ; 1167 ; RV64-LABEL: name: insertelement_nxv4i16 1168 ; RV64: bb.1 (%ir-block.0): 1169 ; RV64-NEXT: liveins: $v8, $x10 1170 ; RV64-NEXT: {{ $}} 1171 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 1172 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 1173 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64) 1174 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1175 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s64) 1176 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) 1177 ; RV64-NEXT: PseudoRET implicit $v8 1178 %a = insertelement <vscale x 4 x i16> %v, i16 %x, i32 0 1179 ret <vscale x 4 x i16> %a 1180} 1181 1182define <vscale x 1 x i32> @insertelement_nxv1i32_0() { 1183 ; RV32-LABEL: name: insertelement_nxv1i32_0 1184 ; RV32: bb.1 (%ir-block.0): 1185 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF 1186 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1187 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) 1188 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) 1189 ; RV32-NEXT: PseudoRET implicit $v8 1190 ; 1191 ; RV64-LABEL: name: insertelement_nxv1i32_0 1192 ; RV64: bb.1 (%ir-block.0): 1193 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF 1194 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1195 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1196 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1197 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) 1198 ; RV64-NEXT: PseudoRET implicit $v8 1199 %a = insertelement <vscale x 1 x i32> poison, i32 0, i32 0 1200 ret <vscale x 1 x i32> %a 1201} 1202 1203define <vscale x 1 x i32> @insertelement_nxv1i32_1() { 1204 ; RV32-LABEL: name: insertelement_nxv1i32_1 1205 ; RV32: bb.1 (%ir-block.0): 1206 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF 1207 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1208 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1209 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) 1210 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) 1211 ; RV32-NEXT: PseudoRET implicit $v8 1212 ; 1213 ; RV64-LABEL: name: insertelement_nxv1i32_1 1214 ; RV64: bb.1 (%ir-block.0): 1215 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF 1216 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1217 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1218 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1219 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) 1220 ; RV64-NEXT: PseudoRET implicit $v8 1221 %a = insertelement <vscale x 1 x i32> poison, i32 -1, i32 0 1222 ret <vscale x 1 x i32> %a 1223} 1224 1225define <vscale x 1 x i32> @insertelement_nxv1i32_2(i32 %x) { 1226 ; RV32-LABEL: name: insertelement_nxv1i32_2 1227 ; RV32: bb.1 (%ir-block.0): 1228 ; RV32-NEXT: liveins: $x10 1229 ; RV32-NEXT: {{ $}} 1230 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1231 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF 1232 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1233 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) 1234 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) 1235 ; RV32-NEXT: PseudoRET implicit $v8 1236 ; 1237 ; RV64-LABEL: name: insertelement_nxv1i32_2 1238 ; RV64: bb.1 (%ir-block.0): 1239 ; RV64-NEXT: liveins: $x10 1240 ; RV64-NEXT: {{ $}} 1241 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1242 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 1243 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF 1244 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1245 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) 1246 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) 1247 ; RV64-NEXT: PseudoRET implicit $v8 1248 %a = insertelement <vscale x 1 x i32> poison, i32 %x, i32 0 1249 ret <vscale x 1 x i32> %a 1250} 1251 1252define <vscale x 2 x i32> @insertelement_nxv2i32_0() { 1253 ; RV32-LABEL: name: insertelement_nxv2i32_0 1254 ; RV32: bb.1 (%ir-block.0): 1255 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF 1256 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1257 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) 1258 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) 1259 ; RV32-NEXT: PseudoRET implicit $v8 1260 ; 1261 ; RV64-LABEL: name: insertelement_nxv2i32_0 1262 ; RV64: bb.1 (%ir-block.0): 1263 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF 1264 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1265 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1266 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1267 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) 1268 ; RV64-NEXT: PseudoRET implicit $v8 1269 %a = insertelement <vscale x 2 x i32> poison, i32 0, i32 0 1270 ret <vscale x 2 x i32> %a 1271} 1272 1273define <vscale x 2 x i32> @insertelement_nxv2i32_1() { 1274 ; RV32-LABEL: name: insertelement_nxv2i32_1 1275 ; RV32: bb.1 (%ir-block.0): 1276 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF 1277 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1278 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1279 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) 1280 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) 1281 ; RV32-NEXT: PseudoRET implicit $v8 1282 ; 1283 ; RV64-LABEL: name: insertelement_nxv2i32_1 1284 ; RV64: bb.1 (%ir-block.0): 1285 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF 1286 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1287 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1288 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1289 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) 1290 ; RV64-NEXT: PseudoRET implicit $v8 1291 %a = insertelement <vscale x 2 x i32> poison, i32 -1, i32 0 1292 ret <vscale x 2 x i32> %a 1293} 1294 1295define <vscale x 2 x i32> @insertelement_nxv2i32_2(i32 %x) { 1296 ; RV32-LABEL: name: insertelement_nxv2i32_2 1297 ; RV32: bb.1 (%ir-block.0): 1298 ; RV32-NEXT: liveins: $x10 1299 ; RV32-NEXT: {{ $}} 1300 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1301 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF 1302 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1303 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) 1304 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) 1305 ; RV32-NEXT: PseudoRET implicit $v8 1306 ; 1307 ; RV64-LABEL: name: insertelement_nxv2i32_2 1308 ; RV64: bb.1 (%ir-block.0): 1309 ; RV64-NEXT: liveins: $x10 1310 ; RV64-NEXT: {{ $}} 1311 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1312 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 1313 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF 1314 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1315 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) 1316 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) 1317 ; RV64-NEXT: PseudoRET implicit $v8 1318 %a = insertelement <vscale x 2 x i32> poison, i32 %x, i32 0 1319 ret <vscale x 2 x i32> %a 1320} 1321 1322define <vscale x 4 x i32> @insertelement_nxv4i32_0() { 1323 ; RV32-LABEL: name: insertelement_nxv4i32_0 1324 ; RV32: bb.1 (%ir-block.0): 1325 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF 1326 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1327 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) 1328 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1329 ; RV32-NEXT: PseudoRET implicit $v8m2 1330 ; 1331 ; RV64-LABEL: name: insertelement_nxv4i32_0 1332 ; RV64: bb.1 (%ir-block.0): 1333 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF 1334 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1335 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1336 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1337 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1338 ; RV64-NEXT: PseudoRET implicit $v8m2 1339 %a = insertelement <vscale x 4 x i32> poison, i32 0, i32 0 1340 ret <vscale x 4 x i32> %a 1341} 1342 1343define <vscale x 4 x i32> @insertelement_nxv4i32_1() { 1344 ; RV32-LABEL: name: insertelement_nxv4i32_1 1345 ; RV32: bb.1 (%ir-block.0): 1346 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF 1347 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1348 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1349 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) 1350 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1351 ; RV32-NEXT: PseudoRET implicit $v8m2 1352 ; 1353 ; RV64-LABEL: name: insertelement_nxv4i32_1 1354 ; RV64: bb.1 (%ir-block.0): 1355 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF 1356 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1357 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1358 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1359 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1360 ; RV64-NEXT: PseudoRET implicit $v8m2 1361 %a = insertelement <vscale x 4 x i32> poison, i32 -1, i32 0 1362 ret <vscale x 4 x i32> %a 1363} 1364 1365define <vscale x 4 x i32> @insertelement_nxv4i32_2(i32 %x) { 1366 ; RV32-LABEL: name: insertelement_nxv4i32_2 1367 ; RV32: bb.1 (%ir-block.0): 1368 ; RV32-NEXT: liveins: $x10 1369 ; RV32-NEXT: {{ $}} 1370 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1371 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF 1372 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1373 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) 1374 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1375 ; RV32-NEXT: PseudoRET implicit $v8m2 1376 ; 1377 ; RV64-LABEL: name: insertelement_nxv4i32_2 1378 ; RV64: bb.1 (%ir-block.0): 1379 ; RV64-NEXT: liveins: $x10 1380 ; RV64-NEXT: {{ $}} 1381 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1382 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 1383 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF 1384 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1385 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) 1386 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1387 ; RV64-NEXT: PseudoRET implicit $v8m2 1388 %a = insertelement <vscale x 4 x i32> poison, i32 %x, i32 0 1389 ret <vscale x 4 x i32> %a 1390} 1391 1392define <vscale x 8 x i32> @insertelement_nxv8i32_0() { 1393 ; RV32-LABEL: name: insertelement_nxv8i32_0 1394 ; RV32: bb.1 (%ir-block.0): 1395 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF 1396 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1397 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) 1398 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) 1399 ; RV32-NEXT: PseudoRET implicit $v8m4 1400 ; 1401 ; RV64-LABEL: name: insertelement_nxv8i32_0 1402 ; RV64: bb.1 (%ir-block.0): 1403 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF 1404 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1405 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1406 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1407 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) 1408 ; RV64-NEXT: PseudoRET implicit $v8m4 1409 %a = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 1410 ret <vscale x 8 x i32> %a 1411} 1412 1413define <vscale x 8 x i32> @insertelement_nxv8i32_1() { 1414 ; RV32-LABEL: name: insertelement_nxv8i32_1 1415 ; RV32: bb.1 (%ir-block.0): 1416 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF 1417 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1418 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1419 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) 1420 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) 1421 ; RV32-NEXT: PseudoRET implicit $v8m4 1422 ; 1423 ; RV64-LABEL: name: insertelement_nxv8i32_1 1424 ; RV64: bb.1 (%ir-block.0): 1425 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF 1426 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1427 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1428 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1429 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) 1430 ; RV64-NEXT: PseudoRET implicit $v8m4 1431 %a = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0 1432 ret <vscale x 8 x i32> %a 1433} 1434 1435define <vscale x 8 x i32> @insertelement_nxv8i32_2(i32 %x) { 1436 ; RV32-LABEL: name: insertelement_nxv8i32_2 1437 ; RV32: bb.1 (%ir-block.0): 1438 ; RV32-NEXT: liveins: $x10 1439 ; RV32-NEXT: {{ $}} 1440 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1441 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF 1442 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1443 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) 1444 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) 1445 ; RV32-NEXT: PseudoRET implicit $v8m4 1446 ; 1447 ; RV64-LABEL: name: insertelement_nxv8i32_2 1448 ; RV64: bb.1 (%ir-block.0): 1449 ; RV64-NEXT: liveins: $x10 1450 ; RV64-NEXT: {{ $}} 1451 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1452 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 1453 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF 1454 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1455 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) 1456 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) 1457 ; RV64-NEXT: PseudoRET implicit $v8m4 1458 %a = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0 1459 ret <vscale x 8 x i32> %a 1460} 1461 1462define <vscale x 16 x i32> @insertelement_nxv16i32_0() { 1463 ; RV32-LABEL: name: insertelement_nxv16i32_0 1464 ; RV32: bb.1 (%ir-block.0): 1465 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF 1466 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1467 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) 1468 ; RV32-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) 1469 ; RV32-NEXT: PseudoRET implicit $v8m8 1470 ; 1471 ; RV64-LABEL: name: insertelement_nxv16i32_0 1472 ; RV64: bb.1 (%ir-block.0): 1473 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF 1474 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1475 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1476 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1477 ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) 1478 ; RV64-NEXT: PseudoRET implicit $v8m8 1479 %a = insertelement <vscale x 16 x i32> poison, i32 0, i32 0 1480 ret <vscale x 16 x i32> %a 1481} 1482 1483define <vscale x 16 x i32> @insertelement_nxv16i32_1() { 1484 ; RV32-LABEL: name: insertelement_nxv16i32_1 1485 ; RV32: bb.1 (%ir-block.0): 1486 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF 1487 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1488 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1489 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) 1490 ; RV32-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) 1491 ; RV32-NEXT: PseudoRET implicit $v8m8 1492 ; 1493 ; RV64-LABEL: name: insertelement_nxv16i32_1 1494 ; RV64: bb.1 (%ir-block.0): 1495 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF 1496 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 1497 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1498 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) 1499 ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) 1500 ; RV64-NEXT: PseudoRET implicit $v8m8 1501 %a = insertelement <vscale x 16 x i32> poison, i32 -1, i32 0 1502 ret <vscale x 16 x i32> %a 1503} 1504 1505define <vscale x 16 x i32> @insertelement_nxv16i32_2(i32 %x) { 1506 ; RV32-LABEL: name: insertelement_nxv16i32_2 1507 ; RV32: bb.1 (%ir-block.0): 1508 ; RV32-NEXT: liveins: $x10 1509 ; RV32-NEXT: {{ $}} 1510 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1511 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF 1512 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1513 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) 1514 ; RV32-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) 1515 ; RV32-NEXT: PseudoRET implicit $v8m8 1516 ; 1517 ; RV64-LABEL: name: insertelement_nxv16i32_2 1518 ; RV64: bb.1 (%ir-block.0): 1519 ; RV64-NEXT: liveins: $x10 1520 ; RV64-NEXT: {{ $}} 1521 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1522 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 1523 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF 1524 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1525 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) 1526 ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) 1527 ; RV64-NEXT: PseudoRET implicit $v8m8 1528 %a = insertelement <vscale x 16 x i32> poison, i32 %x, i32 0 1529 ret <vscale x 16 x i32> %a 1530} 1531 1532define <vscale x 4 x i32> @insertelement_nxv4i32(<vscale x 4 x i32> %v, i32 %x) { 1533 ; RV32-LABEL: name: insertelement_nxv4i32 1534 ; RV32: bb.1 (%ir-block.0): 1535 ; RV32-NEXT: liveins: $x10, $v8m2 1536 ; RV32-NEXT: {{ $}} 1537 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 1538 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 1539 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1540 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32) 1541 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1542 ; RV32-NEXT: PseudoRET implicit $v8m2 1543 ; 1544 ; RV64-LABEL: name: insertelement_nxv4i32 1545 ; RV64: bb.1 (%ir-block.0): 1546 ; RV64-NEXT: liveins: $x10, $v8m2 1547 ; RV64-NEXT: {{ $}} 1548 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 1549 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 1550 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) 1551 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1552 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s64) 1553 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) 1554 ; RV64-NEXT: PseudoRET implicit $v8m2 1555 %a = insertelement <vscale x 4 x i32> %v, i32 %x, i32 0 1556 ret <vscale x 4 x i32> %a 1557} 1558 1559define <vscale x 1 x i64> @insertelement_nxv1i64_0() { 1560 ; RV32-LABEL: name: insertelement_nxv1i64_0 1561 ; RV32: bb.1 (%ir-block.0): 1562 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF 1563 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1564 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1565 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1566 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) 1567 ; RV32-NEXT: PseudoRET implicit $v8 1568 ; 1569 ; RV64-LABEL: name: insertelement_nxv1i64_0 1570 ; RV64: bb.1 (%ir-block.0): 1571 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF 1572 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1573 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) 1574 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) 1575 ; RV64-NEXT: PseudoRET implicit $v8 1576 %a = insertelement <vscale x 1 x i64> poison, i64 0, i32 0 1577 ret <vscale x 1 x i64> %a 1578} 1579 1580define <vscale x 1 x i64> @insertelement_nxv1i64_1() { 1581 ; RV32-LABEL: name: insertelement_nxv1i64_1 1582 ; RV32: bb.1 (%ir-block.0): 1583 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF 1584 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1585 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1586 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1587 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) 1588 ; RV32-NEXT: PseudoRET implicit $v8 1589 ; 1590 ; RV64-LABEL: name: insertelement_nxv1i64_1 1591 ; RV64: bb.1 (%ir-block.0): 1592 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF 1593 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1594 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1595 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) 1596 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) 1597 ; RV64-NEXT: PseudoRET implicit $v8 1598 %a = insertelement <vscale x 1 x i64> poison, i64 -1, i32 0 1599 ret <vscale x 1 x i64> %a 1600} 1601 1602define <vscale x 1 x i64> @insertelement_nxv1i64_2(i64 %x) { 1603 ; RV32-LABEL: name: insertelement_nxv1i64_2 1604 ; RV32: bb.1 (%ir-block.0): 1605 ; RV32-NEXT: liveins: $x10, $x11 1606 ; RV32-NEXT: {{ $}} 1607 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1608 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 1609 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 1610 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF 1611 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1612 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) 1613 ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) 1614 ; RV32-NEXT: PseudoRET implicit $v8 1615 ; 1616 ; RV64-LABEL: name: insertelement_nxv1i64_2 1617 ; RV64: bb.1 (%ir-block.0): 1618 ; RV64-NEXT: liveins: $x10 1619 ; RV64-NEXT: {{ $}} 1620 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1621 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF 1622 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1623 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) 1624 ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) 1625 ; RV64-NEXT: PseudoRET implicit $v8 1626 %a = insertelement <vscale x 1 x i64> poison, i64 %x, i32 0 1627 ret <vscale x 1 x i64> %a 1628} 1629 1630define <vscale x 2 x i64> @insertelement_nxv2i64_0() { 1631 ; RV32-LABEL: name: insertelement_nxv2i64_0 1632 ; RV32: bb.1 (%ir-block.0): 1633 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF 1634 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1635 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1636 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1637 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) 1638 ; RV32-NEXT: PseudoRET implicit $v8m2 1639 ; 1640 ; RV64-LABEL: name: insertelement_nxv2i64_0 1641 ; RV64: bb.1 (%ir-block.0): 1642 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF 1643 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1644 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) 1645 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) 1646 ; RV64-NEXT: PseudoRET implicit $v8m2 1647 %a = insertelement <vscale x 2 x i64> poison, i64 0, i32 0 1648 ret <vscale x 2 x i64> %a 1649} 1650 1651define <vscale x 2 x i64> @insertelement_nxv2i64_1() { 1652 ; RV32-LABEL: name: insertelement_nxv2i64_1 1653 ; RV32: bb.1 (%ir-block.0): 1654 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF 1655 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1656 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1657 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1658 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) 1659 ; RV32-NEXT: PseudoRET implicit $v8m2 1660 ; 1661 ; RV64-LABEL: name: insertelement_nxv2i64_1 1662 ; RV64: bb.1 (%ir-block.0): 1663 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF 1664 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1665 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1666 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) 1667 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) 1668 ; RV64-NEXT: PseudoRET implicit $v8m2 1669 %a = insertelement <vscale x 2 x i64> poison, i64 -1, i32 0 1670 ret <vscale x 2 x i64> %a 1671} 1672 1673define <vscale x 2 x i64> @insertelement_nxv2i64_2(i64 %x) { 1674 ; RV32-LABEL: name: insertelement_nxv2i64_2 1675 ; RV32: bb.1 (%ir-block.0): 1676 ; RV32-NEXT: liveins: $x10, $x11 1677 ; RV32-NEXT: {{ $}} 1678 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1679 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 1680 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 1681 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF 1682 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1683 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) 1684 ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) 1685 ; RV32-NEXT: PseudoRET implicit $v8m2 1686 ; 1687 ; RV64-LABEL: name: insertelement_nxv2i64_2 1688 ; RV64: bb.1 (%ir-block.0): 1689 ; RV64-NEXT: liveins: $x10 1690 ; RV64-NEXT: {{ $}} 1691 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1692 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF 1693 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1694 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) 1695 ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) 1696 ; RV64-NEXT: PseudoRET implicit $v8m2 1697 %a = insertelement <vscale x 2 x i64> poison, i64 %x, i32 0 1698 ret <vscale x 2 x i64> %a 1699} 1700 1701define <vscale x 4 x i64> @insertelement_nxv4i64_0() { 1702 ; RV32-LABEL: name: insertelement_nxv4i64_0 1703 ; RV32: bb.1 (%ir-block.0): 1704 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF 1705 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1706 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1707 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1708 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1709 ; RV32-NEXT: PseudoRET implicit $v8m4 1710 ; 1711 ; RV64-LABEL: name: insertelement_nxv4i64_0 1712 ; RV64: bb.1 (%ir-block.0): 1713 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF 1714 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1715 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) 1716 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1717 ; RV64-NEXT: PseudoRET implicit $v8m4 1718 %a = insertelement <vscale x 4 x i64> poison, i64 0, i32 0 1719 ret <vscale x 4 x i64> %a 1720} 1721 1722define <vscale x 4 x i64> @insertelement_nxv4i64_1() { 1723 ; RV32-LABEL: name: insertelement_nxv4i64_1 1724 ; RV32: bb.1 (%ir-block.0): 1725 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF 1726 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1727 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1728 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1729 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1730 ; RV32-NEXT: PseudoRET implicit $v8m4 1731 ; 1732 ; RV64-LABEL: name: insertelement_nxv4i64_1 1733 ; RV64: bb.1 (%ir-block.0): 1734 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF 1735 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1736 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1737 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) 1738 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1739 ; RV64-NEXT: PseudoRET implicit $v8m4 1740 %a = insertelement <vscale x 4 x i64> poison, i64 -1, i32 0 1741 ret <vscale x 4 x i64> %a 1742} 1743 1744define <vscale x 4 x i64> @insertelement_nxv4i64_2(i64 %x) { 1745 ; RV32-LABEL: name: insertelement_nxv4i64_2 1746 ; RV32: bb.1 (%ir-block.0): 1747 ; RV32-NEXT: liveins: $x10, $x11 1748 ; RV32-NEXT: {{ $}} 1749 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1750 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 1751 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 1752 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF 1753 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1754 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) 1755 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1756 ; RV32-NEXT: PseudoRET implicit $v8m4 1757 ; 1758 ; RV64-LABEL: name: insertelement_nxv4i64_2 1759 ; RV64: bb.1 (%ir-block.0): 1760 ; RV64-NEXT: liveins: $x10 1761 ; RV64-NEXT: {{ $}} 1762 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1763 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF 1764 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1765 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) 1766 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1767 ; RV64-NEXT: PseudoRET implicit $v8m4 1768 %a = insertelement <vscale x 4 x i64> poison, i64 %x, i32 0 1769 ret <vscale x 4 x i64> %a 1770} 1771 1772define <vscale x 8 x i64> @insertelement_nxv8i64_0() { 1773 ; RV32-LABEL: name: insertelement_nxv8i64_0 1774 ; RV32: bb.1 (%ir-block.0): 1775 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF 1776 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1777 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1778 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1779 ; RV32-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) 1780 ; RV32-NEXT: PseudoRET implicit $v8m8 1781 ; 1782 ; RV64-LABEL: name: insertelement_nxv8i64_0 1783 ; RV64: bb.1 (%ir-block.0): 1784 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF 1785 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1786 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) 1787 ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) 1788 ; RV64-NEXT: PseudoRET implicit $v8m8 1789 %a = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 1790 ret <vscale x 8 x i64> %a 1791} 1792 1793define <vscale x 8 x i64> @insertelement_nxv8i64_1() { 1794 ; RV32-LABEL: name: insertelement_nxv8i64_1 1795 ; RV32: bb.1 (%ir-block.0): 1796 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF 1797 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1798 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1799 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1800 ; RV32-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) 1801 ; RV32-NEXT: PseudoRET implicit $v8m8 1802 ; 1803 ; RV64-LABEL: name: insertelement_nxv8i64_1 1804 ; RV64: bb.1 (%ir-block.0): 1805 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF 1806 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1807 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1808 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) 1809 ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) 1810 ; RV64-NEXT: PseudoRET implicit $v8m8 1811 %a = insertelement <vscale x 8 x i64> poison, i64 -1, i32 0 1812 ret <vscale x 8 x i64> %a 1813} 1814 1815define <vscale x 8 x i64> @insertelement_nxv8i64_2(i64 %x) { 1816 ; RV32-LABEL: name: insertelement_nxv8i64_2 1817 ; RV32: bb.1 (%ir-block.0): 1818 ; RV32-NEXT: liveins: $x10, $x11 1819 ; RV32-NEXT: {{ $}} 1820 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1821 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 1822 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 1823 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF 1824 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1825 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) 1826 ; RV32-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) 1827 ; RV32-NEXT: PseudoRET implicit $v8m8 1828 ; 1829 ; RV64-LABEL: name: insertelement_nxv8i64_2 1830 ; RV64: bb.1 (%ir-block.0): 1831 ; RV64-NEXT: liveins: $x10 1832 ; RV64-NEXT: {{ $}} 1833 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1834 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF 1835 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1836 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) 1837 ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) 1838 ; RV64-NEXT: PseudoRET implicit $v8m8 1839 %a = insertelement <vscale x 8 x i64> poison, i64 %x, i32 0 1840 ret <vscale x 8 x i64> %a 1841} 1842 1843define <vscale x 16 x i64> @insertelement_nxv16i64_0() { 1844 ; RV32-LABEL: name: insertelement_nxv16i64_0 1845 ; RV32: bb.1 (%ir-block.0): 1846 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF 1847 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1848 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1849 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1850 ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) 1851 ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) 1852 ; RV32-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) 1853 ; RV32-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 1854 ; 1855 ; RV64-LABEL: name: insertelement_nxv16i64_0 1856 ; RV64: bb.1 (%ir-block.0): 1857 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF 1858 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1859 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) 1860 ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) 1861 ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) 1862 ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) 1863 ; RV64-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 1864 %a = insertelement <vscale x 16 x i64> poison, i64 0, i32 0 1865 ret <vscale x 16 x i64> %a 1866} 1867 1868define <vscale x 16 x i64> @insertelement_nxv16i64_1() { 1869 ; RV32-LABEL: name: insertelement_nxv16i64_1 1870 ; RV32: bb.1 (%ir-block.0): 1871 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF 1872 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1873 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1874 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) 1875 ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) 1876 ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) 1877 ; RV32-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) 1878 ; RV32-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 1879 ; 1880 ; RV64-LABEL: name: insertelement_nxv16i64_1 1881 ; RV64: bb.1 (%ir-block.0): 1882 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF 1883 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1884 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1885 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) 1886 ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) 1887 ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) 1888 ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) 1889 ; RV64-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 1890 %a = insertelement <vscale x 16 x i64> poison, i64 -1, i32 0 1891 ret <vscale x 16 x i64> %a 1892} 1893 1894define <vscale x 16 x i64> @insertelement_nxv16i64_2(i64 %x) { 1895 ; RV32-LABEL: name: insertelement_nxv16i64_2 1896 ; RV32: bb.1 (%ir-block.0): 1897 ; RV32-NEXT: liveins: $x10, $x11 1898 ; RV32-NEXT: {{ $}} 1899 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 1900 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 1901 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 1902 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF 1903 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1904 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) 1905 ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) 1906 ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) 1907 ; RV32-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) 1908 ; RV32-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 1909 ; 1910 ; RV64-LABEL: name: insertelement_nxv16i64_2 1911 ; RV64: bb.1 (%ir-block.0): 1912 ; RV64-NEXT: liveins: $x10 1913 ; RV64-NEXT: {{ $}} 1914 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 1915 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF 1916 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1917 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) 1918 ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) 1919 ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) 1920 ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) 1921 ; RV64-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 1922 %a = insertelement <vscale x 16 x i64> poison, i64 %x, i32 0 1923 ret <vscale x 16 x i64> %a 1924} 1925 1926define <vscale x 4 x i64> @insertelement_nxv4i64(<vscale x 4 x i64> %v, i64 %x) { 1927 ; RV32-LABEL: name: insertelement_nxv4i64 1928 ; RV32: bb.1 (%ir-block.0): 1929 ; RV32-NEXT: liveins: $x10, $x11, $v8m4 1930 ; RV32-NEXT: {{ $}} 1931 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4 1932 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 1933 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11 1934 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) 1935 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 1936 ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[MV]](s64), [[C]](s32) 1937 ; RV32-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1938 ; RV32-NEXT: PseudoRET implicit $v8m4 1939 ; 1940 ; RV64-LABEL: name: insertelement_nxv4i64 1941 ; RV64: bb.1 (%ir-block.0): 1942 ; RV64-NEXT: liveins: $x10, $v8m4 1943 ; RV64-NEXT: {{ $}} 1944 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4 1945 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 1946 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 1947 ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s64), [[C]](s64) 1948 ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) 1949 ; RV64-NEXT: PseudoRET implicit $v8m4 1950 %a = insertelement <vscale x 4 x i64> %v, i64 %x, i32 0 1951 ret <vscale x 4 x i64> %a 1952} 1953