1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \ 3; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \ 4; RUN: | FileCheck -check-prefixes=RV32-ILP32FD,RV32-ILP32F %s 5; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ 6; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \ 7; RUN: | FileCheck -check-prefixes=RV32-ILP32FD,RV32-ILP32D %s 8 9; This file contains tests that should have identical output for the ilp32f 10; and ilp32d ABIs. 11 12define i32 @callee_float_in_fpr(i32 %a, float %b) nounwind { 13 ; RV32-ILP32FD-LABEL: name: callee_float_in_fpr 14 ; RV32-ILP32FD: bb.1 (%ir-block.0): 15 ; RV32-ILP32FD-NEXT: liveins: $x10, $f10_f 16 ; RV32-ILP32FD-NEXT: {{ $}} 17 ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 18 ; RV32-ILP32FD-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f 19 ; RV32-ILP32FD-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY1]](s32) 20 ; RV32-ILP32FD-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[FPTOSI]] 21 ; RV32-ILP32FD-NEXT: $x10 = COPY [[ADD]](s32) 22 ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10 23 %b_fptosi = fptosi float %b to i32 24 %1 = add i32 %a, %b_fptosi 25 ret i32 %1 26} 27 28define i32 @caller_float_in_fpr() nounwind { 29 ; RV32-ILP32F-LABEL: name: caller_float_in_fpr 30 ; RV32-ILP32F: bb.1 (%ir-block.0): 31 ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 32 ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 33 ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 34 ; RV32-ILP32F-NEXT: $x10 = COPY [[C]](s32) 35 ; RV32-ILP32F-NEXT: $f10_f = COPY [[C1]](s32) 36 ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10 37 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 38 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 39 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32) 40 ; RV32-ILP32F-NEXT: PseudoRET implicit $x10 41 ; 42 ; RV32-ILP32D-LABEL: name: caller_float_in_fpr 43 ; RV32-ILP32D: bb.1 (%ir-block.0): 44 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 45 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 46 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 47 ; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32) 48 ; RV32-ILP32D-NEXT: $f10_f = COPY [[C1]](s32) 49 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10 50 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 51 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 52 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) 53 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10 54 %1 = call i32 @callee_float_in_fpr(i32 1, float 2.0) 55 ret i32 %1 56} 57 58; Must keep define on a single line due to an update_llc_test_checks.py limitation 59define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind { 60 ; RV32-ILP32FD-LABEL: name: callee_float_in_fpr_exhausted_gprs 61 ; RV32-ILP32FD: bb.1 (%ir-block.0): 62 ; RV32-ILP32FD-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f 63 ; RV32-ILP32FD-NEXT: {{ $}} 64 ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 65 ; RV32-ILP32FD-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 66 ; RV32-ILP32FD-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 67 ; RV32-ILP32FD-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 68 ; RV32-ILP32FD-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 69 ; RV32-ILP32FD-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 70 ; RV32-ILP32FD-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 71 ; RV32-ILP32FD-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 72 ; RV32-ILP32FD-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) 73 ; RV32-ILP32FD-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 74 ; RV32-ILP32FD-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 75 ; RV32-ILP32FD-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) 76 ; RV32-ILP32FD-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 77 ; RV32-ILP32FD-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16) 78 ; RV32-ILP32FD-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $f10_f 79 ; RV32-ILP32FD-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY8]](s32) 80 ; RV32-ILP32FD-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[FPTOSI]] 81 ; RV32-ILP32FD-NEXT: $x10 = COPY [[ADD]](s32) 82 ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10 83 %f_fptosi = fptosi float %f to i32 84 %1 = add i32 %e, %f_fptosi 85 ret i32 %1 86} 87 88define i32 @caller_float_in_fpr_exhausted_gprs() nounwind { 89 ; RV32-ILP32F-LABEL: name: caller_float_in_fpr_exhausted_gprs 90 ; RV32-ILP32F: bb.1 (%ir-block.0): 91 ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 92 ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 93 ; RV32-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 94 ; RV32-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 95 ; RV32-ILP32F-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 96 ; RV32-ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00 97 ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2 98 ; RV32-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) 99 ; RV32-ILP32F-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64) 100 ; RV32-ILP32F-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64) 101 ; RV32-ILP32F-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64) 102 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2 103 ; RV32-ILP32F-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 104 ; RV32-ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32) 105 ; RV32-ILP32F-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) 106 ; RV32-ILP32F-NEXT: $x10 = COPY [[UV]](s32) 107 ; RV32-ILP32F-NEXT: $x11 = COPY [[UV1]](s32) 108 ; RV32-ILP32F-NEXT: $x12 = COPY [[UV2]](s32) 109 ; RV32-ILP32F-NEXT: $x13 = COPY [[UV3]](s32) 110 ; RV32-ILP32F-NEXT: $x14 = COPY [[UV4]](s32) 111 ; RV32-ILP32F-NEXT: $x15 = COPY [[UV5]](s32) 112 ; RV32-ILP32F-NEXT: $x16 = COPY [[UV6]](s32) 113 ; RV32-ILP32F-NEXT: $x17 = COPY [[UV7]](s32) 114 ; RV32-ILP32F-NEXT: $f10_f = COPY [[C5]](s32) 115 ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10 116 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 117 ; RV32-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 118 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY1]](s32) 119 ; RV32-ILP32F-NEXT: PseudoRET implicit $x10 120 ; 121 ; RV32-ILP32D-LABEL: name: caller_float_in_fpr_exhausted_gprs 122 ; RV32-ILP32D: bb.1 (%ir-block.0): 123 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 124 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 125 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 126 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 127 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 128 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00 129 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2 130 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) 131 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64) 132 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64) 133 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64) 134 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2 135 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 136 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32) 137 ; RV32-ILP32D-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) 138 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32) 139 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32) 140 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32) 141 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32) 142 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32) 143 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32) 144 ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32) 145 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32) 146 ; RV32-ILP32D-NEXT: $f10_f = COPY [[C5]](s32) 147 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10 148 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 149 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 150 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) 151 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10 152 %1 = call i32 @callee_float_in_fpr_exhausted_gprs( 153 i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0) 154 ret i32 %1 155} 156 157; Must keep define on a single line due to an update_llc_test_checks.py limitation 158define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind { 159 ; RV32-ILP32FD-LABEL: name: callee_float_in_gpr_exhausted_fprs 160 ; RV32-ILP32FD: bb.1 (%ir-block.0): 161 ; RV32-ILP32FD-NEXT: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f 162 ; RV32-ILP32FD-NEXT: {{ $}} 163 ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f 164 ; RV32-ILP32FD-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f 165 ; RV32-ILP32FD-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f 166 ; RV32-ILP32FD-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f 167 ; RV32-ILP32FD-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f 168 ; RV32-ILP32FD-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f 169 ; RV32-ILP32FD-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f 170 ; RV32-ILP32FD-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f 171 ; RV32-ILP32FD-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10 172 ; RV32-ILP32FD-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY7]](s32) 173 ; RV32-ILP32FD-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY8]](s32) 174 ; RV32-ILP32FD-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOSI]], [[FPTOSI1]] 175 ; RV32-ILP32FD-NEXT: $x10 = COPY [[ADD]](s32) 176 ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10 177 %h_fptosi = fptosi float %h to i32 178 %i_fptosi = fptosi float %i to i32 179 %1 = add i32 %h_fptosi, %i_fptosi 180 ret i32 %1 181} 182 183define i32 @caller_float_in_gpr_exhausted_fprs() nounwind { 184 ; RV32-ILP32F-LABEL: name: caller_float_in_gpr_exhausted_fprs 185 ; RV32-ILP32F: bb.1 (%ir-block.0): 186 ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 187 ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 188 ; RV32-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+00 189 ; RV32-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00 190 ; RV32-ILP32F-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+00 191 ; RV32-ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00 192 ; RV32-ILP32F-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+00 193 ; RV32-ILP32F-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00 194 ; RV32-ILP32F-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00 195 ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 196 ; RV32-ILP32F-NEXT: $f10_f = COPY [[C]](s32) 197 ; RV32-ILP32F-NEXT: $f11_f = COPY [[C1]](s32) 198 ; RV32-ILP32F-NEXT: $f12_f = COPY [[C2]](s32) 199 ; RV32-ILP32F-NEXT: $f13_f = COPY [[C3]](s32) 200 ; RV32-ILP32F-NEXT: $f14_f = COPY [[C4]](s32) 201 ; RV32-ILP32F-NEXT: $f15_f = COPY [[C5]](s32) 202 ; RV32-ILP32F-NEXT: $f16_f = COPY [[C6]](s32) 203 ; RV32-ILP32F-NEXT: $f17_f = COPY [[C7]](s32) 204 ; RV32-ILP32F-NEXT: $x10 = COPY [[C8]](s32) 205 ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10 206 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 207 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 208 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32) 209 ; RV32-ILP32F-NEXT: PseudoRET implicit $x10 210 ; 211 ; RV32-ILP32D-LABEL: name: caller_float_in_gpr_exhausted_fprs 212 ; RV32-ILP32D: bb.1 (%ir-block.0): 213 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 214 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 215 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+00 216 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00 217 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+00 218 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00 219 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+00 220 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00 221 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00 222 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 223 ; RV32-ILP32D-NEXT: $f10_f = COPY [[C]](s32) 224 ; RV32-ILP32D-NEXT: $f11_f = COPY [[C1]](s32) 225 ; RV32-ILP32D-NEXT: $f12_f = COPY [[C2]](s32) 226 ; RV32-ILP32D-NEXT: $f13_f = COPY [[C3]](s32) 227 ; RV32-ILP32D-NEXT: $f14_f = COPY [[C4]](s32) 228 ; RV32-ILP32D-NEXT: $f15_f = COPY [[C5]](s32) 229 ; RV32-ILP32D-NEXT: $f16_f = COPY [[C6]](s32) 230 ; RV32-ILP32D-NEXT: $f17_f = COPY [[C7]](s32) 231 ; RV32-ILP32D-NEXT: $x10 = COPY [[C8]](s32) 232 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10 233 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 234 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 235 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) 236 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10 237 %1 = call i32 @callee_float_in_gpr_exhausted_fprs( 238 float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, 239 float 7.0, float 8.0, float 9.0) 240 ret i32 %1 241} 242 243; Must keep define on a single line due to an update_llc_test_checks.py limitation 244define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind { 245 ; RV32-ILP32FD-LABEL: name: callee_float_on_stack_exhausted_gprs_fprs 246 ; RV32-ILP32FD: bb.1 (%ir-block.0): 247 ; RV32-ILP32FD-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f 248 ; RV32-ILP32FD-NEXT: {{ $}} 249 ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 250 ; RV32-ILP32FD-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 251 ; RV32-ILP32FD-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 252 ; RV32-ILP32FD-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f 253 ; RV32-ILP32FD-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x12 254 ; RV32-ILP32FD-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x13 255 ; RV32-ILP32FD-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32) 256 ; RV32-ILP32FD-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f11_f 257 ; RV32-ILP32FD-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x14 258 ; RV32-ILP32FD-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x15 259 ; RV32-ILP32FD-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) 260 ; RV32-ILP32FD-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $f12_f 261 ; RV32-ILP32FD-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x16 262 ; RV32-ILP32FD-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x17 263 ; RV32-ILP32FD-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32) 264 ; RV32-ILP32FD-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $f13_f 265 ; RV32-ILP32FD-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $f14_f 266 ; RV32-ILP32FD-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $f15_f 267 ; RV32-ILP32FD-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $f16_f 268 ; RV32-ILP32FD-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $f17_f 269 ; RV32-ILP32FD-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 270 ; RV32-ILP32FD-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16) 271 ; RV32-ILP32FD-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s64) 272 ; RV32-ILP32FD-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[LOAD]](s32) 273 ; RV32-ILP32FD-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[FPTOSI]] 274 ; RV32-ILP32FD-NEXT: $x10 = COPY [[ADD]](s32) 275 ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10 276 %g_trunc = trunc i64 %g to i32 277 %m_fptosi = fptosi float %m to i32 278 %1 = add i32 %g_trunc, %m_fptosi 279 ret i32 %1 280} 281 282define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind { 283 ; RV32-ILP32F-LABEL: name: caller_float_on_stack_exhausted_gprs_fprs 284 ; RV32-ILP32F: bb.1 (%ir-block.0): 285 ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 286 ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 287 ; RV32-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 288 ; RV32-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00 289 ; RV32-ILP32F-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 290 ; RV32-ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00 291 ; RV32-ILP32F-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 292 ; RV32-ILP32F-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00 293 ; RV32-ILP32F-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00 294 ; RV32-ILP32F-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01 295 ; RV32-ILP32F-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01 296 ; RV32-ILP32F-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01 297 ; RV32-ILP32F-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01 298 ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2 299 ; RV32-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) 300 ; RV32-ILP32F-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64) 301 ; RV32-ILP32F-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) 302 ; RV32-ILP32F-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) 303 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2 304 ; RV32-ILP32F-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 305 ; RV32-ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32) 306 ; RV32-ILP32F-NEXT: G_STORE [[C12]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) 307 ; RV32-ILP32F-NEXT: $x10 = COPY [[UV]](s32) 308 ; RV32-ILP32F-NEXT: $x11 = COPY [[UV1]](s32) 309 ; RV32-ILP32F-NEXT: $f10_f = COPY [[C1]](s32) 310 ; RV32-ILP32F-NEXT: $x12 = COPY [[UV2]](s32) 311 ; RV32-ILP32F-NEXT: $x13 = COPY [[UV3]](s32) 312 ; RV32-ILP32F-NEXT: $f11_f = COPY [[C3]](s32) 313 ; RV32-ILP32F-NEXT: $x14 = COPY [[UV4]](s32) 314 ; RV32-ILP32F-NEXT: $x15 = COPY [[UV5]](s32) 315 ; RV32-ILP32F-NEXT: $f12_f = COPY [[C5]](s32) 316 ; RV32-ILP32F-NEXT: $x16 = COPY [[UV6]](s32) 317 ; RV32-ILP32F-NEXT: $x17 = COPY [[UV7]](s32) 318 ; RV32-ILP32F-NEXT: $f13_f = COPY [[C7]](s32) 319 ; RV32-ILP32F-NEXT: $f14_f = COPY [[C8]](s32) 320 ; RV32-ILP32F-NEXT: $f15_f = COPY [[C9]](s32) 321 ; RV32-ILP32F-NEXT: $f16_f = COPY [[C10]](s32) 322 ; RV32-ILP32F-NEXT: $f17_f = COPY [[C11]](s32) 323 ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10 324 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 325 ; RV32-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 326 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY1]](s32) 327 ; RV32-ILP32F-NEXT: PseudoRET implicit $x10 328 ; 329 ; RV32-ILP32D-LABEL: name: caller_float_on_stack_exhausted_gprs_fprs 330 ; RV32-ILP32D: bb.1 (%ir-block.0): 331 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 332 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 333 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 334 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00 335 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 336 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00 337 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 338 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00 339 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00 340 ; RV32-ILP32D-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01 341 ; RV32-ILP32D-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01 342 ; RV32-ILP32D-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01 343 ; RV32-ILP32D-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01 344 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2 345 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) 346 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64) 347 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) 348 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) 349 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2 350 ; RV32-ILP32D-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 351 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32) 352 ; RV32-ILP32D-NEXT: G_STORE [[C12]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) 353 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32) 354 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32) 355 ; RV32-ILP32D-NEXT: $f10_f = COPY [[C1]](s32) 356 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32) 357 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32) 358 ; RV32-ILP32D-NEXT: $f11_f = COPY [[C3]](s32) 359 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32) 360 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32) 361 ; RV32-ILP32D-NEXT: $f12_f = COPY [[C5]](s32) 362 ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32) 363 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32) 364 ; RV32-ILP32D-NEXT: $f13_f = COPY [[C7]](s32) 365 ; RV32-ILP32D-NEXT: $f14_f = COPY [[C8]](s32) 366 ; RV32-ILP32D-NEXT: $f15_f = COPY [[C9]](s32) 367 ; RV32-ILP32D-NEXT: $f16_f = COPY [[C10]](s32) 368 ; RV32-ILP32D-NEXT: $f17_f = COPY [[C11]](s32) 369 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10 370 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2 371 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 372 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32) 373 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10 374 %1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs( 375 i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0, 376 float 9.0, float 10.0, float 11.0, float 12.0, float 13.0) 377 ret i32 %1 378} 379 380define float @callee_float_ret() nounwind { 381 ; RV32-ILP32FD-LABEL: name: callee_float_ret 382 ; RV32-ILP32FD: bb.1 (%ir-block.0): 383 ; RV32-ILP32FD-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 384 ; RV32-ILP32FD-NEXT: $f10_f = COPY [[C]](s32) 385 ; RV32-ILP32FD-NEXT: PseudoRET implicit $f10_f 386 ret float 1.0 387} 388 389define i32 @caller_float_ret() nounwind { 390 ; RV32-ILP32F-LABEL: name: caller_float_ret 391 ; RV32-ILP32F: bb.1 (%ir-block.0): 392 ; RV32-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 393 ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $f10_f 394 ; RV32-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 395 ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f 396 ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32) 397 ; RV32-ILP32F-NEXT: PseudoRET implicit $x10 398 ; 399 ; RV32-ILP32D-LABEL: name: caller_float_ret 400 ; RV32-ILP32D: bb.1 (%ir-block.0): 401 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 402 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_f 403 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 404 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f 405 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32) 406 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10 407 %1 = call float @callee_float_ret() 408 %2 = bitcast float %1 to i32 409 ret i32 %2 410} 411