xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir (revision d365a45cb3eaa640b09874fb7984a6a69683c773) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
3# RUN:   -verify-machineinstrs %s -o - | FileCheck %s
4# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
5# RUN:   -verify-machineinstrs %s -o - | FileCheck %s
6
7---
8name:            test_trap
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12body:             |
13  bb.1:
14    ; CHECK-LABEL: name: test_trap
15    ; CHECK: UNIMP
16    ; CHECK-NEXT: PseudoRET
17    G_TRAP
18    PseudoRET
19
20...
21---
22name:            test_debugtrap
23legalized:       true
24regBankSelected: true
25tracksRegLiveness: true
26body:             |
27  bb.1:
28    ; CHECK-LABEL: name: test_debugtrap
29    ; CHECK: EBREAK
30    ; CHECK-NEXT: PseudoRET
31    G_DEBUGTRAP
32    PseudoRET
33
34...
35