1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s 3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s 4 5# Don't test i1 element types here since they have been widened to i8 in legalization 6 7--- 8name: icmp_nxv1i8 9legalized: true 10regBankSelected: true 11tracksRegLiveness: true 12body: | 13 bb.0.entry: 14 ; RV32I-LABEL: name: icmp_nxv1i8 15 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 16 ; RV32I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */ 17 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] 18 ; RV32I-NEXT: PseudoRET implicit $v8 19 ; 20 ; RV64I-LABEL: name: icmp_nxv1i8 21 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 22 ; RV64I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */ 23 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] 24 ; RV64I-NEXT: PseudoRET implicit $v8 25 %0:vrb(<vscale x 1 x s8>) = G_IMPLICIT_DEF 26 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(ult), %0(<vscale x 1 x s8>), %0 27 $v8 = COPY %1(<vscale x 1 x s1>) 28 PseudoRET implicit $v8 29 30... 31--- 32name: icmp_nxv2i8 33legalized: true 34regBankSelected: true 35tracksRegLiveness: true 36body: | 37 bb.0.entry: 38 ; RV32I-LABEL: name: icmp_nxv2i8 39 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 40 ; RV32I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */ 41 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] 42 ; RV32I-NEXT: PseudoRET implicit $v8 43 ; 44 ; RV64I-LABEL: name: icmp_nxv2i8 45 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 46 ; RV64I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */ 47 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] 48 ; RV64I-NEXT: PseudoRET implicit $v8 49 %0:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF 50 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(slt), %0(<vscale x 2 x s8>), %0 51 $v8 = COPY %1(<vscale x 2 x s1>) 52 PseudoRET implicit $v8 53 54... 55--- 56name: icmp_nxv4i8 57legalized: true 58regBankSelected: true 59tracksRegLiveness: true 60body: | 61 bb.0.entry: 62 ; RV32I-LABEL: name: icmp_nxv4i8 63 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 64 ; RV32I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */ 65 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] 66 ; RV32I-NEXT: PseudoRET implicit $v8 67 ; 68 ; RV64I-LABEL: name: icmp_nxv4i8 69 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 70 ; RV64I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */ 71 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] 72 ; RV64I-NEXT: PseudoRET implicit $v8 73 %0:vrb(<vscale x 4 x s8>) = G_IMPLICIT_DEF 74 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(uge), %0(<vscale x 4 x s8>), %0 75 $v8 = COPY %1(<vscale x 4 x s1>) 76 PseudoRET implicit $v8 77 78... 79--- 80name: icmp_nxv8i8 81legalized: true 82regBankSelected: true 83tracksRegLiveness: true 84body: | 85 bb.0.entry: 86 ; RV32I-LABEL: name: icmp_nxv8i8 87 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 88 ; RV32I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */ 89 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] 90 ; RV32I-NEXT: PseudoRET implicit $v8 91 ; 92 ; RV64I-LABEL: name: icmp_nxv8i8 93 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 94 ; RV64I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */ 95 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] 96 ; RV64I-NEXT: PseudoRET implicit $v8 97 %0:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF 98 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sge), %0(<vscale x 8 x s8>), %0 99 $v8 = COPY %1(<vscale x 8 x s1>) 100 PseudoRET implicit $v8 101 102... 103--- 104name: icmp_nxv16i8 105legalized: true 106regBankSelected: true 107tracksRegLiveness: true 108body: | 109 bb.0.entry: 110 ; RV32I-LABEL: name: icmp_nxv16i8 111 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 112 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */ 113 ; RV32I-NEXT: $v8 = COPY %1 114 ; RV32I-NEXT: PseudoRET implicit $v8 115 ; 116 ; RV64I-LABEL: name: icmp_nxv16i8 117 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 118 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */ 119 ; RV64I-NEXT: $v8 = COPY %1 120 ; RV64I-NEXT: PseudoRET implicit $v8 121 %0:vrb(<vscale x 16 x s8>) = G_IMPLICIT_DEF 122 %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(ugt), %0(<vscale x 16 x s8>), %0 123 $v8 = COPY %1(<vscale x 16 x s1>) 124 PseudoRET implicit $v8 125 126... 127--- 128name: icmp_nxv32i8 129legalized: true 130regBankSelected: true 131tracksRegLiveness: true 132body: | 133 bb.0.entry: 134 ; RV32I-LABEL: name: icmp_nxv32i8 135 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 136 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */ 137 ; RV32I-NEXT: $v8 = COPY %1 138 ; RV32I-NEXT: PseudoRET implicit $v8 139 ; 140 ; RV64I-LABEL: name: icmp_nxv32i8 141 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 142 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */ 143 ; RV64I-NEXT: $v8 = COPY %1 144 ; RV64I-NEXT: PseudoRET implicit $v8 145 %0:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF 146 %1:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 32 x s8>), %0 147 $v8 = COPY %1(<vscale x 32 x s1>) 148 PseudoRET implicit $v8 149 150... 151--- 152name: icmp_nxv64i8 153legalized: true 154regBankSelected: true 155tracksRegLiveness: true 156body: | 157 bb.0.entry: 158 ; RV32I-LABEL: name: icmp_nxv64i8 159 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 160 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */ 161 ; RV32I-NEXT: $v8 = COPY %1 162 ; RV32I-NEXT: PseudoRET implicit $v8 163 ; 164 ; RV64I-LABEL: name: icmp_nxv64i8 165 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 166 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */ 167 ; RV64I-NEXT: $v8 = COPY %1 168 ; RV64I-NEXT: PseudoRET implicit $v8 169 %0:vrb(<vscale x 64 x s8>) = G_IMPLICIT_DEF 170 %1:vrb(<vscale x 64 x s1>) = G_ICMP intpred(ule), %0(<vscale x 64 x s8>), %0 171 $v8 = COPY %1(<vscale x 64 x s1>) 172 PseudoRET implicit $v8 173 174... 175--- 176name: icmp_nxv1i16 177legalized: true 178regBankSelected: true 179tracksRegLiveness: true 180body: | 181 bb.0.entry: 182 ; RV32I-LABEL: name: icmp_nxv1i16 183 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 184 ; RV32I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */ 185 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] 186 ; RV32I-NEXT: PseudoRET implicit $v8 187 ; 188 ; RV64I-LABEL: name: icmp_nxv1i16 189 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 190 ; RV64I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */ 191 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] 192 ; RV64I-NEXT: PseudoRET implicit $v8 193 %0:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF 194 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sle), %0(<vscale x 1 x s16>), %0 195 $v8 = COPY %1(<vscale x 1 x s1>) 196 PseudoRET implicit $v8 197 198... 199--- 200name: icmp_nxv2i16 201legalized: true 202regBankSelected: true 203tracksRegLiveness: true 204body: | 205 bb.0.entry: 206 ; RV32I-LABEL: name: icmp_nxv2i16 207 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 208 ; RV32I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */ 209 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] 210 ; RV32I-NEXT: PseudoRET implicit $v8 211 ; 212 ; RV64I-LABEL: name: icmp_nxv2i16 213 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 214 ; RV64I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */ 215 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] 216 ; RV64I-NEXT: PseudoRET implicit $v8 217 %0:vrb(<vscale x 2 x s16>) = G_IMPLICIT_DEF 218 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ne), %0(<vscale x 2 x s16>), %0 219 $v8 = COPY %1(<vscale x 2 x s1>) 220 PseudoRET implicit $v8 221 222... 223--- 224name: icmp_nxv4i16 225legalized: true 226regBankSelected: true 227tracksRegLiveness: true 228body: | 229 bb.0.entry: 230 ; RV32I-LABEL: name: icmp_nxv4i16 231 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 232 ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */ 233 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] 234 ; RV32I-NEXT: PseudoRET implicit $v8 235 ; 236 ; RV64I-LABEL: name: icmp_nxv4i16 237 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 238 ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */ 239 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] 240 ; RV64I-NEXT: PseudoRET implicit $v8 241 %0:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF 242 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(eq), %0(<vscale x 4 x s16>), %0 243 $v8 = COPY %1(<vscale x 4 x s1>) 244 PseudoRET implicit $v8 245 246... 247--- 248name: icmp_nxv8i16 249legalized: true 250regBankSelected: true 251tracksRegLiveness: true 252body: | 253 bb.0.entry: 254 ; RV32I-LABEL: name: icmp_nxv8i16 255 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 256 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */ 257 ; RV32I-NEXT: $v8 = COPY %1 258 ; RV32I-NEXT: PseudoRET implicit $v8 259 ; 260 ; RV64I-LABEL: name: icmp_nxv8i16 261 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 262 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */ 263 ; RV64I-NEXT: $v8 = COPY %1 264 ; RV64I-NEXT: PseudoRET implicit $v8 265 %0:vrb(<vscale x 8 x s16>) = G_IMPLICIT_DEF 266 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ult), %0(<vscale x 8 x s16>), %0 267 $v8 = COPY %1(<vscale x 8 x s1>) 268 PseudoRET implicit $v8 269 270... 271--- 272name: icmp_nxv16i16 273legalized: true 274regBankSelected: true 275tracksRegLiveness: true 276body: | 277 bb.0.entry: 278 ; RV32I-LABEL: name: icmp_nxv16i16 279 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 280 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */ 281 ; RV32I-NEXT: $v8 = COPY %1 282 ; RV32I-NEXT: PseudoRET implicit $v8 283 ; 284 ; RV64I-LABEL: name: icmp_nxv16i16 285 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 286 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */ 287 ; RV64I-NEXT: $v8 = COPY %1 288 ; RV64I-NEXT: PseudoRET implicit $v8 289 %0:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF 290 %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(slt), %0(<vscale x 16 x s16>), %0 291 $v8 = COPY %1(<vscale x 16 x s1>) 292 PseudoRET implicit $v8 293 294... 295--- 296name: icmp_nxv32i16 297legalized: true 298regBankSelected: true 299tracksRegLiveness: true 300body: | 301 bb.0.entry: 302 ; RV32I-LABEL: name: icmp_nxv32i16 303 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 304 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */ 305 ; RV32I-NEXT: $v8 = COPY %1 306 ; RV32I-NEXT: PseudoRET implicit $v8 307 ; 308 ; RV64I-LABEL: name: icmp_nxv32i16 309 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 310 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */ 311 ; RV64I-NEXT: $v8 = COPY %1 312 ; RV64I-NEXT: PseudoRET implicit $v8 313 %0:vrb(<vscale x 32 x s16>) = G_IMPLICIT_DEF 314 %1:vrb(<vscale x 32 x s1>) = G_ICMP intpred(uge), %0(<vscale x 32 x s16>), %0 315 $v8 = COPY %1(<vscale x 32 x s1>) 316 PseudoRET implicit $v8 317 318... 319--- 320name: icmp_nxv1i32 321legalized: true 322regBankSelected: true 323tracksRegLiveness: true 324body: | 325 bb.0.entry: 326 ; RV32I-LABEL: name: icmp_nxv1i32 327 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 328 ; RV32I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */ 329 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] 330 ; RV32I-NEXT: PseudoRET implicit $v8 331 ; 332 ; RV64I-LABEL: name: icmp_nxv1i32 333 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 334 ; RV64I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */ 335 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] 336 ; RV64I-NEXT: PseudoRET implicit $v8 337 %0:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF 338 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sge), %0(<vscale x 1 x s32>), %0 339 $v8 = COPY %1(<vscale x 1 x s1>) 340 PseudoRET implicit $v8 341 342... 343--- 344name: icmp_nxv2i32 345legalized: true 346regBankSelected: true 347tracksRegLiveness: true 348body: | 349 bb.0.entry: 350 ; RV32I-LABEL: name: icmp_nxv2i32 351 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 352 ; RV32I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */ 353 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] 354 ; RV32I-NEXT: PseudoRET implicit $v8 355 ; 356 ; RV64I-LABEL: name: icmp_nxv2i32 357 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 358 ; RV64I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */ 359 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] 360 ; RV64I-NEXT: PseudoRET implicit $v8 361 %0:vrb(<vscale x 2 x s32>) = G_IMPLICIT_DEF 362 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ugt), %0(<vscale x 2 x s32>), %0 363 $v8 = COPY %1(<vscale x 2 x s1>) 364 PseudoRET implicit $v8 365 366... 367--- 368name: icmp_nxv4i32 369legalized: true 370regBankSelected: true 371tracksRegLiveness: true 372body: | 373 bb.0.entry: 374 ; RV32I-LABEL: name: icmp_nxv4i32 375 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 376 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */ 377 ; RV32I-NEXT: $v8 = COPY %1 378 ; RV32I-NEXT: PseudoRET implicit $v8 379 ; 380 ; RV64I-LABEL: name: icmp_nxv4i32 381 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 382 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */ 383 ; RV64I-NEXT: $v8 = COPY %1 384 ; RV64I-NEXT: PseudoRET implicit $v8 385 %0:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF 386 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s32>), %0 387 $v8 = COPY %1(<vscale x 4 x s1>) 388 PseudoRET implicit $v8 389 390... 391--- 392name: icmp_nxv8i32 393legalized: true 394regBankSelected: true 395tracksRegLiveness: true 396body: | 397 bb.0.entry: 398 ; RV32I-LABEL: name: icmp_nxv8i32 399 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 400 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */ 401 ; RV32I-NEXT: $v8 = COPY %1 402 ; RV32I-NEXT: PseudoRET implicit $v8 403 ; 404 ; RV64I-LABEL: name: icmp_nxv8i32 405 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 406 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */ 407 ; RV64I-NEXT: $v8 = COPY %1 408 ; RV64I-NEXT: PseudoRET implicit $v8 409 %0:vrb(<vscale x 8 x s32>) = G_IMPLICIT_DEF 410 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ule), %0(<vscale x 8 x s32>), %0 411 $v8 = COPY %1(<vscale x 8 x s1>) 412 PseudoRET implicit $v8 413 414... 415--- 416name: icmp_nxv16i32 417legalized: true 418regBankSelected: true 419tracksRegLiveness: true 420body: | 421 bb.0.entry: 422 ; RV32I-LABEL: name: icmp_nxv16i32 423 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 424 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */ 425 ; RV32I-NEXT: $v8 = COPY %1 426 ; RV32I-NEXT: PseudoRET implicit $v8 427 ; 428 ; RV64I-LABEL: name: icmp_nxv16i32 429 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 430 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */ 431 ; RV64I-NEXT: $v8 = COPY %1 432 ; RV64I-NEXT: PseudoRET implicit $v8 433 %0:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF 434 %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sle), %0(<vscale x 16 x s32>), %0 435 $v8 = COPY %1(<vscale x 16 x s1>) 436 PseudoRET implicit $v8 437 438... 439--- 440name: icmp_nxv1i64 441legalized: true 442regBankSelected: true 443tracksRegLiveness: true 444body: | 445 bb.0.entry: 446 ; RV32I-LABEL: name: icmp_nxv1i64 447 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 448 ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */ 449 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] 450 ; RV32I-NEXT: PseudoRET implicit $v8 451 ; 452 ; RV64I-LABEL: name: icmp_nxv1i64 453 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF 454 ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */ 455 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] 456 ; RV64I-NEXT: PseudoRET implicit $v8 457 %0:vrb(<vscale x 1 x s64>) = G_IMPLICIT_DEF 458 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(eq), %0(<vscale x 1 x s64>), %0 459 $v8 = COPY %1(<vscale x 1 x s1>) 460 PseudoRET implicit $v8 461 462... 463--- 464name: icmp_nxv2i64 465legalized: true 466regBankSelected: true 467tracksRegLiveness: true 468body: | 469 bb.0.entry: 470 ; RV32I-LABEL: name: icmp_nxv2i64 471 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 472 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */ 473 ; RV32I-NEXT: $v8 = COPY %1 474 ; RV32I-NEXT: PseudoRET implicit $v8 475 ; 476 ; RV64I-LABEL: name: icmp_nxv2i64 477 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF 478 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */ 479 ; RV64I-NEXT: $v8 = COPY %1 480 ; RV64I-NEXT: PseudoRET implicit $v8 481 %0:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF 482 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ne), %0(<vscale x 2 x s64>), %0 483 $v8 = COPY %1(<vscale x 2 x s1>) 484 PseudoRET implicit $v8 485 486... 487--- 488name: icmp_nxv4i64 489legalized: true 490regBankSelected: true 491tracksRegLiveness: true 492body: | 493 bb.0.entry: 494 ; RV32I-LABEL: name: icmp_nxv4i64 495 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 496 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */ 497 ; RV32I-NEXT: $v8 = COPY %1 498 ; RV32I-NEXT: PseudoRET implicit $v8 499 ; 500 ; RV64I-LABEL: name: icmp_nxv4i64 501 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF 502 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */ 503 ; RV64I-NEXT: $v8 = COPY %1 504 ; RV64I-NEXT: PseudoRET implicit $v8 505 %0:vrb(<vscale x 4 x s64>) = G_IMPLICIT_DEF 506 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(ult), %0(<vscale x 4 x s64>), %0 507 $v8 = COPY %1(<vscale x 4 x s1>) 508 PseudoRET implicit $v8 509 510... 511--- 512name: icmp_nxv8i64 513legalized: true 514regBankSelected: true 515tracksRegLiveness: true 516body: | 517 bb.0.entry: 518 ; RV32I-LABEL: name: icmp_nxv8i64 519 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 520 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */ 521 ; RV32I-NEXT: $v8 = COPY %1 522 ; RV32I-NEXT: PseudoRET implicit $v8 523 ; 524 ; RV64I-LABEL: name: icmp_nxv8i64 525 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF 526 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */ 527 ; RV64I-NEXT: $v8 = COPY %1 528 ; RV64I-NEXT: PseudoRET implicit $v8 529 %0:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF 530 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ult), %0(<vscale x 8 x s64>), %0 531 $v8 = COPY %1(<vscale x 8 x s1>) 532 PseudoRET implicit $v8 533 534... 535